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1&l4_cfg { /* 0x4a000000 */
2 compatible = "ti,dra7-l4-cfg", "simple-bus";
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
6 reg-names = "ap", "la", "ia0";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
12
13 segment@0 { /* 0x4a000000 */
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
18 <0x00000800 0x00000800 0x000800>, /* ap 1 */
19 <0x00001000 0x00001000 0x001000>, /* ap 2 */
20 <0x00002000 0x00002000 0x002000>, /* ap 3 */
21 <0x00004000 0x00004000 0x001000>, /* ap 4 */
22 <0x00005000 0x00005000 0x001000>, /* ap 5 */
23 <0x00006000 0x00006000 0x001000>, /* ap 6 */
24 <0x00008000 0x00008000 0x002000>, /* ap 7 */
25 <0x0000a000 0x0000a000 0x001000>, /* ap 8 */
26 <0x00056000 0x00056000 0x001000>, /* ap 9 */
27 <0x00057000 0x00057000 0x001000>, /* ap 10 */
28 <0x0005e000 0x0005e000 0x002000>, /* ap 11 */
29 <0x00060000 0x00060000 0x001000>, /* ap 12 */
30 <0x00080000 0x00080000 0x008000>, /* ap 13 */
31 <0x00088000 0x00088000 0x001000>, /* ap 14 */
32 <0x000a0000 0x000a0000 0x008000>, /* ap 15 */
33 <0x000a8000 0x000a8000 0x001000>, /* ap 16 */
34 <0x000d9000 0x000d9000 0x001000>, /* ap 17 */
35 <0x000da000 0x000da000 0x001000>, /* ap 18 */
36 <0x000dd000 0x000dd000 0x001000>, /* ap 19 */
37 <0x000de000 0x000de000 0x001000>, /* ap 20 */
38 <0x000e0000 0x000e0000 0x001000>, /* ap 21 */
39 <0x000e1000 0x000e1000 0x001000>, /* ap 22 */
40 <0x000f4000 0x000f4000 0x001000>, /* ap 23 */
41 <0x000f5000 0x000f5000 0x001000>, /* ap 24 */
42 <0x000f6000 0x000f6000 0x001000>, /* ap 25 */
43 <0x000f7000 0x000f7000 0x001000>, /* ap 26 */
44 <0x00090000 0x00090000 0x008000>, /* ap 59 */
45 <0x00098000 0x00098000 0x001000>; /* ap 60 */
46
47 target-module@2000 { /* 0x4a002000, ap 3 08.0 */
48 compatible = "ti,sysc-omap4", "ti,sysc";
49 reg = <0x2000 0x4>;
50 reg-names = "rev";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges = <0x0 0x2000 0x2000>;
54
55 scm: scm@0 {
56 compatible = "ti,dra7-scm-core", "simple-bus";
57 reg = <0 0x2000>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges = <0 0 0x2000>;
61
62 scm_conf: scm_conf@0 {
63 compatible = "syscon", "simple-bus";
64 reg = <0x0 0x1400>;
65 #address-cells = <1>;
66 #size-cells = <1>;
67 ranges = <0 0x0 0x1400>;
68
69 pbias_regulator: pbias_regulator@e00 {
70 compatible = "ti,pbias-dra7", "ti,pbias-omap";
71 reg = <0xe00 0x4>;
72 syscon = <&scm_conf>;
73 pbias_mmc_reg: pbias_mmc_omap5 {
74 regulator-name = "pbias_mmc_omap5";
75 regulator-min-microvolt = <1800000>;
76 regulator-max-microvolt = <3300000>;
77 };
78 };
79
80 phy_gmii_sel: phy-gmii-sel {
81 compatible = "ti,dra7xx-phy-gmii-sel";
82 reg = <0x554 0x4>;
83 #phy-cells = <1>;
84 };
85
86 scm_conf_clocks: clocks {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 };
90 };
91
92 dra7_pmx_core: pinmux@1400 {
93 compatible = "ti,dra7-padconf",
94 "pinctrl-single";
95 reg = <0x1400 0x0468>;
96 #address-cells = <1>;
97 #size-cells = <0>;
98 #pinctrl-cells = <1>;
99 #interrupt-cells = <1>;
100 interrupt-controller;
101 pinctrl-single,register-width = <32>;
102 pinctrl-single,function-mask = <0x3fffffff>;
103 };
104
105 scm_conf1: scm_conf@1c04 {
106 compatible = "syscon";
107 reg = <0x1c04 0x0020>;
108 #syscon-cells = <2>;
109 };
110
111 scm_conf_pcie: scm_conf@1c24 {
112 compatible = "syscon";
113 reg = <0x1c24 0x0024>;
114 };
115
116 sdma_xbar: dma-router@b78 {
117 compatible = "ti,dra7-dma-crossbar";
118 reg = <0xb78 0xfc>;
119 #dma-cells = <1>;
120 dma-requests = <205>;
121 ti,dma-safe-map = <0>;
122 dma-masters = <&sdma>;
123 };
124
125 edma_xbar: dma-router@c78 {
126 compatible = "ti,dra7-dma-crossbar";
127 reg = <0xc78 0x7c>;
128 #dma-cells = <2>;
129 dma-requests = <204>;
130 ti,dma-safe-map = <0>;
131 dma-masters = <&edma>;
132 };
133 };
134 };
135
136 target-module@5000 { /* 0x4a005000, ap 5 10.0 */
137 compatible = "ti,sysc-omap4", "ti,sysc";
138 reg = <0x5000 0x4>;
139 reg-names = "rev";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0x0 0x5000 0x1000>;
143
144 cm_core_aon: cm_core_aon@0 {
145 compatible = "ti,dra7-cm-core-aon",
146 "simple-bus";
147 #address-cells = <1>;
148 #size-cells = <1>;
149 reg = <0 0x2000>;
150 ranges = <0 0 0x2000>;
151
152 cm_core_aon_clocks: clocks {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 };
156
157 cm_core_aon_clockdomains: clockdomains {
158 };
159 };
160 };
161
162 target-module@8000 { /* 0x4a008000, ap 7 0e.0 */
163 compatible = "ti,sysc-omap4", "ti,sysc";
164 reg = <0x8000 0x4>;
165 reg-names = "rev";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges = <0x0 0x8000 0x2000>;
169
170 cm_core: cm_core@0 {
171 compatible = "ti,dra7-cm-core", "simple-bus";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0 0x3000>;
175 ranges = <0 0 0x3000>;
176
177 cm_core_clocks: clocks {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 };
181
182 cm_core_clockdomains: clockdomains {
183 };
184 };
185 };
186
187 target-module@56000 { /* 0x4a056000, ap 9 02.0 */
188 compatible = "ti,sysc-omap2", "ti,sysc";
189 ti,hwmods = "dma_system";
190 reg = <0x56000 0x4>,
191 <0x5602c 0x4>,
192 <0x56028 0x4>;
193 reg-names = "rev", "sysc", "syss";
194 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
195 SYSC_OMAP2_EMUFREE |
196 SYSC_OMAP2_SOFTRESET |
197 SYSC_OMAP2_AUTOIDLE)>;
198 ti,sysc-midle = <SYSC_IDLE_FORCE>,
199 <SYSC_IDLE_NO>,
200 <SYSC_IDLE_SMART>,
201 <SYSC_IDLE_SMART_WKUP>;
202 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
203 <SYSC_IDLE_NO>,
204 <SYSC_IDLE_SMART>,
205 <SYSC_IDLE_SMART_WKUP>;
206 ti,syss-mask = <1>;
207 /* Domains (P, C): core_pwrdm, dma_clkdm */
208 clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
209 clock-names = "fck";
210 #address-cells = <1>;
211 #size-cells = <1>;
212 ranges = <0x0 0x56000 0x1000>;
213
214 sdma: dma-controller@0 {
215 compatible = "ti,omap4430-sdma";
216 reg = <0x0 0x1000>;
217 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
221 #dma-cells = <1>;
222 dma-channels = <32>;
223 dma-requests = <127>;
224 };
225 };
226
227 target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
228 compatible = "ti,sysc";
229 status = "disabled";
230 #address-cells = <1>;
231 #size-cells = <1>;
232 ranges = <0x0 0x5e000 0x2000>;
233 };
234
235 target-module@80000 { /* 0x4a080000, ap 13 20.0 */
236 compatible = "ti,sysc-omap2", "ti,sysc";
237 ti,hwmods = "ocp2scp1";
238 reg = <0x80000 0x4>,
239 <0x80010 0x4>,
240 <0x80014 0x4>;
241 reg-names = "rev", "sysc", "syss";
242 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
243 SYSC_OMAP2_AUTOIDLE)>;
244 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
245 <SYSC_IDLE_NO>,
246 <SYSC_IDLE_SMART>;
247 ti,syss-mask = <1>;
248 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
249 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
250 clock-names = "fck";
251 #address-cells = <1>;
252 #size-cells = <1>;
253 ranges = <0x0 0x80000 0x8000>;
254
255 ocp2scp@0 {
256 compatible = "ti,omap-ocp2scp";
257 #address-cells = <1>;
258 #size-cells = <1>;
259 ranges = <0 0 0x8000>;
260 reg = <0x0 0x20>;
261
262 usb2_phy1: phy@4000 {
263 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
264 reg = <0x4000 0x400>;
265 syscon-phy-power = <&scm_conf 0x300>;
266 clocks = <&usb_phy1_always_on_clk32k>,
267 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
268 clock-names = "wkupclk",
269 "refclk";
270 #phy-cells = <0>;
271 };
272
273 usb2_phy2: phy@5000 {
274 compatible = "ti,dra7x-usb2-phy2",
275 "ti,omap-usb2";
276 reg = <0x5000 0x400>;
277 syscon-phy-power = <&scm_conf 0xe74>;
278 clocks = <&usb_phy2_always_on_clk32k>,
279 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
280 clock-names = "wkupclk",
281 "refclk";
282 #phy-cells = <0>;
283 };
284
285 usb3_phy1: phy@4400 {
286 compatible = "ti,omap-usb3";
287 reg = <0x4400 0x80>,
288 <0x4800 0x64>,
289 <0x4c00 0x40>;
290 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
291 syscon-phy-power = <&scm_conf 0x370>;
292 clocks = <&usb_phy3_always_on_clk32k>,
293 <&sys_clkin1>,
294 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
295 clock-names = "wkupclk",
296 "sysclk",
297 "refclk";
298 #phy-cells = <0>;
299 };
300 };
301 };
302
303 target-module@90000 { /* 0x4a090000, ap 59 42.0 */
304 compatible = "ti,sysc-omap2", "ti,sysc";
305 ti,hwmods = "ocp2scp3";
306 reg = <0x90000 0x4>,
307 <0x90010 0x4>,
308 <0x90014 0x4>;
309 reg-names = "rev", "sysc", "syss";
310 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
311 SYSC_OMAP2_AUTOIDLE)>;
312 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
313 <SYSC_IDLE_NO>,
314 <SYSC_IDLE_SMART>;
315 ti,syss-mask = <1>;
316 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
317 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
318 clock-names = "fck";
319 #address-cells = <1>;
320 #size-cells = <1>;
321 ranges = <0x0 0x90000 0x8000>;
322
323 ocp2scp@0 {
324 compatible = "ti,omap-ocp2scp";
325 #address-cells = <1>;
326 #size-cells = <1>;
327 ranges = <0 0 0x8000>;
328 reg = <0x0 0x20>;
329
330 pcie1_phy: pciephy@4000 {
331 compatible = "ti,phy-pipe3-pcie";
332 reg = <0x4000 0x80>, /* phy_rx */
333 <0x4400 0x64>; /* phy_tx */
334 reg-names = "phy_rx", "phy_tx";
335 syscon-phy-power = <&scm_conf_pcie 0x1c>;
336 syscon-pcs = <&scm_conf_pcie 0x10>;
337 clocks = <&dpll_pcie_ref_ck>,
338 <&dpll_pcie_ref_m2ldo_ck>,
339 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
340 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
341 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
342 <&optfclk_pciephy_div>,
343 <&sys_clkin1>;
344 clock-names = "dpll_ref", "dpll_ref_m2",
345 "wkupclk", "refclk",
346 "div-clk", "phy-div", "sysclk";
347 #phy-cells = <0>;
348 };
349
350 pcie2_phy: pciephy@5000 {
351 compatible = "ti,phy-pipe3-pcie";
352 reg = <0x5000 0x80>, /* phy_rx */
353 <0x5400 0x64>; /* phy_tx */
354 reg-names = "phy_rx", "phy_tx";
355 syscon-phy-power = <&scm_conf_pcie 0x20>;
356 syscon-pcs = <&scm_conf_pcie 0x10>;
357 clocks = <&dpll_pcie_ref_ck>,
358 <&dpll_pcie_ref_m2ldo_ck>,
359 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
360 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
361 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
362 <&optfclk_pciephy_div>,
363 <&sys_clkin1>;
364 clock-names = "dpll_ref", "dpll_ref_m2",
365 "wkupclk", "refclk",
366 "div-clk", "phy-div", "sysclk";
367 #phy-cells = <0>;
368 status = "disabled";
369 };
370
371 sata_phy: phy@6000 {
372 compatible = "ti,phy-pipe3-sata";
373 reg = <0x6000 0x80>, /* phy_rx */
374 <0x6400 0x64>, /* phy_tx */
375 <0x6800 0x40>; /* pll_ctrl */
376 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
377 syscon-phy-power = <&scm_conf 0x374>;
378 clocks = <&sys_clkin1>,
379 <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
380 clock-names = "sysclk", "refclk";
381 syscon-pllreset = <&scm_conf 0x3fc>;
382 #phy-cells = <0>;
383 };
384 };
385 };
386
387 target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
388 compatible = "ti,sysc";
389 status = "disabled";
390 #address-cells = <1>;
391 #size-cells = <1>;
392 ranges = <0x0 0xa0000 0x8000>;
393 };
394
395 target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
396 compatible = "ti,sysc-omap4-sr", "ti,sysc";
397 ti,hwmods = "smartreflex_mpu";
398 reg = <0xd9038 0x4>;
399 reg-names = "sysc";
400 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
401 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
402 <SYSC_IDLE_NO>,
403 <SYSC_IDLE_SMART>,
404 <SYSC_IDLE_SMART_WKUP>;
405 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
406 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
407 clock-names = "fck";
408 #address-cells = <1>;
409 #size-cells = <1>;
410 ranges = <0x0 0xd9000 0x1000>;
411
412 /* SmartReflex child device marked reserved in TRM */
413 };
414
415 target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
416 compatible = "ti,sysc-omap4-sr", "ti,sysc";
417 ti,hwmods = "smartreflex_core";
418 reg = <0xdd038 0x4>;
419 reg-names = "sysc";
420 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
421 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
422 <SYSC_IDLE_NO>,
423 <SYSC_IDLE_SMART>,
424 <SYSC_IDLE_SMART_WKUP>;
425 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
426 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
427 clock-names = "fck";
428 #address-cells = <1>;
429 #size-cells = <1>;
430 ranges = <0x0 0xdd000 0x1000>;
431
432 /* SmartReflex child device marked reserved in TRM */
433 };
434
435 target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
436 compatible = "ti,sysc";
437 status = "disabled";
438 #address-cells = <1>;
439 #size-cells = <1>;
440 ranges = <0x0 0xe0000 0x1000>;
441 };
442
443 target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
444 compatible = "ti,sysc-omap4", "ti,sysc";
445 ti,hwmods = "mailbox1";
446 reg = <0xf4000 0x4>,
447 <0xf4010 0x4>;
448 reg-names = "rev", "sysc";
449 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
450 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
451 <SYSC_IDLE_NO>,
452 <SYSC_IDLE_SMART>;
453 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
454 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
455 clock-names = "fck";
456 #address-cells = <1>;
457 #size-cells = <1>;
458 ranges = <0x0 0xf4000 0x1000>;
459
460 mailbox1: mailbox@0 {
461 compatible = "ti,omap4-mailbox";
462 reg = <0x0 0x200>;
463 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
466 #mbox-cells = <1>;
467 ti,mbox-num-users = <3>;
468 ti,mbox-num-fifos = <8>;
469 status = "disabled";
470 };
471 };
472
473 target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
474 compatible = "ti,sysc-omap2", "ti,sysc";
475 ti,hwmods = "spinlock";
476 reg = <0xf6000 0x4>,
477 <0xf6010 0x4>,
478 <0xf6014 0x4>;
479 reg-names = "rev", "sysc", "syss";
480 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
481 SYSC_OMAP2_SOFTRESET |
482 SYSC_OMAP2_AUTOIDLE)>;
483 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
484 <SYSC_IDLE_NO>,
485 <SYSC_IDLE_SMART>;
486 ti,syss-mask = <1>;
487 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
488 clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
489 clock-names = "fck";
490 #address-cells = <1>;
491 #size-cells = <1>;
492 ranges = <0x0 0xf6000 0x1000>;
493
494 hwspinlock: spinlock@0 {
495 compatible = "ti,omap4-hwspinlock";
496 reg = <0x0 0x1000>;
497 #hwlock-cells = <1>;
498 };
499 };
500 };
501
502 segment@100000 { /* 0x4a100000 */
503 compatible = "simple-bus";
504 #address-cells = <1>;
505 #size-cells = <1>;
506 ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
507 <0x00003000 0x00103000 0x001000>, /* ap 28 */
508 <0x00008000 0x00108000 0x001000>, /* ap 29 */
509 <0x00009000 0x00109000 0x001000>, /* ap 30 */
510 <0x00040000 0x00140000 0x010000>, /* ap 31 */
511 <0x00050000 0x00150000 0x001000>, /* ap 32 */
512 <0x00051000 0x00151000 0x001000>, /* ap 33 */
513 <0x00052000 0x00152000 0x001000>, /* ap 34 */
514 <0x00053000 0x00153000 0x001000>, /* ap 35 */
515 <0x00054000 0x00154000 0x001000>, /* ap 36 */
516 <0x00055000 0x00155000 0x001000>, /* ap 37 */
517 <0x00056000 0x00156000 0x001000>, /* ap 38 */
518 <0x00057000 0x00157000 0x001000>, /* ap 39 */
519 <0x00058000 0x00158000 0x001000>, /* ap 40 */
520 <0x0005b000 0x0015b000 0x001000>, /* ap 41 */
521 <0x0005c000 0x0015c000 0x001000>, /* ap 42 */
522 <0x0005d000 0x0015d000 0x001000>, /* ap 45 */
523 <0x0005e000 0x0015e000 0x001000>, /* ap 46 */
524 <0x0005f000 0x0015f000 0x001000>, /* ap 47 */
525 <0x00060000 0x00160000 0x001000>, /* ap 48 */
526 <0x00061000 0x00161000 0x001000>, /* ap 49 */
527 <0x00062000 0x00162000 0x001000>, /* ap 50 */
528 <0x00063000 0x00163000 0x001000>, /* ap 51 */
529 <0x00064000 0x00164000 0x001000>, /* ap 52 */
530 <0x00065000 0x00165000 0x001000>, /* ap 53 */
531 <0x00066000 0x00166000 0x001000>, /* ap 54 */
532 <0x00067000 0x00167000 0x001000>, /* ap 55 */
533 <0x00068000 0x00168000 0x001000>, /* ap 56 */
534 <0x0006d000 0x0016d000 0x001000>, /* ap 57 */
535 <0x0006e000 0x0016e000 0x001000>, /* ap 58 */
536 <0x00071000 0x00171000 0x001000>, /* ap 61 */
537 <0x00072000 0x00172000 0x001000>, /* ap 62 */
538 <0x00073000 0x00173000 0x001000>, /* ap 63 */
539 <0x00074000 0x00174000 0x001000>, /* ap 64 */
540 <0x00075000 0x00175000 0x001000>, /* ap 65 */
541 <0x00076000 0x00176000 0x001000>, /* ap 66 */
542 <0x00077000 0x00177000 0x001000>, /* ap 67 */
543 <0x00078000 0x00178000 0x001000>, /* ap 68 */
544 <0x00081000 0x00181000 0x001000>, /* ap 69 */
545 <0x00082000 0x00182000 0x001000>, /* ap 70 */
546 <0x00083000 0x00183000 0x001000>, /* ap 71 */
547 <0x00084000 0x00184000 0x001000>, /* ap 72 */
548 <0x00085000 0x00185000 0x001000>, /* ap 73 */
549 <0x00086000 0x00186000 0x001000>, /* ap 74 */
550 <0x00087000 0x00187000 0x001000>, /* ap 75 */
551 <0x00088000 0x00188000 0x001000>, /* ap 76 */
552 <0x00069000 0x00169000 0x001000>, /* ap 103 */
553 <0x0006a000 0x0016a000 0x001000>, /* ap 104 */
554 <0x00079000 0x00179000 0x001000>, /* ap 105 */
555 <0x0007a000 0x0017a000 0x001000>, /* ap 106 */
556 <0x0006b000 0x0016b000 0x001000>, /* ap 107 */
557 <0x0006c000 0x0016c000 0x001000>, /* ap 108 */
558 <0x0007b000 0x0017b000 0x001000>, /* ap 121 */
559 <0x0007c000 0x0017c000 0x001000>, /* ap 122 */
560 <0x0007d000 0x0017d000 0x001000>, /* ap 123 */
561 <0x0007e000 0x0017e000 0x001000>, /* ap 124 */
562 <0x00059000 0x00159000 0x001000>, /* ap 125 */
563 <0x0005a000 0x0015a000 0x001000>; /* ap 126 */
564
565 target-module@2000 { /* 0x4a102000, ap 27 3c.0 */
566 compatible = "ti,sysc";
567 status = "disabled";
568 #address-cells = <1>;
569 #size-cells = <1>;
570 ranges = <0x0 0x2000 0x1000>;
571 };
572
573 target-module@8000 { /* 0x4a108000, ap 29 1e.0 */
574 compatible = "ti,sysc";
575 status = "disabled";
576 #address-cells = <1>;
577 #size-cells = <1>;
578 ranges = <0x0 0x8000 0x1000>;
579 };
580
581 target-module@40000 { /* 0x4a140000, ap 31 06.0 */
582 compatible = "ti,sysc";
583 status = "disabled";
584 #address-cells = <1>;
585 #size-cells = <1>;
586 ranges = <0x0 0x40000 0x10000>;
587 };
588
589 target-module@51000 { /* 0x4a151000, ap 33 50.0 */
590 compatible = "ti,sysc";
591 status = "disabled";
592 #address-cells = <1>;
593 #size-cells = <1>;
594 ranges = <0x0 0x51000 0x1000>;
595 };
596
597 target-module@53000 { /* 0x4a153000, ap 35 54.0 */
598 compatible = "ti,sysc";
599 status = "disabled";
600 #address-cells = <1>;
601 #size-cells = <1>;
602 ranges = <0x0 0x53000 0x1000>;
603 };
604
605 target-module@55000 { /* 0x4a155000, ap 37 46.0 */
606 compatible = "ti,sysc";
607 status = "disabled";
608 #address-cells = <1>;
609 #size-cells = <1>;
610 ranges = <0x0 0x55000 0x1000>;
611 };
612
613 target-module@57000 { /* 0x4a157000, ap 39 58.0 */
614 compatible = "ti,sysc";
615 status = "disabled";
616 #address-cells = <1>;
617 #size-cells = <1>;
618 ranges = <0x0 0x57000 0x1000>;
619 };
620
621 target-module@59000 { /* 0x4a159000, ap 125 6a.0 */
622 compatible = "ti,sysc";
623 status = "disabled";
624 #address-cells = <1>;
625 #size-cells = <1>;
626 ranges = <0x0 0x59000 0x1000>;
627 };
628
629 target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */
630 compatible = "ti,sysc";
631 status = "disabled";
632 #address-cells = <1>;
633 #size-cells = <1>;
634 ranges = <0x0 0x5b000 0x1000>;
635 };
636
637 target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */
638 compatible = "ti,sysc";
639 status = "disabled";
640 #address-cells = <1>;
641 #size-cells = <1>;
642 ranges = <0x0 0x5d000 0x1000>;
643 };
644
645 target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */
646 compatible = "ti,sysc";
647 status = "disabled";
648 #address-cells = <1>;
649 #size-cells = <1>;
650 ranges = <0x0 0x5f000 0x1000>;
651 };
652
653 target-module@61000 { /* 0x4a161000, ap 49 32.0 */
654 compatible = "ti,sysc";
655 status = "disabled";
656 #address-cells = <1>;
657 #size-cells = <1>;
658 ranges = <0x0 0x61000 0x1000>;
659 };
660
661 target-module@63000 { /* 0x4a163000, ap 51 5c.0 */
662 compatible = "ti,sysc";
663 status = "disabled";
664 #address-cells = <1>;
665 #size-cells = <1>;
666 ranges = <0x0 0x63000 0x1000>;
667 };
668
669 target-module@65000 { /* 0x4a165000, ap 53 4e.0 */
670 compatible = "ti,sysc";
671 status = "disabled";
672 #address-cells = <1>;
673 #size-cells = <1>;
674 ranges = <0x0 0x65000 0x1000>;
675 };
676
677 target-module@67000 { /* 0x4a167000, ap 55 5e.0 */
678 compatible = "ti,sysc";
679 status = "disabled";
680 #address-cells = <1>;
681 #size-cells = <1>;
682 ranges = <0x0 0x67000 0x1000>;
683 };
684
685 target-module@69000 { /* 0x4a169000, ap 103 4a.0 */
686 compatible = "ti,sysc";
687 status = "disabled";
688 #address-cells = <1>;
689 #size-cells = <1>;
690 ranges = <0x0 0x69000 0x1000>;
691 };
692
693 target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */
694 compatible = "ti,sysc";
695 status = "disabled";
696 #address-cells = <1>;
697 #size-cells = <1>;
698 ranges = <0x0 0x6b000 0x1000>;
699 };
700
701 target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */
702 compatible = "ti,sysc";
703 status = "disabled";
704 #address-cells = <1>;
705 #size-cells = <1>;
706 ranges = <0x0 0x6d000 0x1000>;
707 };
708
709 target-module@71000 { /* 0x4a171000, ap 61 48.0 */
710 compatible = "ti,sysc";
711 status = "disabled";
712 #address-cells = <1>;
713 #size-cells = <1>;
714 ranges = <0x0 0x71000 0x1000>;
715 };
716
717 target-module@73000 { /* 0x4a173000, ap 63 2a.0 */
718 compatible = "ti,sysc";
719 status = "disabled";
720 #address-cells = <1>;
721 #size-cells = <1>;
722 ranges = <0x0 0x73000 0x1000>;
723 };
724
725 target-module@75000 { /* 0x4a175000, ap 65 64.0 */
726 compatible = "ti,sysc";
727 status = "disabled";
728 #address-cells = <1>;
729 #size-cells = <1>;
730 ranges = <0x0 0x75000 0x1000>;
731 };
732
733 target-module@77000 { /* 0x4a177000, ap 67 66.0 */
734 compatible = "ti,sysc";
735 status = "disabled";
736 #address-cells = <1>;
737 #size-cells = <1>;
738 ranges = <0x0 0x77000 0x1000>;
739 };
740
741 target-module@79000 { /* 0x4a179000, ap 105 34.0 */
742 compatible = "ti,sysc";
743 status = "disabled";
744 #address-cells = <1>;
745 #size-cells = <1>;
746 ranges = <0x0 0x79000 0x1000>;
747 };
748
749 target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */
750 compatible = "ti,sysc";
751 status = "disabled";
752 #address-cells = <1>;
753 #size-cells = <1>;
754 ranges = <0x0 0x7b000 0x1000>;
755 };
756
757 target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */
758 compatible = "ti,sysc";
759 status = "disabled";
760 #address-cells = <1>;
761 #size-cells = <1>;
762 ranges = <0x0 0x7d000 0x1000>;
763 };
764
765 target-module@81000 { /* 0x4a181000, ap 69 26.0 */
766 compatible = "ti,sysc";
767 status = "disabled";
768 #address-cells = <1>;
769 #size-cells = <1>;
770 ranges = <0x0 0x81000 0x1000>;
771 };
772
773 target-module@83000 { /* 0x4a183000, ap 71 2e.0 */
774 compatible = "ti,sysc";
775 status = "disabled";
776 #address-cells = <1>;
777 #size-cells = <1>;
778 ranges = <0x0 0x83000 0x1000>;
779 };
780
781 target-module@85000 { /* 0x4a185000, ap 73 36.0 */
782 compatible = "ti,sysc";
783 status = "disabled";
784 #address-cells = <1>;
785 #size-cells = <1>;
786 ranges = <0x0 0x85000 0x1000>;
787 };
788
789 target-module@87000 { /* 0x4a187000, ap 75 74.0 */
790 compatible = "ti,sysc";
791 status = "disabled";
792 #address-cells = <1>;
793 #size-cells = <1>;
794 ranges = <0x0 0x87000 0x1000>;
795 };
796 };
797
798 segment@200000 { /* 0x4a200000 */
799 compatible = "simple-bus";
800 #address-cells = <1>;
801 #size-cells = <1>;
802 ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
803 <0x00019000 0x00219000 0x001000>, /* ap 44 */
804 <0x00000000 0x00200000 0x001000>, /* ap 77 */
805 <0x00001000 0x00201000 0x001000>, /* ap 78 */
806 <0x0000a000 0x0020a000 0x001000>, /* ap 79 */
807 <0x0000b000 0x0020b000 0x001000>, /* ap 80 */
808 <0x0000c000 0x0020c000 0x001000>, /* ap 81 */
809 <0x0000d000 0x0020d000 0x001000>, /* ap 82 */
810 <0x0000e000 0x0020e000 0x001000>, /* ap 83 */
811 <0x0000f000 0x0020f000 0x001000>, /* ap 84 */
812 <0x00010000 0x00210000 0x001000>, /* ap 85 */
813 <0x00011000 0x00211000 0x001000>, /* ap 86 */
814 <0x00012000 0x00212000 0x001000>, /* ap 87 */
815 <0x00013000 0x00213000 0x001000>, /* ap 88 */
816 <0x00014000 0x00214000 0x001000>, /* ap 89 */
817 <0x00015000 0x00215000 0x001000>, /* ap 90 */
818 <0x0002a000 0x0022a000 0x001000>, /* ap 91 */
819 <0x0002b000 0x0022b000 0x001000>, /* ap 92 */
820 <0x0001c000 0x0021c000 0x001000>, /* ap 93 */
821 <0x0001d000 0x0021d000 0x001000>, /* ap 94 */
822 <0x0001e000 0x0021e000 0x001000>, /* ap 95 */
823 <0x0001f000 0x0021f000 0x001000>, /* ap 96 */
824 <0x00020000 0x00220000 0x001000>, /* ap 97 */
825 <0x00021000 0x00221000 0x001000>, /* ap 98 */
826 <0x00024000 0x00224000 0x001000>, /* ap 99 */
827 <0x00025000 0x00225000 0x001000>, /* ap 100 */
828 <0x00026000 0x00226000 0x001000>, /* ap 101 */
829 <0x00027000 0x00227000 0x001000>, /* ap 102 */
830 <0x0002c000 0x0022c000 0x001000>, /* ap 109 */
831 <0x0002d000 0x0022d000 0x001000>, /* ap 110 */
832 <0x0002e000 0x0022e000 0x001000>, /* ap 111 */
833 <0x0002f000 0x0022f000 0x001000>, /* ap 112 */
834 <0x00030000 0x00230000 0x001000>, /* ap 113 */
835 <0x00031000 0x00231000 0x001000>, /* ap 114 */
836 <0x00032000 0x00232000 0x001000>, /* ap 115 */
837 <0x00033000 0x00233000 0x001000>, /* ap 116 */
838 <0x00034000 0x00234000 0x001000>, /* ap 117 */
839 <0x00035000 0x00235000 0x001000>, /* ap 118 */
840 <0x00036000 0x00236000 0x001000>, /* ap 119 */
841 <0x00037000 0x00237000 0x001000>, /* ap 120 */
842 <0x0001a000 0x0021a000 0x001000>, /* ap 127 */
843 <0x0001b000 0x0021b000 0x001000>; /* ap 128 */
844
845 target-module@0 { /* 0x4a200000, ap 77 3e.0 */
846 compatible = "ti,sysc";
847 status = "disabled";
848 #address-cells = <1>;
849 #size-cells = <1>;
850 ranges = <0x0 0x0 0x1000>;
851 };
852
853 target-module@a000 { /* 0x4a20a000, ap 79 30.0 */
854 compatible = "ti,sysc";
855 status = "disabled";
856 #address-cells = <1>;
857 #size-cells = <1>;
858 ranges = <0x0 0xa000 0x1000>;
859 };
860
861 target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */
862 compatible = "ti,sysc";
863 status = "disabled";
864 #address-cells = <1>;
865 #size-cells = <1>;
866 ranges = <0x0 0xc000 0x1000>;
867 };
868
869 target-module@e000 { /* 0x4a20e000, ap 83 22.0 */
870 compatible = "ti,sysc";
871 status = "disabled";
872 #address-cells = <1>;
873 #size-cells = <1>;
874 ranges = <0x0 0xe000 0x1000>;
875 };
876
877 target-module@10000 { /* 0x4a210000, ap 85 14.0 */
878 compatible = "ti,sysc";
879 status = "disabled";
880 #address-cells = <1>;
881 #size-cells = <1>;
882 ranges = <0x0 0x10000 0x1000>;
883 };
884
885 target-module@12000 { /* 0x4a212000, ap 87 16.0 */
886 compatible = "ti,sysc";
887 status = "disabled";
888 #address-cells = <1>;
889 #size-cells = <1>;
890 ranges = <0x0 0x12000 0x1000>;
891 };
892
893 target-module@14000 { /* 0x4a214000, ap 89 1c.0 */
894 compatible = "ti,sysc";
895 status = "disabled";
896 #address-cells = <1>;
897 #size-cells = <1>;
898 ranges = <0x0 0x14000 0x1000>;
899 };
900
901 target-module@18000 { /* 0x4a218000, ap 43 12.0 */
902 compatible = "ti,sysc";
903 status = "disabled";
904 #address-cells = <1>;
905 #size-cells = <1>;
906 ranges = <0x0 0x18000 0x1000>;
907 };
908
909 target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */
910 compatible = "ti,sysc";
911 status = "disabled";
912 #address-cells = <1>;
913 #size-cells = <1>;
914 ranges = <0x0 0x1a000 0x1000>;
915 };
916
917 target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */
918 compatible = "ti,sysc";
919 status = "disabled";
920 #address-cells = <1>;
921 #size-cells = <1>;
922 ranges = <0x0 0x1c000 0x1000>;
923 };
924
925 target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */
926 compatible = "ti,sysc";
927 status = "disabled";
928 #address-cells = <1>;
929 #size-cells = <1>;
930 ranges = <0x0 0x1e000 0x1000>;
931 };
932
933 target-module@20000 { /* 0x4a220000, ap 97 24.0 */
934 compatible = "ti,sysc";
935 status = "disabled";
936 #address-cells = <1>;
937 #size-cells = <1>;
938 ranges = <0x0 0x20000 0x1000>;
939 };
940
941 target-module@24000 { /* 0x4a224000, ap 99 44.0 */
942 compatible = "ti,sysc";
943 status = "disabled";
944 #address-cells = <1>;
945 #size-cells = <1>;
946 ranges = <0x0 0x24000 0x1000>;
947 };
948
949 target-module@26000 { /* 0x4a226000, ap 101 2c.0 */
950 compatible = "ti,sysc";
951 status = "disabled";
952 #address-cells = <1>;
953 #size-cells = <1>;
954 ranges = <0x0 0x26000 0x1000>;
955 };
956
957 target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */
958 compatible = "ti,sysc";
959 status = "disabled";
960 #address-cells = <1>;
961 #size-cells = <1>;
962 ranges = <0x0 0x2a000 0x1000>;
963 };
964
965 target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */
966 compatible = "ti,sysc";
967 status = "disabled";
968 #address-cells = <1>;
969 #size-cells = <1>;
970 ranges = <0x0 0x2c000 0x1000>;
971 };
972
973 target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */
974 compatible = "ti,sysc";
975 status = "disabled";
976 #address-cells = <1>;
977 #size-cells = <1>;
978 ranges = <0x0 0x2e000 0x1000>;
979 };
980
981 target-module@30000 { /* 0x4a230000, ap 113 70.0 */
982 compatible = "ti,sysc";
983 status = "disabled";
984 #address-cells = <1>;
985 #size-cells = <1>;
986 ranges = <0x0 0x30000 0x1000>;
987 };
988
989 target-module@32000 { /* 0x4a232000, ap 115 5a.0 */
990 compatible = "ti,sysc";
991 status = "disabled";
992 #address-cells = <1>;
993 #size-cells = <1>;
994 ranges = <0x0 0x32000 0x1000>;
995 };
996
997 target-module@34000 { /* 0x4a234000, ap 117 76.1 */
998 compatible = "ti,sysc";
999 status = "disabled";
1000 #address-cells = <1>;
1001 #size-cells = <1>;
1002 ranges = <0x0 0x34000 0x1000>;
1003 };
1004
1005 target-module@36000 { /* 0x4a236000, ap 119 62.0 */
1006 compatible = "ti,sysc";
1007 status = "disabled";
1008 #address-cells = <1>;
1009 #size-cells = <1>;
1010 ranges = <0x0 0x36000 0x1000>;
1011 };
1012 };
1013};
1014
1015&l4_per1 { /* 0x48000000 */
1016 compatible = "ti,dra7-l4-per1", "simple-bus";
1017 reg = <0x48000000 0x800>,
1018 <0x48000800 0x800>,
1019 <0x48001000 0x400>,
1020 <0x48001400 0x400>,
1021 <0x48001800 0x400>,
1022 <0x48001c00 0x400>;
1023 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1024 #address-cells = <1>;
1025 #size-cells = <1>;
1026 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1027 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1028
1029 segment@0 { /* 0x48000000 */
1030 compatible = "simple-bus";
1031 #address-cells = <1>;
1032 #size-cells = <1>;
1033 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1034 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1035 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1036 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1037 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1038 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1039 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1040 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1041 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1042 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1043 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1044 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1045 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1046 <0x00055000 0x00055000 0x001000>, /* ap 13 */
1047 <0x00056000 0x00056000 0x001000>, /* ap 14 */
1048 <0x00057000 0x00057000 0x001000>, /* ap 15 */
1049 <0x00058000 0x00058000 0x001000>, /* ap 16 */
1050 <0x00059000 0x00059000 0x001000>, /* ap 17 */
1051 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
1052 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
1053 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
1054 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
1055 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
1056 <0x00060000 0x00060000 0x001000>, /* ap 23 */
1057 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
1058 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
1059 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
1060 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
1061 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
1062 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
1063 <0x00070000 0x00070000 0x001000>, /* ap 30 */
1064 <0x00071000 0x00071000 0x001000>, /* ap 31 */
1065 <0x00072000 0x00072000 0x001000>, /* ap 32 */
1066 <0x00073000 0x00073000 0x001000>, /* ap 33 */
1067 <0x00061000 0x00061000 0x001000>, /* ap 34 */
1068 <0x00053000 0x00053000 0x001000>, /* ap 35 */
1069 <0x00054000 0x00054000 0x001000>, /* ap 36 */
1070 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
1071 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
1072 <0x00078000 0x00078000 0x001000>, /* ap 39 */
1073 <0x00079000 0x00079000 0x001000>, /* ap 40 */
1074 <0x00086000 0x00086000 0x001000>, /* ap 41 */
1075 <0x00087000 0x00087000 0x001000>, /* ap 42 */
1076 <0x00088000 0x00088000 0x001000>, /* ap 43 */
1077 <0x00089000 0x00089000 0x001000>, /* ap 44 */
1078 <0x00051000 0x00051000 0x001000>, /* ap 45 */
1079 <0x00052000 0x00052000 0x001000>, /* ap 46 */
1080 <0x00098000 0x00098000 0x001000>, /* ap 47 */
1081 <0x00099000 0x00099000 0x001000>, /* ap 48 */
1082 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
1083 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
1084 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
1085 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
1086 <0x00068000 0x00068000 0x001000>, /* ap 53 */
1087 <0x00069000 0x00069000 0x001000>, /* ap 54 */
1088 <0x00090000 0x00090000 0x002000>, /* ap 55 */
1089 <0x00092000 0x00092000 0x001000>, /* ap 56 */
1090 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1091 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1092 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1093 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1094 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1095 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1096 <0x00066000 0x00066000 0x001000>, /* ap 63 */
1097 <0x00067000 0x00067000 0x001000>, /* ap 64 */
1098 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1099 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1100 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1101 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1102 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1103 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1104 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1105 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1106 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1107 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1108 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1109 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1110 <0x00001400 0x00001400 0x000400>, /* ap 77 */
1111 <0x00001800 0x00001800 0x000400>, /* ap 78 */
1112 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1113 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1114 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1115 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1116 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1117 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1118
1119 target-module@20000 { /* 0x48020000, ap 3 04.0 */
1120 compatible = "ti,sysc-omap2", "ti,sysc";
1121 reg = <0x20050 0x4>,
1122 <0x20054 0x4>,
1123 <0x20058 0x4>;
1124 reg-names = "rev", "sysc", "syss";
1125 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1126 SYSC_OMAP2_SOFTRESET |
1127 SYSC_OMAP2_AUTOIDLE)>;
1128 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1129 <SYSC_IDLE_NO>,
1130 <SYSC_IDLE_SMART>,
1131 <SYSC_IDLE_SMART_WKUP>;
1132 ti,syss-mask = <1>;
1133 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1134 clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1135 clock-names = "fck";
1136 #address-cells = <1>;
1137 #size-cells = <1>;
1138 ranges = <0x0 0x20000 0x1000>;
1139
1140 uart3: serial@0 {
1141 compatible = "ti,dra742-uart", "ti,omap4-uart";
1142 reg = <0x0 0x100>;
1143 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1144 clock-frequency = <48000000>;
1145 status = "disabled";
1146 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
1147 dma-names = "tx", "rx";
1148 };
1149 };
1150
1151 target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1152 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1153 ti,hwmods = "timer2";
1154 reg = <0x32000 0x4>,
1155 <0x32010 0x4>;
1156 reg-names = "rev", "sysc";
1157 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1158 SYSC_OMAP4_SOFTRESET)>;
1159 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1160 <SYSC_IDLE_NO>,
1161 <SYSC_IDLE_SMART>,
1162 <SYSC_IDLE_SMART_WKUP>;
1163 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1164 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1165 clock-names = "fck";
1166 #address-cells = <1>;
1167 #size-cells = <1>;
1168 ranges = <0x0 0x32000 0x1000>;
1169
1170 timer2: timer@0 {
1171 compatible = "ti,omap5430-timer";
1172 reg = <0x0 0x80>;
1173 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>;
1174 clock-names = "fck";
1175 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1176 };
1177 };
1178
1179 target-module@34000 { /* 0x48034000, ap 7 46.0 */
1180 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1181 ti,hwmods = "timer3";
1182 reg = <0x34000 0x4>,
1183 <0x34010 0x4>;
1184 reg-names = "rev", "sysc";
1185 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1186 SYSC_OMAP4_SOFTRESET)>;
1187 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1188 <SYSC_IDLE_NO>,
1189 <SYSC_IDLE_SMART>,
1190 <SYSC_IDLE_SMART_WKUP>;
1191 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1192 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1193 clock-names = "fck";
1194 #address-cells = <1>;
1195 #size-cells = <1>;
1196 ranges = <0x0 0x34000 0x1000>;
1197
1198 timer3: timer@0 {
1199 compatible = "ti,omap5430-timer";
1200 reg = <0x0 0x80>;
1201 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
1202 clock-names = "fck";
1203 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1204 };
1205 };
1206
1207 target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1208 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1209 ti,hwmods = "timer4";
1210 reg = <0x36000 0x4>,
1211 <0x36010 0x4>;
1212 reg-names = "rev", "sysc";
1213 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1214 SYSC_OMAP4_SOFTRESET)>;
1215 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1216 <SYSC_IDLE_NO>,
1217 <SYSC_IDLE_SMART>,
1218 <SYSC_IDLE_SMART_WKUP>;
1219 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1220 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1221 clock-names = "fck";
1222 #address-cells = <1>;
1223 #size-cells = <1>;
1224 ranges = <0x0 0x36000 0x1000>;
1225
1226 timer4: timer@0 {
1227 compatible = "ti,omap5430-timer";
1228 reg = <0x0 0x80>;
1229 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
1230 clock-names = "fck";
1231 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1232 };
1233 };
1234
1235 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1236 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1237 ti,hwmods = "timer9";
1238 reg = <0x3e000 0x4>,
1239 <0x3e010 0x4>;
1240 reg-names = "rev", "sysc";
1241 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1242 SYSC_OMAP4_SOFTRESET)>;
1243 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1244 <SYSC_IDLE_NO>,
1245 <SYSC_IDLE_SMART>,
1246 <SYSC_IDLE_SMART_WKUP>;
1247 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1248 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1249 clock-names = "fck";
1250 #address-cells = <1>;
1251 #size-cells = <1>;
1252 ranges = <0x0 0x3e000 0x1000>;
1253
1254 timer9: timer@0 {
1255 compatible = "ti,omap5430-timer";
1256 reg = <0x0 0x80>;
1257 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>;
1258 clock-names = "fck";
1259 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1260 };
1261 };
1262
1263 gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1264 compatible = "ti,sysc-omap2", "ti,sysc";
1265 reg = <0x51000 0x4>,
1266 <0x51010 0x4>,
1267 <0x51114 0x4>;
1268 reg-names = "rev", "sysc", "syss";
1269 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1270 SYSC_OMAP2_SOFTRESET |
1271 SYSC_OMAP2_AUTOIDLE)>;
1272 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1273 <SYSC_IDLE_NO>,
1274 <SYSC_IDLE_SMART>,
1275 <SYSC_IDLE_SMART_WKUP>;
1276 ti,syss-mask = <1>;
1277 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1278 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1279 <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
1280 clock-names = "fck", "dbclk";
1281 #address-cells = <1>;
1282 #size-cells = <1>;
1283 ranges = <0x0 0x51000 0x1000>;
1284
1285 gpio7: gpio@0 {
1286 compatible = "ti,omap4-gpio";
1287 reg = <0x0 0x200>;
1288 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1289 gpio-controller;
1290 #gpio-cells = <2>;
1291 interrupt-controller;
1292 #interrupt-cells = <2>;
1293 };
1294 };
1295
1296 target-module@53000 { /* 0x48053000, ap 35 36.0 */
1297 compatible = "ti,sysc-omap2", "ti,sysc";
1298 reg = <0x53000 0x4>,
1299 <0x53010 0x4>,
1300 <0x53114 0x4>;
1301 reg-names = "rev", "sysc", "syss";
1302 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1303 SYSC_OMAP2_SOFTRESET |
1304 SYSC_OMAP2_AUTOIDLE)>;
1305 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1306 <SYSC_IDLE_NO>,
1307 <SYSC_IDLE_SMART>,
1308 <SYSC_IDLE_SMART_WKUP>;
1309 ti,syss-mask = <1>;
1310 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1311 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1312 <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
1313 clock-names = "fck", "dbclk";
1314 #address-cells = <1>;
1315 #size-cells = <1>;
1316 ranges = <0x0 0x53000 0x1000>;
1317
1318 gpio8: gpio@0 {
1319 compatible = "ti,omap4-gpio";
1320 reg = <0x0 0x200>;
1321 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1322 gpio-controller;
1323 #gpio-cells = <2>;
1324 interrupt-controller;
1325 #interrupt-cells = <2>;
1326 };
1327 };
1328
1329 target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1330 compatible = "ti,sysc-omap2", "ti,sysc";
1331 reg = <0x55000 0x4>,
1332 <0x55010 0x4>,
1333 <0x55114 0x4>;
1334 reg-names = "rev", "sysc", "syss";
1335 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1336 SYSC_OMAP2_SOFTRESET |
1337 SYSC_OMAP2_AUTOIDLE)>;
1338 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1339 <SYSC_IDLE_NO>,
1340 <SYSC_IDLE_SMART>,
1341 <SYSC_IDLE_SMART_WKUP>;
1342 ti,syss-mask = <1>;
1343 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1344 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1345 <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
1346 clock-names = "fck", "dbclk";
1347 #address-cells = <1>;
1348 #size-cells = <1>;
1349 ranges = <0x0 0x55000 0x1000>;
1350
1351 gpio2: gpio@0 {
1352 compatible = "ti,omap4-gpio";
1353 reg = <0x0 0x200>;
1354 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1355 gpio-controller;
1356 #gpio-cells = <2>;
1357 interrupt-controller;
1358 #interrupt-cells = <2>;
1359 };
1360 };
1361
1362 target-module@57000 { /* 0x48057000, ap 15 06.0 */
1363 compatible = "ti,sysc-omap2", "ti,sysc";
1364 reg = <0x57000 0x4>,
1365 <0x57010 0x4>,
1366 <0x57114 0x4>;
1367 reg-names = "rev", "sysc", "syss";
1368 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1369 SYSC_OMAP2_SOFTRESET |
1370 SYSC_OMAP2_AUTOIDLE)>;
1371 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1372 <SYSC_IDLE_NO>,
1373 <SYSC_IDLE_SMART>,
1374 <SYSC_IDLE_SMART_WKUP>;
1375 ti,syss-mask = <1>;
1376 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1377 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1378 <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
1379 clock-names = "fck", "dbclk";
1380 #address-cells = <1>;
1381 #size-cells = <1>;
1382 ranges = <0x0 0x57000 0x1000>;
1383
1384 gpio3: gpio@0 {
1385 compatible = "ti,omap4-gpio";
1386 reg = <0x0 0x200>;
1387 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1388 gpio-controller;
1389 #gpio-cells = <2>;
1390 interrupt-controller;
1391 #interrupt-cells = <2>;
1392 };
1393 };
1394
1395 target-module@59000 { /* 0x48059000, ap 17 16.0 */
1396 compatible = "ti,sysc-omap2", "ti,sysc";
1397 reg = <0x59000 0x4>,
1398 <0x59010 0x4>,
1399 <0x59114 0x4>;
1400 reg-names = "rev", "sysc", "syss";
1401 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1402 SYSC_OMAP2_SOFTRESET |
1403 SYSC_OMAP2_AUTOIDLE)>;
1404 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1405 <SYSC_IDLE_NO>,
1406 <SYSC_IDLE_SMART>,
1407 <SYSC_IDLE_SMART_WKUP>;
1408 ti,syss-mask = <1>;
1409 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1410 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1411 <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
1412 clock-names = "fck", "dbclk";
1413 #address-cells = <1>;
1414 #size-cells = <1>;
1415 ranges = <0x0 0x59000 0x1000>;
1416
1417 gpio4: gpio@0 {
1418 compatible = "ti,omap4-gpio";
1419 reg = <0x0 0x200>;
1420 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1421 gpio-controller;
1422 #gpio-cells = <2>;
1423 interrupt-controller;
1424 #interrupt-cells = <2>;
1425 };
1426 };
1427
1428 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1429 compatible = "ti,sysc-omap2", "ti,sysc";
1430 reg = <0x5b000 0x4>,
1431 <0x5b010 0x4>,
1432 <0x5b114 0x4>;
1433 reg-names = "rev", "sysc", "syss";
1434 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1435 SYSC_OMAP2_SOFTRESET |
1436 SYSC_OMAP2_AUTOIDLE)>;
1437 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1438 <SYSC_IDLE_NO>,
1439 <SYSC_IDLE_SMART>,
1440 <SYSC_IDLE_SMART_WKUP>;
1441 ti,syss-mask = <1>;
1442 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1443 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1444 <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
1445 clock-names = "fck", "dbclk";
1446 #address-cells = <1>;
1447 #size-cells = <1>;
1448 ranges = <0x0 0x5b000 0x1000>;
1449
1450 gpio5: gpio@0 {
1451 compatible = "ti,omap4-gpio";
1452 reg = <0x0 0x200>;
1453 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1454 gpio-controller;
1455 #gpio-cells = <2>;
1456 interrupt-controller;
1457 #interrupt-cells = <2>;
1458 };
1459 };
1460
1461 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1462 compatible = "ti,sysc-omap2", "ti,sysc";
1463 reg = <0x5d000 0x4>,
1464 <0x5d010 0x4>,
1465 <0x5d114 0x4>;
1466 reg-names = "rev", "sysc", "syss";
1467 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1468 SYSC_OMAP2_SOFTRESET |
1469 SYSC_OMAP2_AUTOIDLE)>;
1470 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1471 <SYSC_IDLE_NO>,
1472 <SYSC_IDLE_SMART>,
1473 <SYSC_IDLE_SMART_WKUP>;
1474 ti,syss-mask = <1>;
1475 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1476 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1477 <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
1478 clock-names = "fck", "dbclk";
1479 #address-cells = <1>;
1480 #size-cells = <1>;
1481 ranges = <0x0 0x5d000 0x1000>;
1482
1483 gpio6: gpio@0 {
1484 compatible = "ti,omap4-gpio";
1485 reg = <0x0 0x200>;
1486 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1487 gpio-controller;
1488 #gpio-cells = <2>;
1489 interrupt-controller;
1490 #interrupt-cells = <2>;
1491 };
1492 };
1493
1494 target-module@60000 { /* 0x48060000, ap 23 32.0 */
1495 compatible = "ti,sysc-omap2", "ti,sysc";
1496 reg = <0x60000 0x8>,
1497 <0x60010 0x8>,
1498 <0x60090 0x8>;
1499 reg-names = "rev", "sysc", "syss";
1500 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1501 SYSC_OMAP2_ENAWAKEUP |
1502 SYSC_OMAP2_SOFTRESET |
1503 SYSC_OMAP2_AUTOIDLE)>;
1504 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1505 <SYSC_IDLE_NO>,
1506 <SYSC_IDLE_SMART>,
1507 <SYSC_IDLE_SMART_WKUP>;
1508 ti,syss-mask = <1>;
1509 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1510 clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1511 clock-names = "fck";
1512 #address-cells = <1>;
1513 #size-cells = <1>;
1514 ranges = <0x0 0x60000 0x1000>;
1515
1516 i2c3: i2c@0 {
1517 compatible = "ti,omap4-i2c";
1518 reg = <0x0 0x100>;
1519 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1520 #address-cells = <1>;
1521 #size-cells = <0>;
1522 status = "disabled";
1523 };
1524 };
1525
1526 target-module@66000 { /* 0x48066000, ap 63 14.0 */
1527 compatible = "ti,sysc-omap2", "ti,sysc";
1528 reg = <0x66050 0x4>,
1529 <0x66054 0x4>,
1530 <0x66058 0x4>;
1531 reg-names = "rev", "sysc", "syss";
1532 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1533 SYSC_OMAP2_SOFTRESET |
1534 SYSC_OMAP2_AUTOIDLE)>;
1535 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1536 <SYSC_IDLE_NO>,
1537 <SYSC_IDLE_SMART>,
1538 <SYSC_IDLE_SMART_WKUP>;
1539 ti,syss-mask = <1>;
1540 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1541 clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1542 clock-names = "fck";
1543 #address-cells = <1>;
1544 #size-cells = <1>;
1545 ranges = <0x0 0x66000 0x1000>;
1546
1547 uart5: serial@0 {
1548 compatible = "ti,dra742-uart", "ti,omap4-uart";
1549 reg = <0x0 0x100>;
1550 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1551 clock-frequency = <48000000>;
1552 status = "disabled";
1553 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
1554 dma-names = "tx", "rx";
1555 };
1556 };
1557
1558 target-module@68000 { /* 0x48068000, ap 53 1c.0 */
1559 compatible = "ti,sysc-omap2", "ti,sysc";
1560 reg = <0x68050 0x4>,
1561 <0x68054 0x4>,
1562 <0x68058 0x4>;
1563 reg-names = "rev", "sysc", "syss";
1564 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1565 SYSC_OMAP2_SOFTRESET |
1566 SYSC_OMAP2_AUTOIDLE)>;
1567 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1568 <SYSC_IDLE_NO>,
1569 <SYSC_IDLE_SMART>,
1570 <SYSC_IDLE_SMART_WKUP>;
1571 ti,syss-mask = <1>;
1572 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1573 clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1574 clock-names = "fck";
1575 #address-cells = <1>;
1576 #size-cells = <1>;
1577 ranges = <0x0 0x68000 0x1000>;
1578
1579 uart6: serial@0 {
1580 compatible = "ti,dra742-uart", "ti,omap4-uart";
1581 reg = <0x0 0x100>;
1582 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1583 clock-frequency = <48000000>;
1584 status = "disabled";
1585 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
1586 dma-names = "tx", "rx";
1587 };
1588 };
1589
1590 target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
1591 compatible = "ti,sysc-omap2", "ti,sysc";
1592 reg = <0x6a050 0x4>,
1593 <0x6a054 0x4>,
1594 <0x6a058 0x4>;
1595 reg-names = "rev", "sysc", "syss";
1596 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1597 SYSC_OMAP2_SOFTRESET |
1598 SYSC_OMAP2_AUTOIDLE)>;
1599 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1600 <SYSC_IDLE_NO>,
1601 <SYSC_IDLE_SMART>,
1602 <SYSC_IDLE_SMART_WKUP>;
1603 ti,syss-mask = <1>;
1604 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1605 clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1606 clock-names = "fck";
1607 #address-cells = <1>;
1608 #size-cells = <1>;
1609 ranges = <0x0 0x6a000 0x1000>;
1610
1611 uart1: serial@0 {
1612 compatible = "ti,dra742-uart", "ti,omap4-uart";
1613 reg = <0x0 0x100>;
1614 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1615 clock-frequency = <48000000>;
1616 status = "disabled";
1617 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
1618 dma-names = "tx", "rx";
1619 };
1620 };
1621
1622 target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
1623 compatible = "ti,sysc-omap2", "ti,sysc";
1624 reg = <0x6c050 0x4>,
1625 <0x6c054 0x4>,
1626 <0x6c058 0x4>;
1627 reg-names = "rev", "sysc", "syss";
1628 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1629 SYSC_OMAP2_SOFTRESET |
1630 SYSC_OMAP2_AUTOIDLE)>;
1631 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1632 <SYSC_IDLE_NO>,
1633 <SYSC_IDLE_SMART>,
1634 <SYSC_IDLE_SMART_WKUP>;
1635 ti,syss-mask = <1>;
1636 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1637 clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1638 clock-names = "fck";
1639 #address-cells = <1>;
1640 #size-cells = <1>;
1641 ranges = <0x0 0x6c000 0x1000>;
1642
1643 uart2: serial@0 {
1644 compatible = "ti,dra742-uart", "ti,omap4-uart";
1645 reg = <0x0 0x100>;
1646 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1647 clock-frequency = <48000000>;
1648 status = "disabled";
1649 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
1650 dma-names = "tx", "rx";
1651 };
1652 };
1653
1654 target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
1655 compatible = "ti,sysc-omap2", "ti,sysc";
1656 reg = <0x6e050 0x4>,
1657 <0x6e054 0x4>,
1658 <0x6e058 0x4>;
1659 reg-names = "rev", "sysc", "syss";
1660 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1661 SYSC_OMAP2_SOFTRESET |
1662 SYSC_OMAP2_AUTOIDLE)>;
1663 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1664 <SYSC_IDLE_NO>,
1665 <SYSC_IDLE_SMART>,
1666 <SYSC_IDLE_SMART_WKUP>;
1667 ti,syss-mask = <1>;
1668 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1669 clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1670 clock-names = "fck";
1671 #address-cells = <1>;
1672 #size-cells = <1>;
1673 ranges = <0x0 0x6e000 0x1000>;
1674
1675 uart4: serial@0 {
1676 compatible = "ti,dra742-uart", "ti,omap4-uart";
1677 reg = <0x0 0x100>;
1678 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1679 clock-frequency = <48000000>;
1680 status = "disabled";
1681 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
1682 dma-names = "tx", "rx";
1683 };
1684 };
1685
1686 target-module@70000 { /* 0x48070000, ap 30 22.0 */
1687 compatible = "ti,sysc-omap2", "ti,sysc";
1688 reg = <0x70000 0x8>,
1689 <0x70010 0x8>,
1690 <0x70090 0x8>;
1691 reg-names = "rev", "sysc", "syss";
1692 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1693 SYSC_OMAP2_ENAWAKEUP |
1694 SYSC_OMAP2_SOFTRESET |
1695 SYSC_OMAP2_AUTOIDLE)>;
1696 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1697 <SYSC_IDLE_NO>,
1698 <SYSC_IDLE_SMART>,
1699 <SYSC_IDLE_SMART_WKUP>;
1700 ti,syss-mask = <1>;
1701 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1702 clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1703 clock-names = "fck";
1704 #address-cells = <1>;
1705 #size-cells = <1>;
1706 ranges = <0x0 0x70000 0x1000>;
1707
1708 i2c1: i2c@0 {
1709 compatible = "ti,omap4-i2c";
1710 reg = <0x0 0x100>;
1711 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1712 #address-cells = <1>;
1713 #size-cells = <0>;
1714 status = "disabled";
1715 };
1716 };
1717
1718 target-module@72000 { /* 0x48072000, ap 32 2a.0 */
1719 compatible = "ti,sysc-omap2", "ti,sysc";
1720 reg = <0x72000 0x8>,
1721 <0x72010 0x8>,
1722 <0x72090 0x8>;
1723 reg-names = "rev", "sysc", "syss";
1724 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1725 SYSC_OMAP2_ENAWAKEUP |
1726 SYSC_OMAP2_SOFTRESET |
1727 SYSC_OMAP2_AUTOIDLE)>;
1728 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1729 <SYSC_IDLE_NO>,
1730 <SYSC_IDLE_SMART>,
1731 <SYSC_IDLE_SMART_WKUP>;
1732 ti,syss-mask = <1>;
1733 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1734 clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1735 clock-names = "fck";
1736 #address-cells = <1>;
1737 #size-cells = <1>;
1738 ranges = <0x0 0x72000 0x1000>;
1739
1740 i2c2: i2c@0 {
1741 compatible = "ti,omap4-i2c";
1742 reg = <0x0 0x100>;
1743 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1744 #address-cells = <1>;
1745 #size-cells = <0>;
1746 status = "disabled";
1747 };
1748 };
1749
1750 target-module@78000 { /* 0x48078000, ap 39 0a.0 */
1751 compatible = "ti,sysc-omap2", "ti,sysc";
1752 ti,hwmods = "elm";
1753 reg = <0x78000 0x4>,
1754 <0x78010 0x4>,
1755 <0x78014 0x4>;
1756 reg-names = "rev", "sysc", "syss";
1757 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1758 SYSC_OMAP2_SOFTRESET |
1759 SYSC_OMAP2_AUTOIDLE)>;
1760 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1761 <SYSC_IDLE_NO>,
1762 <SYSC_IDLE_SMART>,
1763 <SYSC_IDLE_SMART_WKUP>;
1764 ti,syss-mask = <1>;
1765 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1766 clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1767 clock-names = "fck";
1768 #address-cells = <1>;
1769 #size-cells = <1>;
1770 ranges = <0x0 0x78000 0x1000>;
1771
1772 elm: elm@0 {
1773 compatible = "ti,am3352-elm";
1774 reg = <0x0 0xfc0>; /* device IO registers */
1775 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1776 status = "disabled";
1777 };
1778 };
1779
1780 target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
1781 compatible = "ti,sysc-omap2", "ti,sysc";
1782 reg = <0x7a000 0x8>,
1783 <0x7a010 0x8>,
1784 <0x7a090 0x8>;
1785 reg-names = "rev", "sysc", "syss";
1786 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1787 SYSC_OMAP2_ENAWAKEUP |
1788 SYSC_OMAP2_SOFTRESET |
1789 SYSC_OMAP2_AUTOIDLE)>;
1790 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1791 <SYSC_IDLE_NO>,
1792 <SYSC_IDLE_SMART>,
1793 <SYSC_IDLE_SMART_WKUP>;
1794 ti,syss-mask = <1>;
1795 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1796 clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1797 clock-names = "fck";
1798 #address-cells = <1>;
1799 #size-cells = <1>;
1800 ranges = <0x0 0x7a000 0x1000>;
1801
1802 i2c4: i2c@0 {
1803 compatible = "ti,omap4-i2c";
1804 reg = <0x0 0x100>;
1805 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1806 #address-cells = <1>;
1807 #size-cells = <0>;
1808 status = "disabled";
1809 };
1810 };
1811
1812 target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
1813 compatible = "ti,sysc-omap2", "ti,sysc";
1814 reg = <0x7c000 0x8>,
1815 <0x7c010 0x8>,
1816 <0x7c090 0x8>;
1817 reg-names = "rev", "sysc", "syss";
1818 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1819 SYSC_OMAP2_ENAWAKEUP |
1820 SYSC_OMAP2_SOFTRESET |
1821 SYSC_OMAP2_AUTOIDLE)>;
1822 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1823 <SYSC_IDLE_NO>,
1824 <SYSC_IDLE_SMART>,
1825 <SYSC_IDLE_SMART_WKUP>;
1826 ti,syss-mask = <1>;
1827 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1828 clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1829 clock-names = "fck";
1830 #address-cells = <1>;
1831 #size-cells = <1>;
1832 ranges = <0x0 0x7c000 0x1000>;
1833
1834 i2c5: i2c@0 {
1835 compatible = "ti,omap4-i2c";
1836 reg = <0x0 0x100>;
1837 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1838 #address-cells = <1>;
1839 #size-cells = <0>;
1840 status = "disabled";
1841 };
1842 };
1843
1844 target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1845 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1846 ti,hwmods = "timer10";
1847 reg = <0x86000 0x4>,
1848 <0x86010 0x4>;
1849 reg-names = "rev", "sysc";
1850 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1851 SYSC_OMAP4_SOFTRESET)>;
1852 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1853 <SYSC_IDLE_NO>,
1854 <SYSC_IDLE_SMART>,
1855 <SYSC_IDLE_SMART_WKUP>;
1856 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1857 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1858 clock-names = "fck";
1859 #address-cells = <1>;
1860 #size-cells = <1>;
1861 ranges = <0x0 0x86000 0x1000>;
1862
1863 timer10: timer@0 {
1864 compatible = "ti,omap5430-timer";
1865 reg = <0x0 0x80>;
1866 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>;
1867 clock-names = "fck";
1868 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1869 };
1870 };
1871
1872 target-module@88000 { /* 0x48088000, ap 43 66.0 */
1873 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1874 ti,hwmods = "timer11";
1875 reg = <0x88000 0x4>,
1876 <0x88010 0x4>;
1877 reg-names = "rev", "sysc";
1878 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1879 SYSC_OMAP4_SOFTRESET)>;
1880 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1881 <SYSC_IDLE_NO>,
1882 <SYSC_IDLE_SMART>,
1883 <SYSC_IDLE_SMART_WKUP>;
1884 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1885 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1886 clock-names = "fck";
1887 #address-cells = <1>;
1888 #size-cells = <1>;
1889 ranges = <0x0 0x88000 0x1000>;
1890
1891 timer11: timer@0 {
1892 compatible = "ti,omap5430-timer";
1893 reg = <0x0 0x80>;
1894 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>;
1895 clock-names = "fck";
1896 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1897 };
1898 };
1899
1900 target-module@90000 { /* 0x48090000, ap 55 12.0 */
1901 compatible = "ti,sysc-omap2", "ti,sysc";
1902 ti,hwmods = "rng";
1903 reg = <0x91fe0 0x4>,
1904 <0x91fe4 0x4>;
1905 reg-names = "rev", "sysc";
1906 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
1907 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1908 <SYSC_IDLE_NO>;
1909 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1910 clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1911 clock-names = "fck";
1912 #address-cells = <1>;
1913 #size-cells = <1>;
1914 ranges = <0x0 0x90000 0x2000>;
1915
1916 rng: rng@0 {
1917 compatible = "ti,omap4-rng";
1918 reg = <0x0 0x2000>;
1919 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1920 clocks = <&l3_iclk_div>;
1921 clock-names = "fck";
1922 };
1923 };
1924
1925 target-module@98000 { /* 0x48098000, ap 47 08.0 */
1926 compatible = "ti,sysc-omap4", "ti,sysc";
1927 reg = <0x98000 0x4>,
1928 <0x98010 0x4>;
1929 reg-names = "rev", "sysc";
1930 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1931 SYSC_OMAP4_SOFTRESET)>;
1932 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1933 <SYSC_IDLE_NO>,
1934 <SYSC_IDLE_SMART>,
1935 <SYSC_IDLE_SMART_WKUP>;
1936 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1937 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1938 clock-names = "fck";
1939 #address-cells = <1>;
1940 #size-cells = <1>;
1941 ranges = <0x0 0x98000 0x1000>;
1942
1943 mcspi1: spi@0 {
1944 compatible = "ti,omap4-mcspi";
1945 reg = <0x0 0x200>;
1946 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1947 #address-cells = <1>;
1948 #size-cells = <0>;
1949 ti,spi-num-cs = <4>;
1950 dmas = <&sdma_xbar 35>,
1951 <&sdma_xbar 36>,
1952 <&sdma_xbar 37>,
1953 <&sdma_xbar 38>,
1954 <&sdma_xbar 39>,
1955 <&sdma_xbar 40>,
1956 <&sdma_xbar 41>,
1957 <&sdma_xbar 42>;
1958 dma-names = "tx0", "rx0", "tx1", "rx1",
1959 "tx2", "rx2", "tx3", "rx3";
1960 status = "disabled";
1961 };
1962 };
1963
1964 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1965 compatible = "ti,sysc-omap4", "ti,sysc";
1966 reg = <0x9a000 0x4>,
1967 <0x9a010 0x4>;
1968 reg-names = "rev", "sysc";
1969 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1970 SYSC_OMAP4_SOFTRESET)>;
1971 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1972 <SYSC_IDLE_NO>,
1973 <SYSC_IDLE_SMART>,
1974 <SYSC_IDLE_SMART_WKUP>;
1975 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1976 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1977 clock-names = "fck";
1978 #address-cells = <1>;
1979 #size-cells = <1>;
1980 ranges = <0x0 0x9a000 0x1000>;
1981
1982 mcspi2: spi@0 {
1983 compatible = "ti,omap4-mcspi";
1984 reg = <0x0 0x200>;
1985 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1986 #address-cells = <1>;
1987 #size-cells = <0>;
1988 ti,spi-num-cs = <2>;
1989 dmas = <&sdma_xbar 43>,
1990 <&sdma_xbar 44>,
1991 <&sdma_xbar 45>,
1992 <&sdma_xbar 46>;
1993 dma-names = "tx0", "rx0", "tx1", "rx1";
1994 status = "disabled";
1995 };
1996 };
1997
1998 target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
1999 compatible = "ti,sysc-omap4", "ti,sysc";
2000 reg = <0x9c000 0x4>,
2001 <0x9c010 0x4>;
2002 reg-names = "rev", "sysc";
2003 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2004 SYSC_OMAP4_SOFTRESET)>;
2005 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2006 <SYSC_IDLE_NO>,
2007 <SYSC_IDLE_SMART>,
2008 <SYSC_IDLE_SMART_WKUP>;
2009 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2010 <SYSC_IDLE_NO>,
2011 <SYSC_IDLE_SMART>,
2012 <SYSC_IDLE_SMART_WKUP>;
2013 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2014 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2015 clock-names = "fck";
2016 #address-cells = <1>;
2017 #size-cells = <1>;
2018 ranges = <0x0 0x9c000 0x1000>;
2019
2020 mmc1: mmc@0 {
2021 compatible = "ti,dra7-sdhci";
2022 reg = <0x0 0x400>;
2023 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2024 status = "disabled";
2025 pbias-supply = <&pbias_mmc_reg>;
2026 max-frequency = <192000000>;
2027 mmc-ddr-1_8v;
2028 mmc-ddr-3_3v;
2029 };
2030 };
2031
2032 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
2033 compatible = "ti,sysc";
2034 status = "disabled";
2035 #address-cells = <1>;
2036 #size-cells = <1>;
2037 ranges = <0x0 0xa2000 0x1000>;
2038 };
2039
2040 target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
2041 compatible = "ti,sysc";
2042 status = "disabled";
2043 #address-cells = <1>;
2044 #size-cells = <1>;
2045 ranges = <0x00000000 0x000a4000 0x00001000>,
2046 <0x00001000 0x000a5000 0x00001000>;
2047 };
2048
2049 target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
2050 compatible = "ti,sysc";
2051 status = "disabled";
2052 #address-cells = <1>;
2053 #size-cells = <1>;
2054 ranges = <0x0 0xa8000 0x4000>;
2055 };
2056
2057 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
2058 compatible = "ti,sysc-omap4", "ti,sysc";
2059 reg = <0xad000 0x4>,
2060 <0xad010 0x4>;
2061 reg-names = "rev", "sysc";
2062 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2063 SYSC_OMAP4_SOFTRESET)>;
2064 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2065 <SYSC_IDLE_NO>,
2066 <SYSC_IDLE_SMART>,
2067 <SYSC_IDLE_SMART_WKUP>;
2068 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2069 <SYSC_IDLE_NO>,
2070 <SYSC_IDLE_SMART>,
2071 <SYSC_IDLE_SMART_WKUP>;
2072 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2073 clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2074 clock-names = "fck";
2075 #address-cells = <1>;
2076 #size-cells = <1>;
2077 ranges = <0x0 0xad000 0x1000>;
2078
2079 mmc3: mmc@0 {
2080 compatible = "ti,dra7-sdhci";
2081 reg = <0x0 0x400>;
2082 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
2083 status = "disabled";
2084 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
2085 max-frequency = <64000000>;
2086 /* SDMA is not supported */
2087 sdhci-caps-mask = <0x0 0x400000>;
2088 };
2089 };
2090
2091 target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
2092 compatible = "ti,sysc-omap2", "ti,sysc";
2093 ti,hwmods = "hdq1w";
2094 reg = <0xb2000 0x4>,
2095 <0xb2014 0x4>,
2096 <0xb2018 0x4>;
2097 reg-names = "rev", "sysc", "syss";
2098 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2099 SYSC_OMAP2_AUTOIDLE)>;
2100 ti,syss-mask = <1>;
2101 ti,no-reset-on-init;
2102 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2103 clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2104 clock-names = "fck";
2105 #address-cells = <1>;
2106 #size-cells = <1>;
2107 ranges = <0x0 0xb2000 0x1000>;
2108
2109 hdqw1w: 1w@0 {
2110 compatible = "ti,omap3-1w";
2111 reg = <0x0 0x1000>;
2112 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2113 };
2114 };
2115
2116 target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
2117 compatible = "ti,sysc-omap4", "ti,sysc";
2118 reg = <0xb4000 0x4>,
2119 <0xb4010 0x4>;
2120 reg-names = "rev", "sysc";
2121 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2122 SYSC_OMAP4_SOFTRESET)>;
2123 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2124 <SYSC_IDLE_NO>,
2125 <SYSC_IDLE_SMART>,
2126 <SYSC_IDLE_SMART_WKUP>;
2127 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2128 <SYSC_IDLE_NO>,
2129 <SYSC_IDLE_SMART>,
2130 <SYSC_IDLE_SMART_WKUP>;
2131 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2132 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2133 clock-names = "fck";
2134 #address-cells = <1>;
2135 #size-cells = <1>;
2136 ranges = <0x0 0xb4000 0x1000>;
2137
2138 mmc2: mmc@0 {
2139 compatible = "ti,dra7-sdhci";
2140 reg = <0x0 0x400>;
2141 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2142 status = "disabled";
2143 max-frequency = <192000000>;
2144 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
2145 sdhci-caps-mask = <0x7 0x0>;
2146 mmc-hs200-1_8v;
2147 mmc-ddr-1_8v;
2148 mmc-ddr-3_3v;
2149 };
2150 };
2151
2152 target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
2153 compatible = "ti,sysc-omap4", "ti,sysc";
2154 reg = <0xb8000 0x4>,
2155 <0xb8010 0x4>;
2156 reg-names = "rev", "sysc";
2157 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2158 SYSC_OMAP4_SOFTRESET)>;
2159 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2160 <SYSC_IDLE_NO>,
2161 <SYSC_IDLE_SMART>,
2162 <SYSC_IDLE_SMART_WKUP>;
2163 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2164 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2165 clock-names = "fck";
2166 #address-cells = <1>;
2167 #size-cells = <1>;
2168 ranges = <0x0 0xb8000 0x1000>;
2169
2170 mcspi3: spi@0 {
2171 compatible = "ti,omap4-mcspi";
2172 reg = <0x0 0x200>;
2173 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2174 #address-cells = <1>;
2175 #size-cells = <0>;
2176 ti,spi-num-cs = <2>;
2177 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
2178 dma-names = "tx0", "rx0";
2179 status = "disabled";
2180 };
2181 };
2182
2183 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2184 compatible = "ti,sysc-omap4", "ti,sysc";
2185 reg = <0xba000 0x4>,
2186 <0xba010 0x4>;
2187 reg-names = "rev", "sysc";
2188 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2189 SYSC_OMAP4_SOFTRESET)>;
2190 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2191 <SYSC_IDLE_NO>,
2192 <SYSC_IDLE_SMART>,
2193 <SYSC_IDLE_SMART_WKUP>;
2194 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2195 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2196 clock-names = "fck";
2197 #address-cells = <1>;
2198 #size-cells = <1>;
2199 ranges = <0x0 0xba000 0x1000>;
2200
2201 mcspi4: spi@0 {
2202 compatible = "ti,omap4-mcspi";
2203 reg = <0x0 0x200>;
2204 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2205 #address-cells = <1>;
2206 #size-cells = <0>;
2207 ti,spi-num-cs = <1>;
2208 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
2209 dma-names = "tx0", "rx0";
2210 status = "disabled";
2211 };
2212 };
2213
2214 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2215 compatible = "ti,sysc-omap4", "ti,sysc";
2216 reg = <0xd1000 0x4>,
2217 <0xd1010 0x4>;
2218 reg-names = "rev", "sysc";
2219 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2220 SYSC_OMAP4_SOFTRESET)>;
2221 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2222 <SYSC_IDLE_NO>,
2223 <SYSC_IDLE_SMART>,
2224 <SYSC_IDLE_SMART_WKUP>;
2225 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2226 <SYSC_IDLE_NO>,
2227 <SYSC_IDLE_SMART>,
2228 <SYSC_IDLE_SMART_WKUP>;
2229 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2230 clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2231 clock-names = "fck";
2232 #address-cells = <1>;
2233 #size-cells = <1>;
2234 ranges = <0x0 0xd1000 0x1000>;
2235
2236 mmc4: mmc@0 {
2237 compatible = "ti,dra7-sdhci";
2238 reg = <0x0 0x400>;
2239 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2240 status = "disabled";
2241 max-frequency = <192000000>;
2242 /* SDMA is not supported */
2243 sdhci-caps-mask = <0x0 0x400000>;
2244 };
2245 };
2246
2247 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2248 compatible = "ti,sysc";
2249 status = "disabled";
2250 #address-cells = <1>;
2251 #size-cells = <1>;
2252 ranges = <0x0 0xd5000 0x1000>;
2253 };
2254 };
2255
2256 segment@200000 { /* 0x48200000 */
2257 compatible = "simple-bus";
2258 #address-cells = <1>;
2259 #size-cells = <1>;
2260 };
2261};
2262
2263&l4_per2 { /* 0x48400000 */
2264 compatible = "ti,dra7-l4-per2", "simple-bus";
2265 reg = <0x48400000 0x800>,
2266 <0x48400800 0x800>,
2267 <0x48401000 0x400>,
2268 <0x48401400 0x400>,
2269 <0x48401800 0x400>;
2270 reg-names = "ap", "la", "ia0", "ia1", "ia2";
2271 #address-cells = <1>;
2272 #size-cells = <1>;
2273 ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */
2274 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2275 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2276 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2277 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2278 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2279 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2280 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2281 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2282
2283 segment@0 { /* 0x48400000 */
2284 compatible = "simple-bus";
2285 #address-cells = <1>;
2286 #size-cells = <1>;
2287 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2288 <0x00001000 0x00001000 0x000400>, /* ap 1 */
2289 <0x00000800 0x00000800 0x000800>, /* ap 2 */
2290 <0x00084000 0x00084000 0x004000>, /* ap 3 */
2291 <0x00001400 0x00001400 0x000400>, /* ap 4 */
2292 <0x00001800 0x00001800 0x000400>, /* ap 5 */
2293 <0x00088000 0x00088000 0x001000>, /* ap 6 */
2294 <0x0002c000 0x0002c000 0x001000>, /* ap 7 */
2295 <0x0002d000 0x0002d000 0x001000>, /* ap 8 */
2296 <0x00060000 0x00060000 0x002000>, /* ap 9 */
2297 <0x00062000 0x00062000 0x001000>, /* ap 10 */
2298 <0x00064000 0x00064000 0x002000>, /* ap 11 */
2299 <0x00066000 0x00066000 0x001000>, /* ap 12 */
2300 <0x00068000 0x00068000 0x002000>, /* ap 13 */
2301 <0x0006a000 0x0006a000 0x001000>, /* ap 14 */
2302 <0x0006c000 0x0006c000 0x002000>, /* ap 15 */
2303 <0x0006e000 0x0006e000 0x001000>, /* ap 16 */
2304 <0x00036000 0x00036000 0x001000>, /* ap 17 */
2305 <0x00037000 0x00037000 0x001000>, /* ap 18 */
2306 <0x00070000 0x00070000 0x002000>, /* ap 19 */
2307 <0x00072000 0x00072000 0x001000>, /* ap 20 */
2308 <0x0003a000 0x0003a000 0x001000>, /* ap 21 */
2309 <0x0003b000 0x0003b000 0x001000>, /* ap 22 */
2310 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
2311 <0x0003d000 0x0003d000 0x001000>, /* ap 24 */
2312 <0x0003e000 0x0003e000 0x001000>, /* ap 25 */
2313 <0x0003f000 0x0003f000 0x001000>, /* ap 26 */
2314 <0x00040000 0x00040000 0x001000>, /* ap 27 */
2315 <0x00041000 0x00041000 0x001000>, /* ap 28 */
2316 <0x00042000 0x00042000 0x001000>, /* ap 29 */
2317 <0x00043000 0x00043000 0x001000>, /* ap 30 */
2318 <0x00080000 0x00080000 0x002000>, /* ap 31 */
2319 <0x00082000 0x00082000 0x001000>, /* ap 32 */
2320 <0x0004a000 0x0004a000 0x001000>, /* ap 33 */
2321 <0x0004b000 0x0004b000 0x001000>, /* ap 34 */
2322 <0x00074000 0x00074000 0x002000>, /* ap 35 */
2323 <0x00076000 0x00076000 0x001000>, /* ap 36 */
2324 <0x00050000 0x00050000 0x001000>, /* ap 37 */
2325 <0x00051000 0x00051000 0x001000>, /* ap 38 */
2326 <0x00078000 0x00078000 0x002000>, /* ap 39 */
2327 <0x0007a000 0x0007a000 0x001000>, /* ap 40 */
2328 <0x00054000 0x00054000 0x001000>, /* ap 41 */
2329 <0x00055000 0x00055000 0x001000>, /* ap 42 */
2330 <0x0007c000 0x0007c000 0x002000>, /* ap 43 */
2331 <0x0007e000 0x0007e000 0x001000>, /* ap 44 */
2332 <0x0004c000 0x0004c000 0x001000>, /* ap 45 */
2333 <0x0004d000 0x0004d000 0x001000>, /* ap 46 */
2334 <0x00020000 0x00020000 0x001000>, /* ap 47 */
2335 <0x00021000 0x00021000 0x001000>, /* ap 48 */
2336 <0x00022000 0x00022000 0x001000>, /* ap 49 */
2337 <0x00023000 0x00023000 0x001000>, /* ap 50 */
2338 <0x00024000 0x00024000 0x001000>, /* ap 51 */
2339 <0x00025000 0x00025000 0x001000>, /* ap 52 */
2340 <0x00046000 0x00046000 0x001000>, /* ap 53 */
2341 <0x00047000 0x00047000 0x001000>, /* ap 54 */
2342 <0x00048000 0x00048000 0x001000>, /* ap 55 */
2343 <0x00049000 0x00049000 0x001000>, /* ap 56 */
2344 <0x00058000 0x00058000 0x002000>, /* ap 57 */
2345 <0x0005a000 0x0005a000 0x001000>, /* ap 58 */
2346 <0x0005b000 0x0005b000 0x001000>, /* ap 59 */
2347 <0x0005c000 0x0005c000 0x001000>, /* ap 60 */
2348 <0x0005d000 0x0005d000 0x001000>, /* ap 61 */
2349 <0x0005e000 0x0005e000 0x001000>, /* ap 62 */
2350 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2351 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2352 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2353 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2354 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2355 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2356 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2357 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2358
2359 target-module@20000 { /* 0x48420000, ap 47 02.0 */
2360 compatible = "ti,sysc-omap2", "ti,sysc";
2361 reg = <0x20050 0x4>,
2362 <0x20054 0x4>,
2363 <0x20058 0x4>;
2364 reg-names = "rev", "sysc", "syss";
2365 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2366 SYSC_OMAP2_SOFTRESET |
2367 SYSC_OMAP2_AUTOIDLE)>;
2368 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2369 <SYSC_IDLE_NO>,
2370 <SYSC_IDLE_SMART>,
2371 <SYSC_IDLE_SMART_WKUP>;
2372 ti,syss-mask = <1>;
2373 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2374 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2375 clock-names = "fck";
2376 #address-cells = <1>;
2377 #size-cells = <1>;
2378 ranges = <0x0 0x20000 0x1000>;
2379
2380 uart7: serial@0 {
2381 compatible = "ti,dra742-uart", "ti,omap4-uart";
2382 reg = <0x0 0x100>;
2383 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2384 clock-frequency = <48000000>;
2385 status = "disabled";
2386 };
2387 };
2388
2389 target-module@22000 { /* 0x48422000, ap 49 0a.0 */
2390 compatible = "ti,sysc-omap2", "ti,sysc";
2391 reg = <0x22050 0x4>,
2392 <0x22054 0x4>,
2393 <0x22058 0x4>;
2394 reg-names = "rev", "sysc", "syss";
2395 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2396 SYSC_OMAP2_SOFTRESET |
2397 SYSC_OMAP2_AUTOIDLE)>;
2398 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2399 <SYSC_IDLE_NO>,
2400 <SYSC_IDLE_SMART>,
2401 <SYSC_IDLE_SMART_WKUP>;
2402 ti,syss-mask = <1>;
2403 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2404 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2405 clock-names = "fck";
2406 #address-cells = <1>;
2407 #size-cells = <1>;
2408 ranges = <0x0 0x22000 0x1000>;
2409
2410 uart8: serial@0 {
2411 compatible = "ti,dra742-uart", "ti,omap4-uart";
2412 reg = <0x0 0x100>;
2413 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
2414 clock-frequency = <48000000>;
2415 status = "disabled";
2416 };
2417 };
2418
2419 target-module@24000 { /* 0x48424000, ap 51 12.0 */
2420 compatible = "ti,sysc-omap2", "ti,sysc";
2421 reg = <0x24050 0x4>,
2422 <0x24054 0x4>,
2423 <0x24058 0x4>;
2424 reg-names = "rev", "sysc", "syss";
2425 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2426 SYSC_OMAP2_SOFTRESET |
2427 SYSC_OMAP2_AUTOIDLE)>;
2428 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2429 <SYSC_IDLE_NO>,
2430 <SYSC_IDLE_SMART>,
2431 <SYSC_IDLE_SMART_WKUP>;
2432 ti,syss-mask = <1>;
2433 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2434 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2435 clock-names = "fck";
2436 #address-cells = <1>;
2437 #size-cells = <1>;
2438 ranges = <0x0 0x24000 0x1000>;
2439
2440 uart9: serial@0 {
2441 compatible = "ti,dra742-uart", "ti,omap4-uart";
2442 reg = <0x0 0x100>;
2443 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
2444 clock-frequency = <48000000>;
2445 status = "disabled";
2446 };
2447 };
2448
2449 target-module@2c000 { /* 0x4842c000, ap 7 18.0 */
2450 compatible = "ti,sysc";
2451 status = "disabled";
2452 #address-cells = <1>;
2453 #size-cells = <1>;
2454 ranges = <0x0 0x2c000 0x1000>;
2455 };
2456
2457 target-module@36000 { /* 0x48436000, ap 17 06.0 */
2458 compatible = "ti,sysc";
2459 status = "disabled";
2460 #address-cells = <1>;
2461 #size-cells = <1>;
2462 ranges = <0x0 0x36000 0x1000>;
2463 };
2464
2465 target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */
2466 compatible = "ti,sysc";
2467 status = "disabled";
2468 #address-cells = <1>;
2469 #size-cells = <1>;
2470 ranges = <0x0 0x3a000 0x1000>;
2471 };
2472
2473 atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
2474 compatible = "ti,sysc-omap4", "ti,sysc";
2475 reg = <0x3c000 0x4>;
2476 reg-names = "rev";
2477 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2478 clock-names = "fck";
2479 #address-cells = <1>;
2480 #size-cells = <1>;
2481 ranges = <0x0 0x3c000 0x1000>;
2482
2483 atl: atl@0 {
2484 compatible = "ti,dra7-atl";
2485 reg = <0x0 0x3ff>;
2486 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
2487 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
2488 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2489 clock-names = "fck";
2490 status = "disabled";
2491 };
2492 };
2493
2494 target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
2495 compatible = "ti,sysc-omap4", "ti,sysc";
2496 ti,hwmods = "epwmss0";
2497 reg = <0x3e000 0x4>,
2498 <0x3e004 0x4>;
2499 reg-names = "rev", "sysc";
2500 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2501 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2502 <SYSC_IDLE_NO>,
2503 <SYSC_IDLE_SMART>;
2504 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2505 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2506 clock-names = "fck";
2507 #address-cells = <1>;
2508 #size-cells = <1>;
2509 ranges = <0x0 0x3e000 0x1000>;
2510
2511 epwmss0: epwmss@0 {
2512 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2513 reg = <0x0 0x30>;
2514 #address-cells = <1>;
2515 #size-cells = <1>;
2516 status = "disabled";
2517 ranges = <0 0 0x1000>;
2518
2519 ecap0: ecap@100 {
2520 compatible = "ti,dra746-ecap",
2521 "ti,am3352-ecap";
2522 #pwm-cells = <3>;
2523 reg = <0x100 0x80>;
2524 clocks = <&l4_root_clk_div>;
2525 clock-names = "fck";
2526 status = "disabled";
2527 };
2528
2529 ehrpwm0: pwm@200 {
2530 compatible = "ti,dra746-ehrpwm",
2531 "ti,am3352-ehrpwm";
2532 #pwm-cells = <3>;
2533 reg = <0x200 0x80>;
2534 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
2535 clock-names = "tbclk", "fck";
2536 status = "disabled";
2537 };
2538 };
2539 };
2540
2541 target-module@40000 { /* 0x48440000, ap 27 38.0 */
2542 compatible = "ti,sysc-omap4", "ti,sysc";
2543 ti,hwmods = "epwmss1";
2544 reg = <0x40000 0x4>,
2545 <0x40004 0x4>;
2546 reg-names = "rev", "sysc";
2547 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2548 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2549 <SYSC_IDLE_NO>,
2550 <SYSC_IDLE_SMART>;
2551 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2552 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2553 clock-names = "fck";
2554 #address-cells = <1>;
2555 #size-cells = <1>;
2556 ranges = <0x0 0x40000 0x1000>;
2557
2558 epwmss1: epwmss@0 {
2559 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2560 reg = <0x0 0x30>;
2561 #address-cells = <1>;
2562 #size-cells = <1>;
2563 status = "disabled";
2564 ranges = <0 0 0x1000>;
2565
2566 ecap1: ecap@100 {
2567 compatible = "ti,dra746-ecap",
2568 "ti,am3352-ecap";
2569 #pwm-cells = <3>;
2570 reg = <0x100 0x80>;
2571 clocks = <&l4_root_clk_div>;
2572 clock-names = "fck";
2573 status = "disabled";
2574 };
2575
2576 ehrpwm1: pwm@200 {
2577 compatible = "ti,dra746-ehrpwm",
2578 "ti,am3352-ehrpwm";
2579 #pwm-cells = <3>;
2580 reg = <0x200 0x80>;
2581 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2582 clock-names = "tbclk", "fck";
2583 status = "disabled";
2584 };
2585 };
2586 };
2587
2588 target-module@42000 { /* 0x48442000, ap 29 20.0 */
2589 compatible = "ti,sysc-omap4", "ti,sysc";
2590 ti,hwmods = "epwmss2";
2591 reg = <0x42000 0x4>,
2592 <0x42004 0x4>;
2593 reg-names = "rev", "sysc";
2594 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2595 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2596 <SYSC_IDLE_NO>,
2597 <SYSC_IDLE_SMART>;
2598 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2599 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2600 clock-names = "fck";
2601 #address-cells = <1>;
2602 #size-cells = <1>;
2603 ranges = <0x0 0x42000 0x1000>;
2604
2605 epwmss2: epwmss@0 {
2606 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2607 reg = <0x0 0x30>;
2608 #address-cells = <1>;
2609 #size-cells = <1>;
2610 status = "disabled";
2611 ranges = <0 0 0x1000>;
2612
2613 ecap2: ecap@100 {
2614 compatible = "ti,dra746-ecap",
2615 "ti,am3352-ecap";
2616 #pwm-cells = <3>;
2617 reg = <0x100 0x80>;
2618 clocks = <&l4_root_clk_div>;
2619 clock-names = "fck";
2620 status = "disabled";
2621 };
2622
2623 ehrpwm2: pwm@200 {
2624 compatible = "ti,dra746-ehrpwm",
2625 "ti,am3352-ehrpwm";
2626 #pwm-cells = <3>;
2627 reg = <0x200 0x80>;
2628 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2629 clock-names = "tbclk", "fck";
2630 status = "disabled";
2631 };
2632 };
2633 };
2634
2635 target-module@46000 { /* 0x48446000, ap 53 40.0 */
2636 compatible = "ti,sysc";
2637 status = "disabled";
2638 #address-cells = <1>;
2639 #size-cells = <1>;
2640 ranges = <0x0 0x46000 0x1000>;
2641 };
2642
2643 target-module@48000 { /* 0x48448000, ap 55 48.0 */
2644 compatible = "ti,sysc";
2645 status = "disabled";
2646 #address-cells = <1>;
2647 #size-cells = <1>;
2648 ranges = <0x0 0x48000 0x1000>;
2649 };
2650
2651 target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */
2652 compatible = "ti,sysc";
2653 status = "disabled";
2654 #address-cells = <1>;
2655 #size-cells = <1>;
2656 ranges = <0x0 0x4a000 0x1000>;
2657 };
2658
2659 target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */
2660 compatible = "ti,sysc";
2661 status = "disabled";
2662 #address-cells = <1>;
2663 #size-cells = <1>;
2664 ranges = <0x0 0x4c000 0x1000>;
2665 };
2666
2667 target-module@50000 { /* 0x48450000, ap 37 24.0 */
2668 compatible = "ti,sysc";
2669 status = "disabled";
2670 #address-cells = <1>;
2671 #size-cells = <1>;
2672 ranges = <0x0 0x50000 0x1000>;
2673 };
2674
2675 target-module@54000 { /* 0x48454000, ap 41 2c.0 */
2676 compatible = "ti,sysc";
2677 status = "disabled";
2678 #address-cells = <1>;
2679 #size-cells = <1>;
2680 ranges = <0x0 0x54000 0x1000>;
2681 };
2682
2683 target-module@58000 { /* 0x48458000, ap 57 28.0 */
2684 compatible = "ti,sysc";
2685 status = "disabled";
2686 #address-cells = <1>;
2687 #size-cells = <1>;
2688 ranges = <0x0 0x58000 0x2000>;
2689 };
2690
2691 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
2692 compatible = "ti,sysc";
2693 status = "disabled";
2694 #address-cells = <1>;
2695 #size-cells = <1>;
2696 ranges = <0x0 0x5b000 0x1000>;
2697 };
2698
2699 target-module@5d000 { /* 0x4845d000, ap 61 22.0 */
2700 compatible = "ti,sysc";
2701 status = "disabled";
2702 #address-cells = <1>;
2703 #size-cells = <1>;
2704 ranges = <0x0 0x5d000 0x1000>;
2705 };
2706
2707 target-module@60000 { /* 0x48460000, ap 9 0e.0 */
2708 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2709 reg = <0x60000 0x4>,
2710 <0x60004 0x4>;
2711 reg-names = "rev", "sysc";
2712 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2713 <SYSC_IDLE_NO>,
2714 <SYSC_IDLE_SMART>;
2715 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
2716 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2717 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2718 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2719 clock-names = "fck", "ahclkx", "ahclkr";
2720 #address-cells = <1>;
2721 #size-cells = <1>;
2722 ranges = <0x0 0x60000 0x2000>,
2723 <0x45800000 0x45800000 0x400000>;
2724
2725 mcasp1: mcasp@0 {
2726 compatible = "ti,dra7-mcasp-audio";
2727 reg = <0x0 0x2000>,
2728 <0x45800000 0x1000>; /* L3 data port */
2729 reg-names = "mpu","dat";
2730 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2731 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2732 interrupt-names = "tx", "rx";
2733 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
2734 dma-names = "tx", "rx";
2735 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2736 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2737 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2738 clock-names = "fck", "ahclkx", "ahclkr";
2739 status = "disabled";
2740 };
2741 };
2742
2743 target-module@64000 { /* 0x48464000, ap 11 1e.0 */
2744 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2745 reg = <0x64000 0x4>,
2746 <0x64004 0x4>;
2747 reg-names = "rev", "sysc";
2748 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2749 <SYSC_IDLE_NO>,
2750 <SYSC_IDLE_SMART>;
2751 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2752 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2753 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2754 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2755 clock-names = "fck", "ahclkx", "ahclkr";
2756 #address-cells = <1>;
2757 #size-cells = <1>;
2758 ranges = <0x0 0x64000 0x2000>,
2759 <0x45c00000 0x45c00000 0x400000>;
2760
2761 mcasp2: mcasp@0 {
2762 compatible = "ti,dra7-mcasp-audio";
2763 reg = <0x0 0x2000>,
2764 <0x45c00000 0x1000>; /* L3 data port */
2765 reg-names = "mpu","dat";
2766 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2767 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2768 interrupt-names = "tx", "rx";
2769 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
2770 dma-names = "tx", "rx";
2771 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2772 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2773 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2774 clock-names = "fck", "ahclkx", "ahclkr";
2775 status = "disabled";
2776 };
2777 };
2778
2779 target-module@68000 { /* 0x48468000, ap 13 26.0 */
2780 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2781 reg = <0x68000 0x4>,
2782 <0x68004 0x4>;
2783 reg-names = "rev", "sysc";
2784 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2785 <SYSC_IDLE_NO>,
2786 <SYSC_IDLE_SMART>;
2787 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2788 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2789 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2790 clock-names = "fck", "ahclkx";
2791 #address-cells = <1>;
2792 #size-cells = <1>;
2793 ranges = <0x0 0x68000 0x2000>,
2794 <0x46000000 0x46000000 0x400000>;
2795
2796 mcasp3: mcasp@0 {
2797 compatible = "ti,dra7-mcasp-audio";
2798 reg = <0x0 0x2000>,
2799 <0x46000000 0x1000>; /* L3 data port */
2800 reg-names = "mpu","dat";
2801 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
2802 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2803 interrupt-names = "tx", "rx";
2804 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
2805 dma-names = "tx", "rx";
2806 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2807 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2808 clock-names = "fck", "ahclkx";
2809 status = "disabled";
2810 };
2811 };
2812
2813 target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
2814 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2815 reg = <0x6c000 0x4>,
2816 <0x6c004 0x4>;
2817 reg-names = "rev", "sysc";
2818 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2819 <SYSC_IDLE_NO>,
2820 <SYSC_IDLE_SMART>;
2821 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2822 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2823 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2824 clock-names = "fck", "ahclkx";
2825 #address-cells = <1>;
2826 #size-cells = <1>;
2827 ranges = <0x0 0x6c000 0x2000>,
2828 <0x48436000 0x48436000 0x400000>;
2829
2830 mcasp4: mcasp@0 {
2831 compatible = "ti,dra7-mcasp-audio";
2832 reg = <0x0 0x2000>,
2833 <0x48436000 0x1000>; /* L3 data port */
2834 reg-names = "mpu","dat";
2835 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
2836 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
2837 interrupt-names = "tx", "rx";
2838 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
2839 dma-names = "tx", "rx";
2840 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2841 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2842 clock-names = "fck", "ahclkx";
2843 status = "disabled";
2844 };
2845 };
2846
2847 target-module@70000 { /* 0x48470000, ap 19 36.0 */
2848 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2849 reg = <0x70000 0x4>,
2850 <0x70004 0x4>;
2851 reg-names = "rev", "sysc";
2852 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2853 <SYSC_IDLE_NO>,
2854 <SYSC_IDLE_SMART>;
2855 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2856 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2857 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2858 clock-names = "fck", "ahclkx";
2859 #address-cells = <1>;
2860 #size-cells = <1>;
2861 ranges = <0x0 0x70000 0x2000>,
2862 <0x4843a000 0x4843a000 0x400000>;
2863
2864 mcasp5: mcasp@0 {
2865 compatible = "ti,dra7-mcasp-audio";
2866 reg = <0x0 0x2000>,
2867 <0x4843a000 0x1000>; /* L3 data port */
2868 reg-names = "mpu","dat";
2869 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
2870 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
2871 interrupt-names = "tx", "rx";
2872 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
2873 dma-names = "tx", "rx";
2874 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2875 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2876 clock-names = "fck", "ahclkx";
2877 status = "disabled";
2878 };
2879 };
2880
2881 target-module@74000 { /* 0x48474000, ap 35 14.0 */
2882 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2883 reg = <0x74000 0x4>,
2884 <0x74004 0x4>;
2885 reg-names = "rev", "sysc";
2886 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2887 <SYSC_IDLE_NO>,
2888 <SYSC_IDLE_SMART>;
2889 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2890 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2891 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2892 clock-names = "fck", "ahclkx";
2893 #address-cells = <1>;
2894 #size-cells = <1>;
2895 ranges = <0x0 0x74000 0x2000>,
2896 <0x4844c000 0x4844c000 0x400000>;
2897
2898 mcasp6: mcasp@0 {
2899 compatible = "ti,dra7-mcasp-audio";
2900 reg = <0x0 0x2000>,
2901 <0x4844c000 0x1000>; /* L3 data port */
2902 reg-names = "mpu","dat";
2903 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
2904 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
2905 interrupt-names = "tx", "rx";
2906 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
2907 dma-names = "tx", "rx";
2908 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2909 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2910 clock-names = "fck", "ahclkx";
2911 status = "disabled";
2912 };
2913 };
2914
2915 target-module@78000 { /* 0x48478000, ap 39 0c.0 */
2916 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2917 reg = <0x78000 0x4>,
2918 <0x78004 0x4>;
2919 reg-names = "rev", "sysc";
2920 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2921 <SYSC_IDLE_NO>,
2922 <SYSC_IDLE_SMART>;
2923 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2924 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2925 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2926 clock-names = "fck", "ahclkx";
2927 #address-cells = <1>;
2928 #size-cells = <1>;
2929 ranges = <0x0 0x78000 0x2000>,
2930 <0x48450000 0x48450000 0x400000>;
2931
2932 mcasp7: mcasp@0 {
2933 compatible = "ti,dra7-mcasp-audio";
2934 reg = <0x0 0x2000>,
2935 <0x48450000 0x1000>; /* L3 data port */
2936 reg-names = "mpu","dat";
2937 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
2938 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2939 interrupt-names = "tx", "rx";
2940 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
2941 dma-names = "tx", "rx";
2942 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2943 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2944 clock-names = "fck", "ahclkx";
2945 status = "disabled";
2946 };
2947 };
2948
2949 target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
2950 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2951 reg = <0x7c000 0x4>,
2952 <0x7c004 0x4>;
2953 reg-names = "rev", "sysc";
2954 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2955 <SYSC_IDLE_NO>,
2956 <SYSC_IDLE_SMART>;
2957 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2958 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2959 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2960 clock-names = "fck", "ahclkx";
2961 #address-cells = <1>;
2962 #size-cells = <1>;
2963 ranges = <0x0 0x7c000 0x2000>,
2964 <0x48454000 0x48454000 0x400000>;
2965
2966 mcasp8: mcasp@0 {
2967 compatible = "ti,dra7-mcasp-audio";
2968 reg = <0x0 0x2000>,
2969 <0x48454000 0x1000>; /* L3 data port */
2970 reg-names = "mpu","dat";
2971 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2972 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2973 interrupt-names = "tx", "rx";
2974 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
2975 dma-names = "tx", "rx";
2976 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2977 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2978 clock-names = "fck", "ahclkx";
2979 status = "disabled";
2980 };
2981 };
2982
2983 target-module@80000 { /* 0x48480000, ap 31 16.0 */
2984 compatible = "ti,sysc-omap4", "ti,sysc";
2985 reg = <0x80020 0x4>;
2986 reg-names = "rev";
2987 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
2988 clock-names = "fck";
2989 #address-cells = <1>;
2990 #size-cells = <1>;
2991 ranges = <0x0 0x80000 0x2000>;
2992
2993 dcan2: can@0 {
2994 compatible = "ti,dra7-d_can";
2995 reg = <0x0 0x2000>;
2996 syscon-raminit = <&scm_conf 0x558 1>;
2997 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
2998 clocks = <&sys_clkin1>;
2999 status = "disabled";
3000 };
3001 };
3002
3003 target-module@84000 { /* 0x48484000, ap 3 10.0 */
3004 compatible = "ti,sysc-omap4-simple", "ti,sysc";
3005 reg = <0x85200 0x4>,
3006 <0x85208 0x4>,
3007 <0x85204 0x4>;
3008 reg-names = "rev", "sysc", "syss";
3009 ti,sysc-mask = <0>;
3010 ti,sysc-midle = <SYSC_IDLE_FORCE>,
3011 <SYSC_IDLE_NO>;
3012 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3013 <SYSC_IDLE_NO>;
3014 ti,syss-mask = <1>;
3015 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3016 clock-names = "fck";
3017 #address-cells = <1>;
3018 #size-cells = <1>;
3019 ranges = <0x0 0x84000 0x4000>;
3020 /*
3021 * Do not allow gating of cpsw clock as workaround
3022 * for errata i877. Keeping internal clock disabled
3023 * causes the device switching characteristics
3024 * to degrade over time and eventually fail to meet
3025 * the data manual delay time/skew specs.
3026 */
3027 ti,no-idle;
3028
3029 mac: ethernet@0 {
3030 compatible = "ti,dra7-cpsw","ti,cpsw";
3031 clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3032 clock-names = "fck", "cpts";
3033 cpdma_channels = <8>;
3034 ale_entries = <1024>;
3035 bd_ram_size = <0x2000>;
3036 mac_control = <0x20>;
3037 slaves = <2>;
3038 active_slave = <0>;
3039 cpts_clock_mult = <0x784CFE14>;
3040 cpts_clock_shift = <29>;
3041 reg = <0x0 0x1000
3042 0x1200 0x2e00>;
3043 #address-cells = <1>;
3044 #size-cells = <1>;
3045
3046 /*
3047 * rx_thresh_pend
3048 * rx_pend
3049 * tx_pend
3050 * misc_pend
3051 */
3052 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3056 ranges = <0 0 0x4000>;
3057 syscon = <&scm_conf>;
3058 status = "disabled";
3059
3060 davinci_mdio: mdio@1000 {
3061 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3062 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3063 clock-names = "fck";
3064 #address-cells = <1>;
3065 #size-cells = <0>;
3066 bus_freq = <1000000>;
3067 reg = <0x1000 0x100>;
3068 };
3069
3070 cpsw_emac0: slave@200 {
3071 /* Filled in by U-Boot */
3072 mac-address = [ 00 00 00 00 00 00 ];
3073 phys = <&phy_gmii_sel 1>;
3074 };
3075
3076 cpsw_emac1: slave@300 {
3077 /* Filled in by U-Boot */
3078 mac-address = [ 00 00 00 00 00 00 ];
3079 phys = <&phy_gmii_sel 2>;
3080 };
3081 };
3082 };
3083 };
3084};
3085
3086&l4_per3 { /* 0x48800000 */
3087 compatible = "ti,dra7-l4-per3", "simple-bus";
3088 reg = <0x48800000 0x800>,
3089 <0x48800800 0x800>,
3090 <0x48801000 0x400>,
3091 <0x48801400 0x400>,
3092 <0x48801800 0x400>;
3093 reg-names = "ap", "la", "ia0", "ia1", "ia2";
3094 #address-cells = <1>;
3095 #size-cells = <1>;
3096 ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */
3097
3098 segment@0 { /* 0x48800000 */
3099 compatible = "simple-bus";
3100 #address-cells = <1>;
3101 #size-cells = <1>;
3102 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
3103 <0x00000800 0x00000800 0x000800>, /* ap 1 */
3104 <0x00001000 0x00001000 0x000400>, /* ap 2 */
3105 <0x00001400 0x00001400 0x000400>, /* ap 3 */
3106 <0x00001800 0x00001800 0x000400>, /* ap 4 */
3107 <0x00020000 0x00020000 0x001000>, /* ap 5 */
3108 <0x00021000 0x00021000 0x001000>, /* ap 6 */
3109 <0x00022000 0x00022000 0x001000>, /* ap 7 */
3110 <0x00023000 0x00023000 0x001000>, /* ap 8 */
3111 <0x00024000 0x00024000 0x001000>, /* ap 9 */
3112 <0x00025000 0x00025000 0x001000>, /* ap 10 */
3113 <0x00026000 0x00026000 0x001000>, /* ap 11 */
3114 <0x00027000 0x00027000 0x001000>, /* ap 12 */
3115 <0x00028000 0x00028000 0x001000>, /* ap 13 */
3116 <0x00029000 0x00029000 0x001000>, /* ap 14 */
3117 <0x0002a000 0x0002a000 0x001000>, /* ap 15 */
3118 <0x0002b000 0x0002b000 0x001000>, /* ap 16 */
3119 <0x0002c000 0x0002c000 0x001000>, /* ap 17 */
3120 <0x0002d000 0x0002d000 0x001000>, /* ap 18 */
3121 <0x0002e000 0x0002e000 0x001000>, /* ap 19 */
3122 <0x0002f000 0x0002f000 0x001000>, /* ap 20 */
3123 <0x00170000 0x00170000 0x010000>, /* ap 21 */
3124 <0x00180000 0x00180000 0x001000>, /* ap 22 */
3125 <0x00190000 0x00190000 0x010000>, /* ap 23 */
3126 <0x001a0000 0x001a0000 0x001000>, /* ap 24 */
3127 <0x001b0000 0x001b0000 0x010000>, /* ap 25 */
3128 <0x001c0000 0x001c0000 0x001000>, /* ap 26 */
3129 <0x001d0000 0x001d0000 0x010000>, /* ap 27 */
3130 <0x001e0000 0x001e0000 0x001000>, /* ap 28 */
3131 <0x00038000 0x00038000 0x001000>, /* ap 29 */
3132 <0x00039000 0x00039000 0x001000>, /* ap 30 */
3133 <0x0005c000 0x0005c000 0x001000>, /* ap 31 */
3134 <0x0005d000 0x0005d000 0x001000>, /* ap 32 */
3135 <0x0003a000 0x0003a000 0x001000>, /* ap 33 */
3136 <0x0003b000 0x0003b000 0x001000>, /* ap 34 */
3137 <0x0003c000 0x0003c000 0x001000>, /* ap 35 */
3138 <0x0003d000 0x0003d000 0x001000>, /* ap 36 */
3139 <0x0003e000 0x0003e000 0x001000>, /* ap 37 */
3140 <0x0003f000 0x0003f000 0x001000>, /* ap 38 */
3141 <0x00040000 0x00040000 0x001000>, /* ap 39 */
3142 <0x00041000 0x00041000 0x001000>, /* ap 40 */
3143 <0x00042000 0x00042000 0x001000>, /* ap 41 */
3144 <0x00043000 0x00043000 0x001000>, /* ap 42 */
3145 <0x00044000 0x00044000 0x001000>, /* ap 43 */
3146 <0x00045000 0x00045000 0x001000>, /* ap 44 */
3147 <0x00046000 0x00046000 0x001000>, /* ap 45 */
3148 <0x00047000 0x00047000 0x001000>, /* ap 46 */
3149 <0x00048000 0x00048000 0x001000>, /* ap 47 */
3150 <0x00049000 0x00049000 0x001000>, /* ap 48 */
3151 <0x0004a000 0x0004a000 0x001000>, /* ap 49 */
3152 <0x0004b000 0x0004b000 0x001000>, /* ap 50 */
3153 <0x0004c000 0x0004c000 0x001000>, /* ap 51 */
3154 <0x0004d000 0x0004d000 0x001000>, /* ap 52 */
3155 <0x0004e000 0x0004e000 0x001000>, /* ap 53 */
3156 <0x0004f000 0x0004f000 0x001000>, /* ap 54 */
3157 <0x00050000 0x00050000 0x001000>, /* ap 55 */
3158 <0x00051000 0x00051000 0x001000>, /* ap 56 */
3159 <0x00052000 0x00052000 0x001000>, /* ap 57 */
3160 <0x00053000 0x00053000 0x001000>, /* ap 58 */
3161 <0x00054000 0x00054000 0x001000>, /* ap 59 */
3162 <0x00055000 0x00055000 0x001000>, /* ap 60 */
3163 <0x00056000 0x00056000 0x001000>, /* ap 61 */
3164 <0x00057000 0x00057000 0x001000>, /* ap 62 */
3165 <0x00058000 0x00058000 0x001000>, /* ap 63 */
3166 <0x00059000 0x00059000 0x001000>, /* ap 64 */
3167 <0x0005a000 0x0005a000 0x001000>, /* ap 65 */
3168 <0x0005b000 0x0005b000 0x001000>, /* ap 66 */
3169 <0x00064000 0x00064000 0x001000>, /* ap 67 */
3170 <0x00065000 0x00065000 0x001000>, /* ap 68 */
3171 <0x0005e000 0x0005e000 0x001000>, /* ap 69 */
3172 <0x0005f000 0x0005f000 0x001000>, /* ap 70 */
3173 <0x00060000 0x00060000 0x001000>, /* ap 71 */
3174 <0x00061000 0x00061000 0x001000>, /* ap 72 */
3175 <0x00062000 0x00062000 0x001000>, /* ap 73 */
3176 <0x00063000 0x00063000 0x001000>, /* ap 74 */
3177 <0x00140000 0x00140000 0x020000>, /* ap 75 */
3178 <0x00160000 0x00160000 0x001000>, /* ap 76 */
3179 <0x00016000 0x00016000 0x001000>, /* ap 77 */
3180 <0x00017000 0x00017000 0x001000>, /* ap 78 */
3181 <0x000c0000 0x000c0000 0x020000>, /* ap 79 */
3182 <0x000e0000 0x000e0000 0x001000>, /* ap 80 */
3183 <0x00004000 0x00004000 0x001000>, /* ap 81 */
3184 <0x00005000 0x00005000 0x001000>, /* ap 82 */
3185 <0x00080000 0x00080000 0x020000>, /* ap 83 */
3186 <0x000a0000 0x000a0000 0x001000>, /* ap 84 */
3187 <0x00100000 0x00100000 0x020000>, /* ap 85 */
3188 <0x00120000 0x00120000 0x001000>, /* ap 86 */
3189 <0x00010000 0x00010000 0x001000>, /* ap 87 */
3190 <0x00011000 0x00011000 0x001000>, /* ap 88 */
3191 <0x0000a000 0x0000a000 0x001000>, /* ap 89 */
3192 <0x0000b000 0x0000b000 0x001000>, /* ap 90 */
3193 <0x0001c000 0x0001c000 0x001000>, /* ap 91 */
3194 <0x0001d000 0x0001d000 0x001000>, /* ap 92 */
3195 <0x0001e000 0x0001e000 0x001000>, /* ap 93 */
3196 <0x0001f000 0x0001f000 0x001000>, /* ap 94 */
3197 <0x00002000 0x00002000 0x001000>, /* ap 95 */
3198 <0x00003000 0x00003000 0x001000>; /* ap 96 */
3199
3200 target-module@2000 { /* 0x48802000, ap 95 7c.0 */
3201 compatible = "ti,sysc-omap4", "ti,sysc";
3202 ti,hwmods = "mailbox13";
3203 reg = <0x2000 0x4>,
3204 <0x2010 0x4>;
3205 reg-names = "rev", "sysc";
3206 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3207 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3208 <SYSC_IDLE_NO>,
3209 <SYSC_IDLE_SMART>;
3210 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3211 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3212 clock-names = "fck";
3213 #address-cells = <1>;
3214 #size-cells = <1>;
3215 ranges = <0x0 0x2000 0x1000>;
3216
3217 mailbox13: mailbox@0 {
3218 compatible = "ti,omap4-mailbox";
3219 reg = <0x0 0x200>;
3220 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
3221 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
3222 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
3223 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
3224 #mbox-cells = <1>;
3225 ti,mbox-num-users = <4>;
3226 ti,mbox-num-fifos = <12>;
3227 status = "disabled";
3228 };
3229 };
3230
3231 target-module@4000 { /* 0x48804000, ap 81 20.0 */
3232 compatible = "ti,sysc";
3233 status = "disabled";
3234 #address-cells = <1>;
3235 #size-cells = <1>;
3236 ranges = <0x0 0x4000 0x1000>;
3237 };
3238
3239 target-module@a000 { /* 0x4880a000, ap 89 18.0 */
3240 compatible = "ti,sysc";
3241 status = "disabled";
3242 #address-cells = <1>;
3243 #size-cells = <1>;
3244 ranges = <0x0 0xa000 0x1000>;
3245 };
3246
3247 target-module@10000 { /* 0x48810000, ap 87 28.0 */
3248 compatible = "ti,sysc";
3249 status = "disabled";
3250 #address-cells = <1>;
3251 #size-cells = <1>;
3252 ranges = <0x0 0x10000 0x1000>;
3253 };
3254
3255 target-module@16000 { /* 0x48816000, ap 77 1e.0 */
3256 compatible = "ti,sysc";
3257 status = "disabled";
3258 #address-cells = <1>;
3259 #size-cells = <1>;
3260 ranges = <0x0 0x16000 0x1000>;
3261 };
3262
3263 target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */
3264 compatible = "ti,sysc";
3265 status = "disabled";
3266 #address-cells = <1>;
3267 #size-cells = <1>;
3268 ranges = <0x0 0x1c000 0x1000>;
3269 };
3270
3271 target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */
3272 compatible = "ti,sysc";
3273 status = "disabled";
3274 #address-cells = <1>;
3275 #size-cells = <1>;
3276 ranges = <0x0 0x1e000 0x1000>;
3277 };
3278
3279 target-module@20000 { /* 0x48820000, ap 5 08.0 */
3280 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3281 ti,hwmods = "timer5";
3282 reg = <0x20000 0x4>,
3283 <0x20010 0x4>;
3284 reg-names = "rev", "sysc";
3285 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3286 SYSC_OMAP4_SOFTRESET)>;
3287 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3288 <SYSC_IDLE_NO>,
3289 <SYSC_IDLE_SMART>,
3290 <SYSC_IDLE_SMART_WKUP>;
3291 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3292 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3293 clock-names = "fck";
3294 #address-cells = <1>;
3295 #size-cells = <1>;
3296 ranges = <0x0 0x20000 0x1000>;
3297
3298 timer5: timer@0 {
3299 compatible = "ti,omap5430-timer";
3300 reg = <0x0 0x80>;
3301 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>;
3302 clock-names = "fck";
3303 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3304 };
3305 };
3306
3307 target-module@22000 { /* 0x48822000, ap 7 24.0 */
3308 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3309 ti,hwmods = "timer6";
3310 reg = <0x22000 0x4>,
3311 <0x22010 0x4>;
3312 reg-names = "rev", "sysc";
3313 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3314 SYSC_OMAP4_SOFTRESET)>;
3315 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3316 <SYSC_IDLE_NO>,
3317 <SYSC_IDLE_SMART>,
3318 <SYSC_IDLE_SMART_WKUP>;
3319 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3320 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3321 clock-names = "fck";
3322 #address-cells = <1>;
3323 #size-cells = <1>;
3324 ranges = <0x0 0x22000 0x1000>;
3325
3326 timer6: timer@0 {
3327 compatible = "ti,omap5430-timer";
3328 reg = <0x0 0x80>;
3329 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>;
3330 clock-names = "fck";
3331 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3332 };
3333 };
3334
3335 target-module@24000 { /* 0x48824000, ap 9 26.0 */
3336 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3337 ti,hwmods = "timer7";
3338 reg = <0x24000 0x4>,
3339 <0x24010 0x4>;
3340 reg-names = "rev", "sysc";
3341 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3342 SYSC_OMAP4_SOFTRESET)>;
3343 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3344 <SYSC_IDLE_NO>,
3345 <SYSC_IDLE_SMART>,
3346 <SYSC_IDLE_SMART_WKUP>;
3347 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3348 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3349 clock-names = "fck";
3350 #address-cells = <1>;
3351 #size-cells = <1>;
3352 ranges = <0x0 0x24000 0x1000>;
3353
3354 timer7: timer@0 {
3355 compatible = "ti,omap5430-timer";
3356 reg = <0x0 0x80>;
3357 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>;
3358 clock-names = "fck";
3359 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3360 };
3361 };
3362
3363 target-module@26000 { /* 0x48826000, ap 11 0c.0 */
3364 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3365 ti,hwmods = "timer8";
3366 reg = <0x26000 0x4>,
3367 <0x26010 0x4>;
3368 reg-names = "rev", "sysc";
3369 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3370 SYSC_OMAP4_SOFTRESET)>;
3371 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3372 <SYSC_IDLE_NO>,
3373 <SYSC_IDLE_SMART>,
3374 <SYSC_IDLE_SMART_WKUP>;
3375 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3376 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3377 clock-names = "fck";
3378 #address-cells = <1>;
3379 #size-cells = <1>;
3380 ranges = <0x0 0x26000 0x1000>;
3381
3382 timer8: timer@0 {
3383 compatible = "ti,omap5430-timer";
3384 reg = <0x0 0x80>;
3385 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>;
3386 clock-names = "fck";
3387 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
3388 };
3389 };
3390
3391 target-module@28000 { /* 0x48828000, ap 13 16.0 */
3392 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3393 ti,hwmods = "timer13";
3394 reg = <0x28000 0x4>,
3395 <0x28010 0x4>;
3396 reg-names = "rev", "sysc";
3397 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3398 SYSC_OMAP4_SOFTRESET)>;
3399 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3400 <SYSC_IDLE_NO>,
3401 <SYSC_IDLE_SMART>,
3402 <SYSC_IDLE_SMART_WKUP>;
3403 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3404 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3405 clock-names = "fck";
3406 #address-cells = <1>;
3407 #size-cells = <1>;
3408 ranges = <0x0 0x28000 0x1000>;
3409
3410 timer13: timer@0 {
3411 compatible = "ti,omap5430-timer";
3412 reg = <0x0 0x80>;
3413 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
3414 clock-names = "fck";
3415 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
3416 };
3417 };
3418
3419 target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
3420 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3421 ti,hwmods = "timer14";
3422 reg = <0x2a000 0x4>,
3423 <0x2a010 0x4>;
3424 reg-names = "rev", "sysc";
3425 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3426 SYSC_OMAP4_SOFTRESET)>;
3427 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3428 <SYSC_IDLE_NO>,
3429 <SYSC_IDLE_SMART>,
3430 <SYSC_IDLE_SMART_WKUP>;
3431 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3432 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3433 clock-names = "fck";
3434 #address-cells = <1>;
3435 #size-cells = <1>;
3436 ranges = <0x0 0x2a000 0x1000>;
3437
3438 timer14: timer@0 {
3439 compatible = "ti,omap5430-timer";
3440 reg = <0x0 0x80>;
3441 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
3442 clock-names = "fck";
3443 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
3444 };
3445 };
3446
3447 target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
3448 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3449 ti,hwmods = "timer15";
3450 reg = <0x2c000 0x4>,
3451 <0x2c010 0x4>;
3452 reg-names = "rev", "sysc";
3453 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3454 SYSC_OMAP4_SOFTRESET)>;
3455 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3456 <SYSC_IDLE_NO>,
3457 <SYSC_IDLE_SMART>,
3458 <SYSC_IDLE_SMART_WKUP>;
3459 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3460 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3461 clock-names = "fck";
3462 #address-cells = <1>;
3463 #size-cells = <1>;
3464 ranges = <0x0 0x2c000 0x1000>;
3465
3466 timer15: timer@0 {
3467 compatible = "ti,omap5430-timer";
3468 reg = <0x0 0x80>;
3469 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
3470 clock-names = "fck";
3471 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
3472 };
3473 };
3474
3475 target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
3476 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3477 ti,hwmods = "timer16";
3478 reg = <0x2e000 0x4>,
3479 <0x2e010 0x4>;
3480 reg-names = "rev", "sysc";
3481 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3482 SYSC_OMAP4_SOFTRESET)>;
3483 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3484 <SYSC_IDLE_NO>,
3485 <SYSC_IDLE_SMART>,
3486 <SYSC_IDLE_SMART_WKUP>;
3487 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3488 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3489 clock-names = "fck";
3490 #address-cells = <1>;
3491 #size-cells = <1>;
3492 ranges = <0x0 0x2e000 0x1000>;
3493
3494 timer16: timer@0 {
3495 compatible = "ti,omap5430-timer";
3496 reg = <0x0 0x80>;
3497 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
3498 clock-names = "fck";
3499 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
3500 };
3501 };
3502
3503 rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
3504 compatible = "ti,sysc-omap4-simple", "ti,sysc";
3505 ti,hwmods = "rtcss";
3506 reg = <0x38074 0x4>,
3507 <0x38078 0x4>;
3508 reg-names = "rev", "sysc";
3509 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3510 <SYSC_IDLE_NO>,
3511 <SYSC_IDLE_SMART>,
3512 <SYSC_IDLE_SMART_WKUP>;
3513 /* Domains (P, C): rtc_pwrdm, rtc_clkdm */
3514 clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3515 clock-names = "fck";
3516 #address-cells = <1>;
3517 #size-cells = <1>;
3518 ranges = <0x0 0x38000 0x1000>;
3519
3520 rtc: rtc@0 {
3521 compatible = "ti,am3352-rtc";
3522 reg = <0x0 0x100>;
3523 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
3524 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
3525 clocks = <&sys_32k_ck>;
3526 };
3527 };
3528
3529 target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
3530 compatible = "ti,sysc-omap4", "ti,sysc";
3531 ti,hwmods = "mailbox2";
3532 reg = <0x3a000 0x4>,
3533 <0x3a010 0x4>;
3534 reg-names = "rev", "sysc";
3535 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3536 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3537 <SYSC_IDLE_NO>,
3538 <SYSC_IDLE_SMART>;
3539 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3540 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3541 clock-names = "fck";
3542 #address-cells = <1>;
3543 #size-cells = <1>;
3544 ranges = <0x0 0x3a000 0x1000>;
3545
3546 mailbox2: mailbox@0 {
3547 compatible = "ti,omap4-mailbox";
3548 reg = <0x0 0x200>;
3549 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3551 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
3552 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
3553 #mbox-cells = <1>;
3554 ti,mbox-num-users = <4>;
3555 ti,mbox-num-fifos = <12>;
3556 status = "disabled";
3557 };
3558 };
3559
3560 target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
3561 compatible = "ti,sysc-omap4", "ti,sysc";
3562 ti,hwmods = "mailbox3";
3563 reg = <0x3c000 0x4>,
3564 <0x3c010 0x4>;
3565 reg-names = "rev", "sysc";
3566 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3567 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3568 <SYSC_IDLE_NO>,
3569 <SYSC_IDLE_SMART>;
3570 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3571 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3572 clock-names = "fck";
3573 #address-cells = <1>;
3574 #size-cells = <1>;
3575 ranges = <0x0 0x3c000 0x1000>;
3576
3577 mailbox3: mailbox@0 {
3578 compatible = "ti,omap4-mailbox";
3579 reg = <0x0 0x200>;
3580 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3581 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3582 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
3584 #mbox-cells = <1>;
3585 ti,mbox-num-users = <4>;
3586 ti,mbox-num-fifos = <12>;
3587 status = "disabled";
3588 };
3589 };
3590
3591 target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
3592 compatible = "ti,sysc-omap4", "ti,sysc";
3593 ti,hwmods = "mailbox4";
3594 reg = <0x3e000 0x4>,
3595 <0x3e010 0x4>;
3596 reg-names = "rev", "sysc";
3597 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3598 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3599 <SYSC_IDLE_NO>,
3600 <SYSC_IDLE_SMART>;
3601 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3602 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3603 clock-names = "fck";
3604 #address-cells = <1>;
3605 #size-cells = <1>;
3606 ranges = <0x0 0x3e000 0x1000>;
3607
3608 mailbox4: mailbox@0 {
3609 compatible = "ti,omap4-mailbox";
3610 reg = <0x0 0x200>;
3611 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3612 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
3615 #mbox-cells = <1>;
3616 ti,mbox-num-users = <4>;
3617 ti,mbox-num-fifos = <12>;
3618 status = "disabled";
3619 };
3620 };
3621
3622 target-module@40000 { /* 0x48840000, ap 39 64.0 */
3623 compatible = "ti,sysc-omap4", "ti,sysc";
3624 ti,hwmods = "mailbox5";
3625 reg = <0x40000 0x4>,
3626 <0x40010 0x4>;
3627 reg-names = "rev", "sysc";
3628 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3629 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3630 <SYSC_IDLE_NO>,
3631 <SYSC_IDLE_SMART>;
3632 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3633 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3634 clock-names = "fck";
3635 #address-cells = <1>;
3636 #size-cells = <1>;
3637 ranges = <0x0 0x40000 0x1000>;
3638
3639 mailbox5: mailbox@0 {
3640 compatible = "ti,omap4-mailbox";
3641 reg = <0x0 0x200>;
3642 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3643 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3644 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3645 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
3646 #mbox-cells = <1>;
3647 ti,mbox-num-users = <4>;
3648 ti,mbox-num-fifos = <12>;
3649 status = "disabled";
3650 };
3651 };
3652
3653 target-module@42000 { /* 0x48842000, ap 41 4e.0 */
3654 compatible = "ti,sysc-omap4", "ti,sysc";
3655 ti,hwmods = "mailbox6";
3656 reg = <0x42000 0x4>,
3657 <0x42010 0x4>;
3658 reg-names = "rev", "sysc";
3659 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3660 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3661 <SYSC_IDLE_NO>,
3662 <SYSC_IDLE_SMART>;
3663 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3664 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3665 clock-names = "fck";
3666 #address-cells = <1>;
3667 #size-cells = <1>;
3668 ranges = <0x0 0x42000 0x1000>;
3669
3670 mailbox6: mailbox@0 {
3671 compatible = "ti,omap4-mailbox";
3672 reg = <0x0 0x200>;
3673 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3674 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3675 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3676 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
3677 #mbox-cells = <1>;
3678 ti,mbox-num-users = <4>;
3679 ti,mbox-num-fifos = <12>;
3680 status = "disabled";
3681 };
3682 };
3683
3684 target-module@44000 { /* 0x48844000, ap 43 42.0 */
3685 compatible = "ti,sysc-omap4", "ti,sysc";
3686 ti,hwmods = "mailbox7";
3687 reg = <0x44000 0x4>,
3688 <0x44010 0x4>;
3689 reg-names = "rev", "sysc";
3690 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3691 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3692 <SYSC_IDLE_NO>,
3693 <SYSC_IDLE_SMART>;
3694 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3695 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3696 clock-names = "fck";
3697 #address-cells = <1>;
3698 #size-cells = <1>;
3699 ranges = <0x0 0x44000 0x1000>;
3700
3701 mailbox7: mailbox@0 {
3702 compatible = "ti,omap4-mailbox";
3703 reg = <0x0 0x200>;
3704 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
3705 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
3706 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
3707 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
3708 #mbox-cells = <1>;
3709 ti,mbox-num-users = <4>;
3710 ti,mbox-num-fifos = <12>;
3711 status = "disabled";
3712 };
3713 };
3714
3715 target-module@46000 { /* 0x48846000, ap 45 48.0 */
3716 compatible = "ti,sysc-omap4", "ti,sysc";
3717 ti,hwmods = "mailbox8";
3718 reg = <0x46000 0x4>,
3719 <0x46010 0x4>;
3720 reg-names = "rev", "sysc";
3721 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3722 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3723 <SYSC_IDLE_NO>,
3724 <SYSC_IDLE_SMART>;
3725 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3726 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3727 clock-names = "fck";
3728 #address-cells = <1>;
3729 #size-cells = <1>;
3730 ranges = <0x0 0x46000 0x1000>;
3731
3732 mailbox8: mailbox@0 {
3733 compatible = "ti,omap4-mailbox";
3734 reg = <0x0 0x200>;
3735 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3736 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3737 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3738 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
3739 #mbox-cells = <1>;
3740 ti,mbox-num-users = <4>;
3741 ti,mbox-num-fifos = <12>;
3742 status = "disabled";
3743 };
3744 };
3745
3746 target-module@48000 { /* 0x48848000, ap 47 36.0 */
3747 compatible = "ti,sysc";
3748 status = "disabled";
3749 #address-cells = <1>;
3750 #size-cells = <1>;
3751 ranges = <0x0 0x48000 0x1000>;
3752 };
3753
3754 target-module@4a000 { /* 0x4884a000, ap 49 38.0 */
3755 compatible = "ti,sysc";
3756 status = "disabled";
3757 #address-cells = <1>;
3758 #size-cells = <1>;
3759 ranges = <0x0 0x4a000 0x1000>;
3760 };
3761
3762 target-module@4c000 { /* 0x4884c000, ap 51 44.0 */
3763 compatible = "ti,sysc";
3764 status = "disabled";
3765 #address-cells = <1>;
3766 #size-cells = <1>;
3767 ranges = <0x0 0x4c000 0x1000>;
3768 };
3769
3770 target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */
3771 compatible = "ti,sysc";
3772 status = "disabled";
3773 #address-cells = <1>;
3774 #size-cells = <1>;
3775 ranges = <0x0 0x4e000 0x1000>;
3776 };
3777
3778 target-module@50000 { /* 0x48850000, ap 55 40.0 */
3779 compatible = "ti,sysc";
3780 status = "disabled";
3781 #address-cells = <1>;
3782 #size-cells = <1>;
3783 ranges = <0x0 0x50000 0x1000>;
3784 };
3785
3786 target-module@52000 { /* 0x48852000, ap 57 54.0 */
3787 compatible = "ti,sysc";
3788 status = "disabled";
3789 #address-cells = <1>;
3790 #size-cells = <1>;
3791 ranges = <0x0 0x52000 0x1000>;
3792 };
3793
3794 target-module@54000 { /* 0x48854000, ap 59 1a.0 */
3795 compatible = "ti,sysc";
3796 status = "disabled";
3797 #address-cells = <1>;
3798 #size-cells = <1>;
3799 ranges = <0x0 0x54000 0x1000>;
3800 };
3801
3802 target-module@56000 { /* 0x48856000, ap 61 22.0 */
3803 compatible = "ti,sysc";
3804 status = "disabled";
3805 #address-cells = <1>;
3806 #size-cells = <1>;
3807 ranges = <0x0 0x56000 0x1000>;
3808 };
3809
3810 target-module@58000 { /* 0x48858000, ap 63 2a.0 */
3811 compatible = "ti,sysc";
3812 status = "disabled";
3813 #address-cells = <1>;
3814 #size-cells = <1>;
3815 ranges = <0x0 0x58000 0x1000>;
3816 };
3817
3818 target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */
3819 compatible = "ti,sysc";
3820 status = "disabled";
3821 #address-cells = <1>;
3822 #size-cells = <1>;
3823 ranges = <0x0 0x5a000 0x1000>;
3824 };
3825
3826 target-module@5c000 { /* 0x4885c000, ap 31 32.0 */
3827 compatible = "ti,sysc";
3828 status = "disabled";
3829 #address-cells = <1>;
3830 #size-cells = <1>;
3831 ranges = <0x0 0x5c000 0x1000>;
3832 };
3833
3834 target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
3835 compatible = "ti,sysc-omap4", "ti,sysc";
3836 ti,hwmods = "mailbox9";
3837 reg = <0x5e000 0x4>,
3838 <0x5e010 0x4>;
3839 reg-names = "rev", "sysc";
3840 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3841 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3842 <SYSC_IDLE_NO>,
3843 <SYSC_IDLE_SMART>;
3844 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3845 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3846 clock-names = "fck";
3847 #address-cells = <1>;
3848 #size-cells = <1>;
3849 ranges = <0x0 0x5e000 0x1000>;
3850
3851 mailbox9: mailbox@0 {
3852 compatible = "ti,omap4-mailbox";
3853 reg = <0x0 0x200>;
3854 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
3855 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3856 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3857 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3858 #mbox-cells = <1>;
3859 ti,mbox-num-users = <4>;
3860 ti,mbox-num-fifos = <12>;
3861 status = "disabled";
3862 };
3863 };
3864
3865 target-module@60000 { /* 0x48860000, ap 71 4a.0 */
3866 compatible = "ti,sysc-omap4", "ti,sysc";
3867 ti,hwmods = "mailbox10";
3868 reg = <0x60000 0x4>,
3869 <0x60010 0x4>;
3870 reg-names = "rev", "sysc";
3871 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3872 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3873 <SYSC_IDLE_NO>,
3874 <SYSC_IDLE_SMART>;
3875 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3876 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3877 clock-names = "fck";
3878 #address-cells = <1>;
3879 #size-cells = <1>;
3880 ranges = <0x0 0x60000 0x1000>;
3881
3882 mailbox10: mailbox@0 {
3883 compatible = "ti,omap4-mailbox";
3884 reg = <0x0 0x200>;
3885 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
3886 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
3887 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
3888 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3889 #mbox-cells = <1>;
3890 ti,mbox-num-users = <4>;
3891 ti,mbox-num-fifos = <12>;
3892 status = "disabled";
3893 };
3894 };
3895
3896 target-module@62000 { /* 0x48862000, ap 73 74.0 */
3897 compatible = "ti,sysc-omap4", "ti,sysc";
3898 ti,hwmods = "mailbox11";
3899 reg = <0x62000 0x4>,
3900 <0x62010 0x4>;
3901 reg-names = "rev", "sysc";
3902 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3903 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3904 <SYSC_IDLE_NO>,
3905 <SYSC_IDLE_SMART>;
3906 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3907 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3908 clock-names = "fck";
3909 #address-cells = <1>;
3910 #size-cells = <1>;
3911 ranges = <0x0 0x62000 0x1000>;
3912
3913 mailbox11: mailbox@0 {
3914 compatible = "ti,omap4-mailbox";
3915 reg = <0x0 0x200>;
3916 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
3917 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
3918 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
3919 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
3920 #mbox-cells = <1>;
3921 ti,mbox-num-users = <4>;
3922 ti,mbox-num-fifos = <12>;
3923 status = "disabled";
3924 };
3925 };
3926
3927 target-module@64000 { /* 0x48864000, ap 67 52.0 */
3928 compatible = "ti,sysc-omap4", "ti,sysc";
3929 ti,hwmods = "mailbox12";
3930 reg = <0x64000 0x4>,
3931 <0x64010 0x4>;
3932 reg-names = "rev", "sysc";
3933 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3934 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3935 <SYSC_IDLE_NO>,
3936 <SYSC_IDLE_SMART>;
3937 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3938 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3939 clock-names = "fck";
3940 #address-cells = <1>;
3941 #size-cells = <1>;
3942 ranges = <0x0 0x64000 0x1000>;
3943
3944 mailbox12: mailbox@0 {
3945 compatible = "ti,omap4-mailbox";
3946 reg = <0x0 0x200>;
3947 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
3948 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
3949 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
3950 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
3951 #mbox-cells = <1>;
3952 ti,mbox-num-users = <4>;
3953 ti,mbox-num-fifos = <12>;
3954 status = "disabled";
3955 };
3956 };
3957
3958 target-module@80000 { /* 0x48880000, ap 83 0e.1 */
3959 compatible = "ti,sysc-omap4", "ti,sysc";
3960 ti,hwmods = "usb_otg_ss1";
3961 reg = <0x80000 0x4>,
3962 <0x80010 0x4>;
3963 reg-names = "rev", "sysc";
3964 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
3965 ti,sysc-midle = <SYSC_IDLE_FORCE>,
3966 <SYSC_IDLE_NO>,
3967 <SYSC_IDLE_SMART>,
3968 <SYSC_IDLE_SMART_WKUP>;
3969 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3970 <SYSC_IDLE_NO>,
3971 <SYSC_IDLE_SMART>,
3972 <SYSC_IDLE_SMART_WKUP>;
3973 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
3974 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
3975 clock-names = "fck";
3976 #address-cells = <1>;
3977 #size-cells = <1>;
3978 ranges = <0x0 0x80000 0x20000>;
3979
3980 omap_dwc3_1: omap_dwc3_1@0 {
3981 compatible = "ti,dwc3";
3982 reg = <0x0 0x10000>;
3983 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3984 #address-cells = <1>;
3985 #size-cells = <1>;
3986 utmi-mode = <2>;
3987 ranges = <0 0 0x20000>;
3988
3989 usb1: usb@10000 {
3990 compatible = "snps,dwc3";
3991 reg = <0x10000 0x17000>;
3992 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
3993 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
3994 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3995 interrupt-names = "peripheral",
3996 "host",
3997 "otg";
3998 phys = <&usb2_phy1>, <&usb3_phy1>;
3999 phy-names = "usb2-phy", "usb3-phy";
4000 maximum-speed = "super-speed";
4001 dr_mode = "otg";
4002 snps,dis_u3_susphy_quirk;
4003 snps,dis_u2_susphy_quirk;
4004 };
4005 };
4006 };
4007
4008 target-module@c0000 { /* 0x488c0000, ap 79 06.0 */
4009 compatible = "ti,sysc-omap4", "ti,sysc";
4010 ti,hwmods = "usb_otg_ss2";
4011 reg = <0xc0000 0x4>,
4012 <0xc0010 0x4>;
4013 reg-names = "rev", "sysc";
4014 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4015 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4016 <SYSC_IDLE_NO>,
4017 <SYSC_IDLE_SMART>,
4018 <SYSC_IDLE_SMART_WKUP>;
4019 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4020 <SYSC_IDLE_NO>,
4021 <SYSC_IDLE_SMART>,
4022 <SYSC_IDLE_SMART_WKUP>;
4023 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4024 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4025 clock-names = "fck";
4026 #address-cells = <1>;
4027 #size-cells = <1>;
4028 ranges = <0x0 0xc0000 0x20000>;
4029
4030 omap_dwc3_2: omap_dwc3_2@0 {
4031 compatible = "ti,dwc3";
4032 reg = <0x0 0x10000>;
4033 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4034 #address-cells = <1>;
4035 #size-cells = <1>;
4036 utmi-mode = <2>;
4037 ranges = <0 0 0x20000>;
4038
4039 usb2: usb@10000 {
4040 compatible = "snps,dwc3";
4041 reg = <0x10000 0x17000>;
4042 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4043 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4044 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4045 interrupt-names = "peripheral",
4046 "host",
4047 "otg";
4048 phys = <&usb2_phy2>;
4049 phy-names = "usb2-phy";
4050 maximum-speed = "high-speed";
4051 dr_mode = "otg";
4052 snps,dis_u3_susphy_quirk;
4053 snps,dis_u2_susphy_quirk;
4054 snps,dis_metastability_quirk;
4055 };
4056 };
4057 };
4058
4059 usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */
4060 compatible = "ti,sysc-omap4", "ti,sysc";
4061 ti,hwmods = "usb_otg_ss3";
4062 reg = <0x100000 0x4>,
4063 <0x100010 0x4>;
4064 reg-names = "rev", "sysc";
4065 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4066 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4067 <SYSC_IDLE_NO>,
4068 <SYSC_IDLE_SMART>,
4069 <SYSC_IDLE_SMART_WKUP>;
4070 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4071 <SYSC_IDLE_NO>,
4072 <SYSC_IDLE_SMART>,
4073 <SYSC_IDLE_SMART_WKUP>;
4074 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4075 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4076 clock-names = "fck";
4077 #address-cells = <1>;
4078 #size-cells = <1>;
4079 ranges = <0x0 0x100000 0x20000>;
4080
4081 omap_dwc3_3: omap_dwc3_3@0 {
4082 compatible = "ti,dwc3";
4083 reg = <0x0 0x10000>;
4084 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4085 #address-cells = <1>;
4086 #size-cells = <1>;
4087 utmi-mode = <2>;
4088 ranges = <0 0 0x20000>;
4089 status = "disabled";
4090
4091 usb3: usb@10000 {
4092 compatible = "snps,dwc3";
4093 reg = <0x10000 0x17000>;
4094 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4095 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4096 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4097 interrupt-names = "peripheral",
4098 "host",
4099 "otg";
4100 maximum-speed = "high-speed";
4101 dr_mode = "otg";
4102 snps,dis_u3_susphy_quirk;
4103 snps,dis_u2_susphy_quirk;
4104 };
4105 };
4106 };
4107
4108 usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
4109 compatible = "ti,sysc-omap4", "ti,sysc";
4110 ti,hwmods = "usb_otg_ss4";
4111 reg = <0x140000 0x4>,
4112 <0x140010 0x4>;
4113 reg-names = "rev", "sysc";
4114 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4115 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4116 <SYSC_IDLE_NO>,
4117 <SYSC_IDLE_SMART>,
4118 <SYSC_IDLE_SMART_WKUP>;
4119 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4120 <SYSC_IDLE_NO>,
4121 <SYSC_IDLE_SMART>,
4122 <SYSC_IDLE_SMART_WKUP>;
4123 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4124 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
4125 clock-names = "fck";
4126 #address-cells = <1>;
4127 #size-cells = <1>;
4128 ranges = <0x0 0x140000 0x20000>;
4129 };
4130
4131 target-module@170000 { /* 0x48970000, ap 21 0a.0 */
4132 compatible = "ti,sysc";
4133 status = "disabled";
4134 #address-cells = <1>;
4135 #size-cells = <1>;
4136 ranges = <0x0 0x170000 0x10000>;
4137 };
4138
4139 target-module@190000 { /* 0x48990000, ap 23 2e.0 */
4140 compatible = "ti,sysc";
4141 status = "disabled";
4142 #address-cells = <1>;
4143 #size-cells = <1>;
4144 ranges = <0x0 0x190000 0x10000>;
4145 };
4146
4147 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
4148 compatible = "ti,sysc";
4149 status = "disabled";
4150 #address-cells = <1>;
4151 #size-cells = <1>;
4152 ranges = <0x0 0x1b0000 0x10000>;
4153 };
4154
4155 target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */
4156 compatible = "ti,sysc";
4157 status = "disabled";
4158 #address-cells = <1>;
4159 #size-cells = <1>;
4160 ranges = <0x0 0x1d0000 0x10000>;
4161 };
4162 };
4163};
4164
4165&l4_wkup { /* 0x4ae00000 */
4166 compatible = "ti,dra7-l4-wkup", "simple-bus";
4167 reg = <0x4ae00000 0x800>,
4168 <0x4ae00800 0x800>,
4169 <0x4ae01000 0x1000>;
4170 reg-names = "ap", "la", "ia0";
4171 #address-cells = <1>;
4172 #size-cells = <1>;
4173 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
4174 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
4175 <0x00020000 0x4ae20000 0x010000>, /* segment 2 */
4176 <0x00030000 0x4ae30000 0x010000>; /* segment 3 */
4177
4178 segment@0 { /* 0x4ae00000 */
4179 compatible = "simple-bus";
4180 #address-cells = <1>;
4181 #size-cells = <1>;
4182 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
4183 <0x00001000 0x00001000 0x001000>, /* ap 1 */
4184 <0x00000800 0x00000800 0x000800>, /* ap 2 */
4185 <0x00006000 0x00006000 0x002000>, /* ap 3 */
4186 <0x00008000 0x00008000 0x001000>, /* ap 4 */
4187 <0x00004000 0x00004000 0x001000>, /* ap 15 */
4188 <0x00005000 0x00005000 0x001000>, /* ap 16 */
4189 <0x0000c000 0x0000c000 0x001000>, /* ap 17 */
4190 <0x0000d000 0x0000d000 0x001000>; /* ap 18 */
4191
4192 target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
4193 compatible = "ti,sysc-omap2", "ti,sysc";
4194 ti,hwmods = "counter_32k";
4195 reg = <0x4000 0x4>,
4196 <0x4010 0x4>;
4197 reg-names = "rev", "sysc";
4198 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4199 <SYSC_IDLE_NO>,
4200 <SYSC_IDLE_SMART>,
4201 <SYSC_IDLE_SMART_WKUP>;
4202 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4203 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4204 clock-names = "fck";
4205 #address-cells = <1>;
4206 #size-cells = <1>;
4207 ranges = <0x0 0x4000 0x1000>;
4208
4209 counter32k: counter@0 {
4210 compatible = "ti,omap-counter32k";
4211 reg = <0x0 0x40>;
4212 };
4213 };
4214
4215 target-module@6000 { /* 0x4ae06000, ap 3 10.0 */
4216 compatible = "ti,sysc-omap4", "ti,sysc";
4217 reg = <0x6000 0x4>;
4218 reg-names = "rev";
4219 #address-cells = <1>;
4220 #size-cells = <1>;
4221 ranges = <0x0 0x6000 0x2000>;
4222
4223 prm: prm@0 {
4224 compatible = "ti,dra7-prm", "simple-bus";
4225 reg = <0 0x3000>;
4226 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4227 #address-cells = <1>;
4228 #size-cells = <1>;
4229 ranges = <0 0 0x3000>;
4230
4231 prm_clocks: clocks {
4232 #address-cells = <1>;
4233 #size-cells = <0>;
4234 };
4235
4236 prm_clockdomains: clockdomains {
4237 };
4238 };
4239 };
4240
4241 target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */
4242 compatible = "ti,sysc-omap4", "ti,sysc";
4243 reg = <0xc000 0x4>;
4244 reg-names = "rev";
4245 #address-cells = <1>;
4246 #size-cells = <1>;
4247 ranges = <0x0 0xc000 0x1000>;
4248
4249 scm_wkup: scm_conf@0 {
4250 compatible = "syscon";
4251 reg = <0 0x1000>;
4252 };
4253 };
4254 };
4255
4256 segment@10000 { /* 0x4ae10000 */
4257 compatible = "simple-bus";
4258 #address-cells = <1>;
4259 #size-cells = <1>;
4260 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
4261 <0x00001000 0x00011000 0x001000>, /* ap 6 */
4262 <0x00004000 0x00014000 0x001000>, /* ap 7 */
4263 <0x00005000 0x00015000 0x001000>, /* ap 8 */
4264 <0x00008000 0x00018000 0x001000>, /* ap 9 */
4265 <0x00009000 0x00019000 0x001000>, /* ap 10 */
4266 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
4267 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
4268
4269 target-module@0 { /* 0x4ae10000, ap 5 20.0 */
4270 compatible = "ti,sysc-omap2", "ti,sysc";
4271 reg = <0x0 0x4>,
4272 <0x10 0x4>,
4273 <0x114 0x4>;
4274 reg-names = "rev", "sysc", "syss";
4275 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4276 SYSC_OMAP2_SOFTRESET |
4277 SYSC_OMAP2_AUTOIDLE)>;
4278 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4279 <SYSC_IDLE_NO>,
4280 <SYSC_IDLE_SMART>,
4281 <SYSC_IDLE_SMART_WKUP>;
4282 ti,syss-mask = <1>;
4283 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4284 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4285 <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>;
4286 clock-names = "fck", "dbclk";
4287 #address-cells = <1>;
4288 #size-cells = <1>;
4289 ranges = <0x0 0x0 0x1000>;
4290
4291 gpio1: gpio@0 {
4292 compatible = "ti,omap4-gpio";
4293 reg = <0x0 0x200>;
4294 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
4295 gpio-controller;
4296 #gpio-cells = <2>;
4297 interrupt-controller;
4298 #interrupt-cells = <2>;
4299 };
4300 };
4301
4302 target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
4303 compatible = "ti,sysc-omap2", "ti,sysc";
4304 ti,hwmods = "wd_timer2";
4305 reg = <0x4000 0x4>,
4306 <0x4010 0x4>,
4307 <0x4014 0x4>;
4308 reg-names = "rev", "sysc", "syss";
4309 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
4310 SYSC_OMAP2_SOFTRESET)>;
4311 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4312 <SYSC_IDLE_NO>,
4313 <SYSC_IDLE_SMART>,
4314 <SYSC_IDLE_SMART_WKUP>;
4315 ti,syss-mask = <1>;
4316 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4317 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4318 clock-names = "fck";
4319 #address-cells = <1>;
4320 #size-cells = <1>;
4321 ranges = <0x0 0x4000 0x1000>;
4322
4323 wdt2: wdt@0 {
4324 compatible = "ti,omap3-wdt";
4325 reg = <0x0 0x80>;
4326 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4327 };
4328 };
4329
4330 target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
4331 compatible = "ti,sysc-omap4-timer", "ti,sysc";
4332 ti,hwmods = "timer1";
4333 reg = <0x8000 0x4>,
4334 <0x8010 0x4>;
4335 reg-names = "rev", "sysc";
4336 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4337 SYSC_OMAP4_SOFTRESET)>;
4338 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4339 <SYSC_IDLE_NO>,
4340 <SYSC_IDLE_SMART>,
4341 <SYSC_IDLE_SMART_WKUP>;
4342 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4343 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4344 clock-names = "fck";
4345 #address-cells = <1>;
4346 #size-cells = <1>;
4347 ranges = <0x0 0x8000 0x1000>;
4348
4349 timer1: timer@0 {
4350 compatible = "ti,omap5430-timer";
4351 reg = <0x0 0x80>;
4352 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
4353 clock-names = "fck";
4354 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4355 ti,timer-alwon;
4356 };
4357 };
4358
4359 target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */
4360 compatible = "ti,sysc";
4361 status = "disabled";
4362 #address-cells = <1>;
4363 #size-cells = <1>;
4364 ranges = <0x0 0xc000 0x1000>;
4365 };
4366 };
4367
4368 segment@20000 { /* 0x4ae20000 */
4369 compatible = "simple-bus";
4370 #address-cells = <1>;
4371 #size-cells = <1>;
4372 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
4373 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
4374 <0x00000000 0x00020000 0x001000>, /* ap 19 */
4375 <0x00001000 0x00021000 0x001000>, /* ap 20 */
4376 <0x00002000 0x00022000 0x001000>, /* ap 21 */
4377 <0x00003000 0x00023000 0x001000>, /* ap 22 */
4378 <0x00007000 0x00027000 0x000400>, /* ap 23 */
4379 <0x00008000 0x00028000 0x000800>, /* ap 24 */
4380 <0x00009000 0x00029000 0x000100>, /* ap 25 */
4381 <0x00008800 0x00028800 0x000200>, /* ap 26 */
4382 <0x00008a00 0x00028a00 0x000100>, /* ap 27 */
4383 <0x0000b000 0x0002b000 0x001000>, /* ap 28 */
4384 <0x0000c000 0x0002c000 0x001000>, /* ap 29 */
4385 <0x0000f000 0x0002f000 0x001000>; /* ap 32 */
4386
4387 target-module@0 { /* 0x4ae20000, ap 19 08.0 */
4388 compatible = "ti,sysc-omap4-timer", "ti,sysc";
4389 ti,hwmods = "timer12";
4390 reg = <0x0 0x4>,
4391 <0x10 0x4>;
4392 reg-names = "rev", "sysc";
4393 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4394 SYSC_OMAP4_SOFTRESET)>;
4395 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4396 <SYSC_IDLE_NO>,
4397 <SYSC_IDLE_SMART>,
4398 <SYSC_IDLE_SMART_WKUP>;
4399 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4400 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4401 clock-names = "fck";
4402 #address-cells = <1>;
4403 #size-cells = <1>;
4404 ranges = <0x0 0x0 0x1000>;
4405
4406 timer12: timer@0 {
4407 compatible = "ti,omap5430-timer";
4408 reg = <0x0 0x80>;
4409 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
4410 ti,timer-alwon;
4411 ti,timer-secure;
4412 };
4413 };
4414
4415 target-module@2000 { /* 0x4ae22000, ap 21 18.0 */
4416 compatible = "ti,sysc";
4417 status = "disabled";
4418 #address-cells = <1>;
4419 #size-cells = <1>;
4420 ranges = <0x0 0x2000 0x1000>;
4421 };
4422
4423 target-module@6000 { /* 0x4ae26000, ap 13 48.0 */
4424 compatible = "ti,sysc";
4425 status = "disabled";
4426 #address-cells = <1>;
4427 #size-cells = <1>;
4428 ranges = <0x00000000 0x00006000 0x00001000>,
4429 <0x00001000 0x00007000 0x00000400>,
4430 <0x00002000 0x00008000 0x00000800>,
4431 <0x00002800 0x00008800 0x00000200>,
4432 <0x00002a00 0x00008a00 0x00000100>,
4433 <0x00003000 0x00009000 0x00000100>;
4434 };
4435
4436 target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */
4437 compatible = "ti,sysc-omap2", "ti,sysc";
4438 reg = <0xb050 0x4>,
4439 <0xb054 0x4>,
4440 <0xb058 0x4>;
4441 reg-names = "rev", "sysc", "syss";
4442 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4443 SYSC_OMAP2_SOFTRESET |
4444 SYSC_OMAP2_AUTOIDLE)>;
4445 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4446 <SYSC_IDLE_NO>,
4447 <SYSC_IDLE_SMART>,
4448 <SYSC_IDLE_SMART_WKUP>;
4449 ti,syss-mask = <1>;
4450 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4451 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4452 clock-names = "fck";
4453 #address-cells = <1>;
4454 #size-cells = <1>;
4455 ranges = <0x0 0xb000 0x1000>;
4456
4457 uart10: serial@0 {
4458 compatible = "ti,dra742-uart", "ti,omap4-uart";
4459 reg = <0x0 0x100>;
4460 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
4461 clock-frequency = <48000000>;
4462 status = "disabled";
4463 };
4464 };
4465
4466 target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */
4467 compatible = "ti,sysc";
4468 status = "disabled";
4469 #address-cells = <1>;
4470 #size-cells = <1>;
4471 ranges = <0x0 0xf000 0x1000>;
4472 };
4473 };
4474
4475 segment@30000 { /* 0x4ae30000 */
4476 compatible = "simple-bus";
4477 #address-cells = <1>;
4478 #size-cells = <1>;
4479 ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */
4480 <0x0000e000 0x0003e000 0x001000>, /* ap 31 */
4481 <0x00000000 0x00030000 0x001000>, /* ap 33 */
4482 <0x00001000 0x00031000 0x001000>, /* ap 34 */
4483 <0x00002000 0x00032000 0x001000>, /* ap 35 */
4484 <0x00003000 0x00033000 0x001000>, /* ap 36 */
4485 <0x00004000 0x00034000 0x001000>, /* ap 37 */
4486 <0x00005000 0x00035000 0x001000>, /* ap 38 */
4487 <0x00006000 0x00036000 0x001000>, /* ap 39 */
4488 <0x00007000 0x00037000 0x001000>, /* ap 40 */
4489 <0x00008000 0x00038000 0x001000>, /* ap 41 */
4490 <0x00009000 0x00039000 0x001000>, /* ap 42 */
4491 <0x0000a000 0x0003a000 0x001000>; /* ap 43 */
4492
4493 target-module@1000 { /* 0x4ae31000, ap 34 60.0 */
4494 compatible = "ti,sysc";
4495 status = "disabled";
4496 #address-cells = <1>;
4497 #size-cells = <1>;
4498 ranges = <0x0 0x1000 0x1000>;
4499 };
4500
4501 target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */
4502 compatible = "ti,sysc";
4503 status = "disabled";
4504 #address-cells = <1>;
4505 #size-cells = <1>;
4506 ranges = <0x0 0x3000 0x1000>;
4507 };
4508
4509 target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */
4510 compatible = "ti,sysc";
4511 status = "disabled";
4512 #address-cells = <1>;
4513 #size-cells = <1>;
4514 ranges = <0x0 0x5000 0x1000>;
4515 };
4516
4517 target-module@7000 { /* 0x4ae37000, ap 40 68.0 */
4518 compatible = "ti,sysc";
4519 status = "disabled";
4520 #address-cells = <1>;
4521 #size-cells = <1>;
4522 ranges = <0x0 0x7000 0x1000>;
4523 };
4524
4525 target-module@9000 { /* 0x4ae39000, ap 42 70.0 */
4526 compatible = "ti,sysc";
4527 status = "disabled";
4528 #address-cells = <1>;
4529 #size-cells = <1>;
4530 ranges = <0x0 0x9000 0x1000>;
4531 };
4532
4533 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */
4534 compatible = "ti,sysc-omap4", "ti,sysc";
4535 reg = <0xc020 0x4>;
4536 reg-names = "rev";
4537 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4538 clock-names = "fck";
4539 #address-cells = <1>;
4540 #size-cells = <1>;
4541 ranges = <0x0 0xc000 0x2000>;
4542
4543 dcan1: can@0 {
4544 compatible = "ti,dra7-d_can";
4545 reg = <0x0 0x2000>;
4546 syscon-raminit = <&scm_conf 0x558 0>;
4547 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
4548 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>;
4549 status = "disabled";
4550 };
4551 };
4552 };
4553};
4554