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1/*
2 * Copyright 2014 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23/dts-v1/;
24#include <dt-bindings/interrupt-controller/irq.h>
25#include <dt-bindings/gpio/gpio.h>
26#include "skeleton.dtsi"
27
28/ {
29 model = "ARM RealView PB1176";
30 compatible = "arm,realview-pb1176";
31
32 chosen { };
33
34 aliases {
35 serial0 = &pb1176_serial0;
36 serial1 = &pb1176_serial1;
37 serial2 = &pb1176_serial2;
38 serial3 = &pb1176_serial3;
39 serial4 = &fpga_serial;
40 };
41
42 memory {
43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
45 };
46
47 /* The voltage to the MMC card is hardwired at 3.3V */
48 vmmc: fixedregulator@0 {
49 compatible = "regulator-fixed";
50 regulator-name = "vmmc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 regulator-boot-on;
54 };
55
56 veth: fixedregulator@0 {
57 compatible = "regulator-fixed";
58 regulator-name = "veth";
59 regulator-min-microvolt = <3300000>;
60 regulator-max-microvolt = <3300000>;
61 regulator-boot-on;
62 };
63
64 xtal24mhz: xtal24mhz@24M {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <24000000>;
68 };
69
70 timclk: timclk@1M {
71 #clock-cells = <0>;
72 compatible = "fixed-factor-clock";
73 clock-div = <24>;
74 clock-mult = <1>;
75 clocks = <&xtal24mhz>;
76 };
77
78 mclk: mclk@24M {
79 #clock-cells = <0>;
80 compatible = "fixed-factor-clock";
81 clock-div = <1>;
82 clock-mult = <1>;
83 clocks = <&xtal24mhz>;
84 };
85
86 kmiclk: kmiclk@24M {
87 #clock-cells = <0>;
88 compatible = "fixed-factor-clock";
89 clock-div = <1>;
90 clock-mult = <1>;
91 clocks = <&xtal24mhz>;
92 };
93
94 sspclk: sspclk@24M {
95 #clock-cells = <0>;
96 compatible = "fixed-factor-clock";
97 clock-div = <1>;
98 clock-mult = <1>;
99 clocks = <&xtal24mhz>;
100 };
101
102 uartclk: uartclk@24M {
103 #clock-cells = <0>;
104 compatible = "fixed-factor-clock";
105 clock-div = <1>;
106 clock-mult = <1>;
107 clocks = <&xtal24mhz>;
108 };
109
110 /* FIXME: this actually hangs off the PLL clocks */
111 pclk: pclk@0 {
112 #clock-cells = <0>;
113 compatible = "fixed-clock";
114 clock-frequency = <0>;
115 };
116
117 flash@30000000 {
118 compatible = "arm,versatile-flash", "cfi-flash";
119 reg = <0x30000000 0x4000000>;
120 bank-width = <4>;
121 };
122
123 fpga_flash@38000000 {
124 compatible = "arm,versatile-flash", "cfi-flash";
125 reg = <0x38000000 0x800000>;
126 bank-width = <4>;
127 };
128
129 /*
130 * The "secure flash" contains things like the boot
131 * monitor so we don't want people to accidentally
132 * screw this up. Mark the device tree node disabled
133 * by default.
134 */
135 secflash@3c000000 {
136 compatible = "arm,versatile-flash", "cfi-flash";
137 reg = <0x3c000000 0x4000000>;
138 bank-width = <4>;
139 status = "disabled";
140 };
141
142 /* SMSC 9118 ethernet with PHY and EEPROM */
143 ethernet@3a000000 {
144 compatible = "smsc,lan9118", "smsc,lan9115";
145 reg = <0x3a000000 0x10000>;
146 interrupt-parent = <&intc_fpga1176>;
147 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
148 phy-mode = "mii";
149 reg-io-width = <4>;
150 smsc,irq-active-high;
151 smsc,irq-push-pull;
152 vdd33a-supply = <&veth>;
153 vddvario-supply = <&veth>;
154 };
155
156 usb@3b000000 {
157 compatible = "nxp,usb-isp1761";
158 reg = <0x3b000000 0x20000>;
159 interrupt-parent = <&intc_fpga1176>;
160 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
161 port1-otg;
162 };
163
164 bridge {
165 compatible = "ti,ths8134a", "ti,ths8134";
166 #address-cells = <1>;
167 #size-cells = <0>;
168
169 ports {
170 #address-cells = <1>;
171 #size-cells = <0>;
172
173 port@0 {
174 reg = <0>;
175
176 vga_bridge_in: endpoint {
177 remote-endpoint = <&clcd_pads>;
178 };
179 };
180
181 port@1 {
182 reg = <1>;
183
184 vga_bridge_out: endpoint {
185 remote-endpoint = <&vga_con_in>;
186 };
187 };
188 };
189 };
190
191 vga {
192 compatible = "vga-connector";
193
194 port {
195 vga_con_in: endpoint {
196 remote-endpoint = <&vga_bridge_out>;
197 };
198 };
199 };
200
201 soc {
202 #address-cells = <1>;
203 #size-cells = <1>;
204 compatible = "arm,realview-pb1176-soc", "simple-bus";
205 regmap = <&syscon>;
206 ranges;
207
208 syscon: syscon@10000000 {
209 compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
210 reg = <0x10000000 0x1000>;
211
212 led@08.0 {
213 compatible = "register-bit-led";
214 offset = <0x08>;
215 mask = <0x01>;
216 label = "versatile:0";
217 linux,default-trigger = "heartbeat";
218 default-state = "on";
219 };
220 led@08.1 {
221 compatible = "register-bit-led";
222 offset = <0x08>;
223 mask = <0x02>;
224 label = "versatile:1";
225 linux,default-trigger = "mmc0";
226 default-state = "off";
227 };
228 led@08.2 {
229 compatible = "register-bit-led";
230 offset = <0x08>;
231 mask = <0x04>;
232 label = "versatile:2";
233 linux,default-trigger = "cpu0";
234 default-state = "off";
235 };
236 led@08.3 {
237 compatible = "register-bit-led";
238 offset = <0x08>;
239 mask = <0x08>;
240 label = "versatile:3";
241 default-state = "off";
242 };
243 led@08.4 {
244 compatible = "register-bit-led";
245 offset = <0x08>;
246 mask = <0x10>;
247 label = "versatile:4";
248 default-state = "off";
249 };
250 led@08.5 {
251 compatible = "register-bit-led";
252 offset = <0x08>;
253 mask = <0x20>;
254 label = "versatile:5";
255 default-state = "off";
256 };
257 led@08.6 {
258 compatible = "register-bit-led";
259 offset = <0x08>;
260 mask = <0x40>;
261 label = "versatile:6";
262 default-state = "off";
263 };
264 led@08.7 {
265 compatible = "register-bit-led";
266 offset = <0x08>;
267 mask = <0x80>;
268 label = "versatile:7";
269 default-state = "off";
270 };
271 oscclk0: osc0@0c {
272 compatible = "arm,syscon-icst307";
273 #clock-cells = <0>;
274 lock-offset = <0x20>;
275 vco-offset = <0x0C>;
276 clocks = <&xtal24mhz>;
277 };
278 oscclk1: osc1@10 {
279 compatible = "arm,syscon-icst307";
280 #clock-cells = <0>;
281 lock-offset = <0x20>;
282 vco-offset = <0x10>;
283 clocks = <&xtal24mhz>;
284 };
285 oscclk2: osc2@14 {
286 compatible = "arm,syscon-icst307";
287 #clock-cells = <0>;
288 lock-offset = <0x20>;
289 vco-offset = <0x14>;
290 clocks = <&xtal24mhz>;
291 };
292 oscclk3: osc3@18 {
293 compatible = "arm,syscon-icst307";
294 #clock-cells = <0>;
295 lock-offset = <0x20>;
296 vco-offset = <0x18>;
297 clocks = <&xtal24mhz>;
298 };
299 oscclk4: osc4@1c {
300 compatible = "arm,syscon-icst307";
301 #clock-cells = <0>;
302 lock-offset = <0x20>;
303 vco-offset = <0x1c>;
304 clocks = <&xtal24mhz>;
305 };
306 };
307
308 /* Primary DevChip GIC synthesized with the CPU */
309 intc_dc1176: interrupt-controller@10120000 {
310 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
311 #interrupt-cells = <3>;
312 #address-cells = <1>;
313 interrupt-controller;
314 reg = <0x10121000 0x1000>,
315 <0x10120000 0x100>;
316 };
317
318 L2: l2-cache {
319 compatible = "arm,l220-cache";
320 reg = <0x10110000 0x1000>;
321 interrupt-parent = <&intc_dc1176>;
322 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
323 cache-unified;
324 cache-level = <2>;
325 /*
326 * Override default cache size, sets and
327 * associativity as these may be erroneously set
328 * up by boot loader(s).
329 */
330 arm,override-auxreg;
331 cache-size = <131072>; // 128kB
332 cache-sets = <512>;
333 cache-line-size = <32>;
334 };
335
336 pmu {
337 compatible = "arm,arm1176-pmu";
338 interrupt-parent = <&intc_dc1176>;
339 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
340 };
341
342 timer01: timer@10104000 {
343 compatible = "arm,sp804", "arm,primecell";
344 reg = <0x10104000 0x1000>;
345 interrupt-parent = <&intc_dc1176>;
346 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&timclk>, <&timclk>, <&pclk>;
348 clock-names = "timer1", "timer2", "apb_pclk";
349 };
350
351 timer23: timer@10105000 {
352 compatible = "arm,sp804", "arm,primecell";
353 reg = <0x10105000 0x1000>;
354 interrupt-parent = <&intc_dc1176>;
355 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
356 arm,sp804-has-irq = <1>;
357 clocks = <&timclk>, <&timclk>, <&pclk>;
358 clock-names = "timer1", "timer2", "apb_pclk";
359 };
360
361 pb1176_rtc: rtc@10108000 {
362 compatible = "arm,pl031", "arm,primecell";
363 reg = <0x10108000 0x1000>;
364 interrupt-parent = <&intc_dc1176>;
365 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&pclk>;
367 clock-names = "apb_pclk";
368 };
369
370 pb1176_gpio0: gpio@1010a000 {
371 compatible = "arm,pl061", "arm,primecell";
372 reg = <0x1010a000 0x1000>;
373 gpio-controller;
374 interrupt-parent = <&intc_dc1176>;
375 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
376 #gpio-cells = <2>;
377 interrupt-controller;
378 #interrupt-cells = <2>;
379 clocks = <&pclk>;
380 clock-names = "apb_pclk";
381 };
382
383 pb1176_ssp: ssp@1010b000 {
384 compatible = "arm,pl022", "arm,primecell";
385 reg = <0x1010b000 0x1000>;
386 interrupt-parent = <&intc_dc1176>;
387 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&sspclk>, <&pclk>;
389 clock-names = "SSPCLK", "apb_pclk";
390 };
391
392 pb1176_serial0: serial@1010c000 {
393 compatible = "arm,pl011", "arm,primecell";
394 reg = <0x1010c000 0x1000>;
395 interrupt-parent = <&intc_dc1176>;
396 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&uartclk>, <&pclk>;
398 clock-names = "uartclk", "apb_pclk";
399 };
400
401 pb1176_serial1: serial@1010d000 {
402 compatible = "arm,pl011", "arm,primecell";
403 reg = <0x1010d000 0x1000>;
404 interrupt-parent = <&intc_dc1176>;
405 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&uartclk>, <&pclk>;
407 clock-names = "uartclk", "apb_pclk";
408 };
409
410 pb1176_serial2: serial@1010e000 {
411 compatible = "arm,pl011", "arm,primecell";
412 reg = <0x1010e000 0x1000>;
413 interrupt-parent = <&intc_dc1176>;
414 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&uartclk>, <&pclk>;
416 clock-names = "uartclk", "apb_pclk";
417 };
418
419 pb1176_serial3: serial@1010f000 {
420 compatible = "arm,pl011", "arm,primecell";
421 reg = <0x1010f000 0x1000>;
422 interrupt-parent = <&intc_dc1176>;
423 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&uartclk>, <&pclk>;
425 clock-names = "uartclk", "apb_pclk";
426 };
427
428 /* Direct-mapped development chip ROM */
429 pb1176_rom@10200000 {
430 compatible = "direct-mapped";
431 reg = <0x10200000 0x4000>;
432 bank-width = <1>;
433 };
434
435 clcd@10112000 {
436 compatible = "arm,pl111", "arm,primecell";
437 reg = <0x10112000 0x1000>;
438 interrupt-parent = <&intc_dc1176>;
439 interrupt-names = "combined";
440 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&oscclk0>, <&pclk>;
442 clock-names = "clcdclk", "apb_pclk";
443 /* 1024x768 16bpp @65MHz works fine */
444 max-memory-bandwidth = <95000000>;
445
446 port {
447 clcd_pads: endpoint {
448 remote-endpoint = <&vga_bridge_in>;
449 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
450 };
451 };
452 };
453 };
454
455 /* These peripherals are inside the FPGA rather than the DevChip */
456 fpga {
457 #address-cells = <1>;
458 #size-cells = <1>;
459 compatible = "simple-bus";
460 ranges;
461
462 i2c0: i2c@10002000 {
463 #address-cells = <1>;
464 #size-cells = <0>;
465 compatible = "arm,versatile-i2c";
466 reg = <0x10002000 0x1000>;
467
468 rtc@68 {
469 compatible = "dallas,ds1338";
470 reg = <0x68>;
471 };
472 };
473
474 fpga_aaci: aaci@10004000 {
475 compatible = "arm,pl041", "arm,primecell";
476 reg = <0x10004000 0x1000>;
477 interrupt-parent = <&intc_fpga1176>;
478 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&pclk>;
480 clock-names = "apb_pclk";
481 };
482
483 fpga_mci: mmcsd@10005000 {
484 compatible = "arm,pl18x", "arm,primecell";
485 reg = <0x10005000 0x1000>;
486 interrupt-parent = <&intc_fpga1176>;
487 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
488 <0 2 IRQ_TYPE_LEVEL_HIGH>;
489 /* Due to frequent FIFO overruns, use just 500 kHz */
490 max-frequency = <500000>;
491 bus-width = <4>;
492 cap-sd-highspeed;
493 cap-mmc-highspeed;
494 clocks = <&mclk>, <&pclk>;
495 clock-names = "mclk", "apb_pclk";
496 vmmc-supply = <&vmmc>;
497 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
498 wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
499 };
500
501 fpga_kmi0: kmi@10006000 {
502 compatible = "arm,pl050", "arm,primecell";
503 reg = <0x10006000 0x1000>;
504 interrupt-parent = <&intc_fpga1176>;
505 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&kmiclk>, <&pclk>;
507 clock-names = "KMIREFCLK", "apb_pclk";
508 };
509
510 fpga_kmi1: kmi@10007000 {
511 compatible = "arm,pl050", "arm,primecell";
512 reg = <0x10007000 0x1000>;
513 interrupt-parent = <&intc_fpga1176>;
514 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&kmiclk>, <&pclk>;
516 clock-names = "KMIREFCLK", "apb_pclk";
517 };
518
519 fpga_charlcd: charlcd@10008000 {
520 compatible = "arm,versatile-lcd";
521 reg = <0x10008000 0x1000>;
522 interrupt-parent = <&intc_fpga1176>;
523 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&pclk>;
525 clock-names = "apb_pclk";
526 };
527
528 fpga_serial: serial@10009000 {
529 compatible = "arm,pl011", "arm,primecell";
530 reg = <0x10009000 0x1000>;
531 interrupt-parent = <&intc_fpga1176>;
532 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&uartclk>, <&pclk>;
534 clock-names = "uartclk", "apb_pclk";
535 };
536
537 /* This GIC on the board is cascaded off the DevChip GIC */
538 intc_fpga1176: interrupt-controller@10040000 {
539 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
540 #interrupt-cells = <3>;
541 #address-cells = <1>;
542 interrupt-controller;
543 reg = <0x10041000 0x1000>,
544 <0x10040000 0x100>;
545 interrupt-parent = <&intc_dc1176>;
546 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
547 };
548
549 fpga_gpio0: gpio@10014000 {
550 compatible = "arm,pl061", "arm,primecell";
551 reg = <0x10014000 0x1000>;
552 gpio-controller;
553 interrupt-parent = <&intc_fpga1176>;
554 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
555 #gpio-cells = <2>;
556 interrupt-controller;
557 #interrupt-cells = <2>;
558 clocks = <&pclk>;
559 clock-names = "apb_pclk";
560 };
561
562 fpga_gpio1: gpio@10015000 {
563 compatible = "arm,pl061", "arm,primecell";
564 reg = <0x10015000 0x1000>;
565 gpio-controller;
566 interrupt-parent = <&intc_fpga1176>;
567 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
568 #gpio-cells = <2>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
571 clocks = <&pclk>;
572 clock-names = "apb_pclk";
573 };
574
575 fpga_rtc: rtc@10017000 {
576 compatible = "arm,pl031", "arm,primecell";
577 reg = <0x10017000 0x1000>;
578 interrupt-parent = <&intc_fpga1176>;
579 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&pclk>;
581 clock-names = "apb_pclk";
582 };
583 };
584};
1/*
2 * Copyright 2014 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23/dts-v1/;
24#include <dt-bindings/interrupt-controller/irq.h>
25#include <dt-bindings/gpio/gpio.h>
26
27/ {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 model = "ARM RealView PB1176";
31 compatible = "arm,realview-pb1176";
32
33 chosen { };
34
35 aliases {
36 serial0 = &pb1176_serial0;
37 serial1 = &pb1176_serial1;
38 serial2 = &pb1176_serial2;
39 serial3 = &pb1176_serial3;
40 serial4 = &fpga_serial;
41 };
42
43 memory {
44 device_type = "memory";
45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
47 };
48
49 /* The voltage to the MMC card is hardwired at 3.3V */
50 vmmc: regulator-vmmc {
51 compatible = "regulator-fixed";
52 regulator-name = "vmmc";
53 regulator-min-microvolt = <3300000>;
54 regulator-max-microvolt = <3300000>;
55 regulator-boot-on;
56 };
57
58 veth: regulator-veth {
59 compatible = "regulator-fixed";
60 regulator-name = "veth";
61 regulator-min-microvolt = <3300000>;
62 regulator-max-microvolt = <3300000>;
63 regulator-boot-on;
64 };
65
66 xtal24mhz: xtal24mhz@24M {
67 #clock-cells = <0>;
68 compatible = "fixed-clock";
69 clock-frequency = <24000000>;
70 };
71
72 timclk: timclk@1M {
73 #clock-cells = <0>;
74 compatible = "fixed-factor-clock";
75 clock-div = <24>;
76 clock-mult = <1>;
77 clocks = <&xtal24mhz>;
78 };
79
80 mclk: mclk@24M {
81 #clock-cells = <0>;
82 compatible = "fixed-factor-clock";
83 clock-div = <1>;
84 clock-mult = <1>;
85 clocks = <&xtal24mhz>;
86 };
87
88 kmiclk: kmiclk@24M {
89 #clock-cells = <0>;
90 compatible = "fixed-factor-clock";
91 clock-div = <1>;
92 clock-mult = <1>;
93 clocks = <&xtal24mhz>;
94 };
95
96 sspclk: sspclk@24M {
97 #clock-cells = <0>;
98 compatible = "fixed-factor-clock";
99 clock-div = <1>;
100 clock-mult = <1>;
101 clocks = <&xtal24mhz>;
102 };
103
104 uartclk: uartclk@24M {
105 #clock-cells = <0>;
106 compatible = "fixed-factor-clock";
107 clock-div = <1>;
108 clock-mult = <1>;
109 clocks = <&xtal24mhz>;
110 };
111
112 /* FIXME: this actually hangs off the PLL clocks */
113 pclk: pclk@0 {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 clock-frequency = <0>;
117 };
118
119 flash@30000000 {
120 compatible = "arm,versatile-flash", "cfi-flash";
121 reg = <0x30000000 0x4000000>;
122 bank-width = <4>;
123 partitions {
124 compatible = "arm,arm-firmware-suite";
125 };
126 };
127
128 fpga_flash@38000000 {
129 compatible = "arm,versatile-flash", "cfi-flash";
130 reg = <0x38000000 0x800000>;
131 bank-width = <4>;
132 partitions {
133 compatible = "arm,arm-firmware-suite";
134 };
135 };
136
137 /*
138 * The "secure flash" contains things like the boot
139 * monitor so we don't want people to accidentally
140 * screw this up. Mark the device tree node disabled
141 * by default.
142 */
143 secflash@3c000000 {
144 compatible = "arm,versatile-flash", "cfi-flash";
145 reg = <0x3c000000 0x4000000>;
146 bank-width = <4>;
147 status = "disabled";
148 };
149
150 /* SMSC 9118 ethernet with PHY and EEPROM */
151 ethernet@3a000000 {
152 compatible = "smsc,lan9118", "smsc,lan9115";
153 reg = <0x3a000000 0x10000>;
154 interrupt-parent = <&intc_fpga1176>;
155 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
156 phy-mode = "mii";
157 reg-io-width = <4>;
158 smsc,irq-active-high;
159 smsc,irq-push-pull;
160 vdd33a-supply = <&veth>;
161 vddvario-supply = <&veth>;
162 };
163
164 usb@3b000000 {
165 compatible = "nxp,usb-isp1761";
166 reg = <0x3b000000 0x20000>;
167 interrupt-parent = <&intc_fpga1176>;
168 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
169 port1-otg;
170 };
171
172 bridge {
173 compatible = "ti,ths8134a", "ti,ths8134";
174 #address-cells = <1>;
175 #size-cells = <0>;
176
177 ports {
178 #address-cells = <1>;
179 #size-cells = <0>;
180
181 port@0 {
182 reg = <0>;
183
184 vga_bridge_in: endpoint {
185 remote-endpoint = <&clcd_pads>;
186 };
187 };
188
189 port@1 {
190 reg = <1>;
191
192 vga_bridge_out: endpoint {
193 remote-endpoint = <&vga_con_in>;
194 };
195 };
196 };
197 };
198
199 vga {
200 compatible = "vga-connector";
201
202 port {
203 vga_con_in: endpoint {
204 remote-endpoint = <&vga_bridge_out>;
205 };
206 };
207 };
208
209 soc {
210 #address-cells = <1>;
211 #size-cells = <1>;
212 compatible = "arm,realview-pb1176-soc", "simple-bus";
213 regmap = <&syscon>;
214 ranges;
215
216 syscon: syscon@10000000 {
217 compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd";
218 reg = <0x10000000 0x1000>;
219
220 led@08.0 {
221 compatible = "register-bit-led";
222 offset = <0x08>;
223 mask = <0x01>;
224 label = "versatile:0";
225 linux,default-trigger = "heartbeat";
226 default-state = "on";
227 };
228 led@08.1 {
229 compatible = "register-bit-led";
230 offset = <0x08>;
231 mask = <0x02>;
232 label = "versatile:1";
233 linux,default-trigger = "mmc0";
234 default-state = "off";
235 };
236 led@08.2 {
237 compatible = "register-bit-led";
238 offset = <0x08>;
239 mask = <0x04>;
240 label = "versatile:2";
241 linux,default-trigger = "cpu0";
242 default-state = "off";
243 };
244 led@08.3 {
245 compatible = "register-bit-led";
246 offset = <0x08>;
247 mask = <0x08>;
248 label = "versatile:3";
249 default-state = "off";
250 };
251 led@08.4 {
252 compatible = "register-bit-led";
253 offset = <0x08>;
254 mask = <0x10>;
255 label = "versatile:4";
256 default-state = "off";
257 };
258 led@08.5 {
259 compatible = "register-bit-led";
260 offset = <0x08>;
261 mask = <0x20>;
262 label = "versatile:5";
263 default-state = "off";
264 };
265 led@08.6 {
266 compatible = "register-bit-led";
267 offset = <0x08>;
268 mask = <0x40>;
269 label = "versatile:6";
270 default-state = "off";
271 };
272 led@08.7 {
273 compatible = "register-bit-led";
274 offset = <0x08>;
275 mask = <0x80>;
276 label = "versatile:7";
277 default-state = "off";
278 };
279 oscclk0: osc0@0c {
280 compatible = "arm,syscon-icst307";
281 #clock-cells = <0>;
282 lock-offset = <0x20>;
283 vco-offset = <0x0C>;
284 clocks = <&xtal24mhz>;
285 };
286 oscclk1: osc1@10 {
287 compatible = "arm,syscon-icst307";
288 #clock-cells = <0>;
289 lock-offset = <0x20>;
290 vco-offset = <0x10>;
291 clocks = <&xtal24mhz>;
292 };
293 oscclk2: osc2@14 {
294 compatible = "arm,syscon-icst307";
295 #clock-cells = <0>;
296 lock-offset = <0x20>;
297 vco-offset = <0x14>;
298 clocks = <&xtal24mhz>;
299 };
300 oscclk3: osc3@18 {
301 compatible = "arm,syscon-icst307";
302 #clock-cells = <0>;
303 lock-offset = <0x20>;
304 vco-offset = <0x18>;
305 clocks = <&xtal24mhz>;
306 };
307 oscclk4: osc4@1c {
308 compatible = "arm,syscon-icst307";
309 #clock-cells = <0>;
310 lock-offset = <0x20>;
311 vco-offset = <0x1c>;
312 clocks = <&xtal24mhz>;
313 };
314 };
315
316 /* Primary DevChip GIC synthesized with the CPU */
317 intc_dc1176: interrupt-controller@10120000 {
318 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
319 #interrupt-cells = <3>;
320 #address-cells = <1>;
321 interrupt-controller;
322 reg = <0x10121000 0x1000>,
323 <0x10120000 0x100>;
324 };
325
326 L2: l2-cache {
327 compatible = "arm,l220-cache";
328 reg = <0x10110000 0x1000>;
329 interrupt-parent = <&intc_dc1176>;
330 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
331 cache-unified;
332 cache-level = <2>;
333 /*
334 * Override default cache size, sets and
335 * associativity as these may be erroneously set
336 * up by boot loader(s).
337 */
338 arm,override-auxreg;
339 cache-size = <131072>; // 128kB
340 cache-sets = <512>;
341 cache-line-size = <32>;
342 };
343
344 pmu {
345 compatible = "arm,arm1176-pmu";
346 interrupt-parent = <&intc_dc1176>;
347 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
348 };
349
350 timer01: timer@10104000 {
351 compatible = "arm,sp804", "arm,primecell";
352 reg = <0x10104000 0x1000>;
353 interrupt-parent = <&intc_dc1176>;
354 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&timclk>, <&timclk>, <&pclk>;
356 clock-names = "timer1", "timer2", "apb_pclk";
357 };
358
359 timer23: timer@10105000 {
360 compatible = "arm,sp804", "arm,primecell";
361 reg = <0x10105000 0x1000>;
362 interrupt-parent = <&intc_dc1176>;
363 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
364 arm,sp804-has-irq = <1>;
365 clocks = <&timclk>, <&timclk>, <&pclk>;
366 clock-names = "timer1", "timer2", "apb_pclk";
367 };
368
369 pb1176_rtc: rtc@10108000 {
370 compatible = "arm,pl031", "arm,primecell";
371 reg = <0x10108000 0x1000>;
372 interrupt-parent = <&intc_dc1176>;
373 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&pclk>;
375 clock-names = "apb_pclk";
376 };
377
378 pb1176_gpio0: gpio@1010a000 {
379 compatible = "arm,pl061", "arm,primecell";
380 reg = <0x1010a000 0x1000>;
381 gpio-controller;
382 interrupt-parent = <&intc_dc1176>;
383 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
384 #gpio-cells = <2>;
385 interrupt-controller;
386 #interrupt-cells = <2>;
387 clocks = <&pclk>;
388 clock-names = "apb_pclk";
389 };
390
391 pb1176_ssp: spi@1010b000 {
392 compatible = "arm,pl022", "arm,primecell";
393 reg = <0x1010b000 0x1000>;
394 interrupt-parent = <&intc_dc1176>;
395 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&sspclk>, <&pclk>;
397 clock-names = "SSPCLK", "apb_pclk";
398 };
399
400 pb1176_serial0: serial@1010c000 {
401 compatible = "arm,pl011", "arm,primecell";
402 reg = <0x1010c000 0x1000>;
403 interrupt-parent = <&intc_dc1176>;
404 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&uartclk>, <&pclk>;
406 clock-names = "uartclk", "apb_pclk";
407 };
408
409 pb1176_serial1: serial@1010d000 {
410 compatible = "arm,pl011", "arm,primecell";
411 reg = <0x1010d000 0x1000>;
412 interrupt-parent = <&intc_dc1176>;
413 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&uartclk>, <&pclk>;
415 clock-names = "uartclk", "apb_pclk";
416 };
417
418 pb1176_serial2: serial@1010e000 {
419 compatible = "arm,pl011", "arm,primecell";
420 reg = <0x1010e000 0x1000>;
421 interrupt-parent = <&intc_dc1176>;
422 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&uartclk>, <&pclk>;
424 clock-names = "uartclk", "apb_pclk";
425 };
426
427 pb1176_serial3: serial@1010f000 {
428 compatible = "arm,pl011", "arm,primecell";
429 reg = <0x1010f000 0x1000>;
430 interrupt-parent = <&intc_dc1176>;
431 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&uartclk>, <&pclk>;
433 clock-names = "uartclk", "apb_pclk";
434 };
435
436 /* Direct-mapped development chip ROM */
437 pb1176_rom@10200000 {
438 compatible = "direct-mapped";
439 reg = <0x10200000 0x4000>;
440 bank-width = <1>;
441 };
442
443 clcd@10112000 {
444 compatible = "arm,pl111", "arm,primecell";
445 reg = <0x10112000 0x1000>;
446 interrupt-parent = <&intc_dc1176>;
447 interrupt-names = "combined";
448 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&oscclk0>, <&pclk>;
450 clock-names = "clcdclk", "apb_pclk";
451 /* 1024x768 16bpp @65MHz works fine */
452 max-memory-bandwidth = <95000000>;
453
454 port {
455 clcd_pads: endpoint {
456 remote-endpoint = <&vga_bridge_in>;
457 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
458 };
459 };
460 };
461 };
462
463 /* These peripherals are inside the FPGA rather than the DevChip */
464 fpga {
465 #address-cells = <1>;
466 #size-cells = <1>;
467 compatible = "simple-bus";
468 ranges;
469
470 i2c0: i2c@10002000 {
471 #address-cells = <1>;
472 #size-cells = <0>;
473 compatible = "arm,versatile-i2c";
474 reg = <0x10002000 0x1000>;
475
476 rtc@68 {
477 compatible = "dallas,ds1338";
478 reg = <0x68>;
479 };
480 };
481
482 fpga_aaci: aaci@10004000 {
483 compatible = "arm,pl041", "arm,primecell";
484 reg = <0x10004000 0x1000>;
485 interrupt-parent = <&intc_fpga1176>;
486 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&pclk>;
488 clock-names = "apb_pclk";
489 };
490
491 fpga_mci: mmcsd@10005000 {
492 compatible = "arm,pl18x", "arm,primecell";
493 reg = <0x10005000 0x1000>;
494 interrupt-parent = <&intc_fpga1176>;
495 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
496 <0 2 IRQ_TYPE_LEVEL_HIGH>;
497 /* Due to frequent FIFO overruns, use just 500 kHz */
498 max-frequency = <500000>;
499 bus-width = <4>;
500 cap-sd-highspeed;
501 cap-mmc-highspeed;
502 clocks = <&mclk>, <&pclk>;
503 clock-names = "mclk", "apb_pclk";
504 vmmc-supply = <&vmmc>;
505 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
506 wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
507 };
508
509 fpga_kmi0: kmi@10006000 {
510 compatible = "arm,pl050", "arm,primecell";
511 reg = <0x10006000 0x1000>;
512 interrupt-parent = <&intc_fpga1176>;
513 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&kmiclk>, <&pclk>;
515 clock-names = "KMIREFCLK", "apb_pclk";
516 };
517
518 fpga_kmi1: kmi@10007000 {
519 compatible = "arm,pl050", "arm,primecell";
520 reg = <0x10007000 0x1000>;
521 interrupt-parent = <&intc_fpga1176>;
522 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&kmiclk>, <&pclk>;
524 clock-names = "KMIREFCLK", "apb_pclk";
525 };
526
527 fpga_charlcd: charlcd@10008000 {
528 compatible = "arm,versatile-lcd";
529 reg = <0x10008000 0x1000>;
530 interrupt-parent = <&intc_fpga1176>;
531 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&pclk>;
533 clock-names = "apb_pclk";
534 };
535
536 fpga_serial: serial@10009000 {
537 compatible = "arm,pl011", "arm,primecell";
538 reg = <0x10009000 0x1000>;
539 interrupt-parent = <&intc_fpga1176>;
540 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&uartclk>, <&pclk>;
542 clock-names = "uartclk", "apb_pclk";
543 };
544
545 /* This GIC on the board is cascaded off the DevChip GIC */
546 intc_fpga1176: interrupt-controller@10040000 {
547 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
548 #interrupt-cells = <3>;
549 #address-cells = <1>;
550 interrupt-controller;
551 reg = <0x10041000 0x1000>,
552 <0x10040000 0x100>;
553 interrupt-parent = <&intc_dc1176>;
554 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
555 };
556
557 fpga_gpio0: gpio@10014000 {
558 compatible = "arm,pl061", "arm,primecell";
559 reg = <0x10014000 0x1000>;
560 gpio-controller;
561 interrupt-parent = <&intc_fpga1176>;
562 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
563 #gpio-cells = <2>;
564 interrupt-controller;
565 #interrupt-cells = <2>;
566 clocks = <&pclk>;
567 clock-names = "apb_pclk";
568 };
569
570 fpga_gpio1: gpio@10015000 {
571 compatible = "arm,pl061", "arm,primecell";
572 reg = <0x10015000 0x1000>;
573 gpio-controller;
574 interrupt-parent = <&intc_fpga1176>;
575 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
576 #gpio-cells = <2>;
577 interrupt-controller;
578 #interrupt-cells = <2>;
579 clocks = <&pclk>;
580 clock-names = "apb_pclk";
581 };
582
583 fpga_rtc: rtc@10017000 {
584 compatible = "arm,pl031", "arm,primecell";
585 reg = <0x10017000 0x1000>;
586 interrupt-parent = <&intc_fpga1176>;
587 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&pclk>;
589 clock-names = "apb_pclk";
590 };
591 };
592};