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1/*
2 * Device Tree Source for AM43xx clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10&scm_clocks {
11 sys_clkin_ck: sys_clkin_ck@40 {
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
15 ti,bit-shift = <31>;
16 reg = <0x0040>;
17 };
18
19 crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
20 #clock-cells = <0>;
21 compatible = "ti,mux-clock";
22 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
23 ti,bit-shift = <29>;
24 reg = <0x0040>;
25 };
26
27 sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
28 #clock-cells = <0>;
29 compatible = "ti,mux-clock";
30 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
31 ti,bit-shift = <22>;
32 reg = <0x0040>;
33 };
34
35 adc_tsc_fck: adc_tsc_fck {
36 #clock-cells = <0>;
37 compatible = "fixed-factor-clock";
38 clocks = <&sys_clkin_ck>;
39 clock-mult = <1>;
40 clock-div = <1>;
41 };
42
43 dcan0_fck: dcan0_fck {
44 #clock-cells = <0>;
45 compatible = "fixed-factor-clock";
46 clocks = <&sys_clkin_ck>;
47 clock-mult = <1>;
48 clock-div = <1>;
49 };
50
51 dcan1_fck: dcan1_fck {
52 #clock-cells = <0>;
53 compatible = "fixed-factor-clock";
54 clocks = <&sys_clkin_ck>;
55 clock-mult = <1>;
56 clock-div = <1>;
57 };
58
59 mcasp0_fck: mcasp0_fck {
60 #clock-cells = <0>;
61 compatible = "fixed-factor-clock";
62 clocks = <&sys_clkin_ck>;
63 clock-mult = <1>;
64 clock-div = <1>;
65 };
66
67 mcasp1_fck: mcasp1_fck {
68 #clock-cells = <0>;
69 compatible = "fixed-factor-clock";
70 clocks = <&sys_clkin_ck>;
71 clock-mult = <1>;
72 clock-div = <1>;
73 };
74
75 smartreflex0_fck: smartreflex0_fck {
76 #clock-cells = <0>;
77 compatible = "fixed-factor-clock";
78 clocks = <&sys_clkin_ck>;
79 clock-mult = <1>;
80 clock-div = <1>;
81 };
82
83 smartreflex1_fck: smartreflex1_fck {
84 #clock-cells = <0>;
85 compatible = "fixed-factor-clock";
86 clocks = <&sys_clkin_ck>;
87 clock-mult = <1>;
88 clock-div = <1>;
89 };
90
91 sha0_fck: sha0_fck {
92 #clock-cells = <0>;
93 compatible = "fixed-factor-clock";
94 clocks = <&sys_clkin_ck>;
95 clock-mult = <1>;
96 clock-div = <1>;
97 };
98
99 aes0_fck: aes0_fck {
100 #clock-cells = <0>;
101 compatible = "fixed-factor-clock";
102 clocks = <&sys_clkin_ck>;
103 clock-mult = <1>;
104 clock-div = <1>;
105 };
106
107 rng_fck: rng_fck {
108 #clock-cells = <0>;
109 compatible = "fixed-factor-clock";
110 clocks = <&sys_clkin_ck>;
111 clock-mult = <1>;
112 clock-div = <1>;
113 };
114
115 ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
116 #clock-cells = <0>;
117 compatible = "ti,gate-clock";
118 clocks = <&l4ls_gclk>;
119 ti,bit-shift = <0>;
120 reg = <0x0664>;
121 };
122
123 ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
124 #clock-cells = <0>;
125 compatible = "ti,gate-clock";
126 clocks = <&l4ls_gclk>;
127 ti,bit-shift = <1>;
128 reg = <0x0664>;
129 };
130
131 ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
132 #clock-cells = <0>;
133 compatible = "ti,gate-clock";
134 clocks = <&l4ls_gclk>;
135 ti,bit-shift = <2>;
136 reg = <0x0664>;
137 };
138
139 ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
140 #clock-cells = <0>;
141 compatible = "ti,gate-clock";
142 clocks = <&l4ls_gclk>;
143 ti,bit-shift = <4>;
144 reg = <0x0664>;
145 };
146
147 ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
148 #clock-cells = <0>;
149 compatible = "ti,gate-clock";
150 clocks = <&l4ls_gclk>;
151 ti,bit-shift = <5>;
152 reg = <0x0664>;
153 };
154
155 ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
156 #clock-cells = <0>;
157 compatible = "ti,gate-clock";
158 clocks = <&l4ls_gclk>;
159 ti,bit-shift = <6>;
160 reg = <0x0664>;
161 };
162};
163&prcm_clocks {
164 clk_32768_ck: clk_32768_ck {
165 #clock-cells = <0>;
166 compatible = "fixed-clock";
167 clock-frequency = <32768>;
168 };
169
170 clk_rc32k_ck: clk_rc32k_ck {
171 #clock-cells = <0>;
172 compatible = "fixed-clock";
173 clock-frequency = <32768>;
174 };
175
176 virt_19200000_ck: virt_19200000_ck {
177 #clock-cells = <0>;
178 compatible = "fixed-clock";
179 clock-frequency = <19200000>;
180 };
181
182 virt_24000000_ck: virt_24000000_ck {
183 #clock-cells = <0>;
184 compatible = "fixed-clock";
185 clock-frequency = <24000000>;
186 };
187
188 virt_25000000_ck: virt_25000000_ck {
189 #clock-cells = <0>;
190 compatible = "fixed-clock";
191 clock-frequency = <25000000>;
192 };
193
194 virt_26000000_ck: virt_26000000_ck {
195 #clock-cells = <0>;
196 compatible = "fixed-clock";
197 clock-frequency = <26000000>;
198 };
199
200 tclkin_ck: tclkin_ck {
201 #clock-cells = <0>;
202 compatible = "fixed-clock";
203 clock-frequency = <26000000>;
204 };
205
206 dpll_core_ck: dpll_core_ck@2d20 {
207 #clock-cells = <0>;
208 compatible = "ti,am3-dpll-core-clock";
209 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
210 reg = <0x2d20>, <0x2d24>, <0x2d2c>;
211 };
212
213 dpll_core_x2_ck: dpll_core_x2_ck {
214 #clock-cells = <0>;
215 compatible = "ti,am3-dpll-x2-clock";
216 clocks = <&dpll_core_ck>;
217 };
218
219 dpll_core_m4_ck: dpll_core_m4_ck@2d38 {
220 #clock-cells = <0>;
221 compatible = "ti,divider-clock";
222 clocks = <&dpll_core_x2_ck>;
223 ti,max-div = <31>;
224 ti,autoidle-shift = <8>;
225 reg = <0x2d38>;
226 ti,index-starts-at-one;
227 ti,invert-autoidle-bit;
228 };
229
230 dpll_core_m5_ck: dpll_core_m5_ck@2d3c {
231 #clock-cells = <0>;
232 compatible = "ti,divider-clock";
233 clocks = <&dpll_core_x2_ck>;
234 ti,max-div = <31>;
235 ti,autoidle-shift = <8>;
236 reg = <0x2d3c>;
237 ti,index-starts-at-one;
238 ti,invert-autoidle-bit;
239 };
240
241 dpll_core_m6_ck: dpll_core_m6_ck@2d40 {
242 #clock-cells = <0>;
243 compatible = "ti,divider-clock";
244 clocks = <&dpll_core_x2_ck>;
245 ti,max-div = <31>;
246 ti,autoidle-shift = <8>;
247 reg = <0x2d40>;
248 ti,index-starts-at-one;
249 ti,invert-autoidle-bit;
250 };
251
252 dpll_mpu_ck: dpll_mpu_ck@2d60 {
253 #clock-cells = <0>;
254 compatible = "ti,am3-dpll-clock";
255 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
256 reg = <0x2d60>, <0x2d64>, <0x2d6c>;
257 };
258
259 dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
260 #clock-cells = <0>;
261 compatible = "ti,divider-clock";
262 clocks = <&dpll_mpu_ck>;
263 ti,max-div = <31>;
264 ti,autoidle-shift = <8>;
265 reg = <0x2d70>;
266 ti,index-starts-at-one;
267 ti,invert-autoidle-bit;
268 };
269
270 mpu_periphclk: mpu_periphclk {
271 #clock-cells = <0>;
272 compatible = "fixed-factor-clock";
273 clocks = <&dpll_mpu_m2_ck>;
274 clock-mult = <1>;
275 clock-div = <2>;
276 };
277
278 dpll_ddr_ck: dpll_ddr_ck@2da0 {
279 #clock-cells = <0>;
280 compatible = "ti,am3-dpll-clock";
281 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
282 reg = <0x2da0>, <0x2da4>, <0x2dac>;
283 };
284
285 dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
286 #clock-cells = <0>;
287 compatible = "ti,divider-clock";
288 clocks = <&dpll_ddr_ck>;
289 ti,max-div = <31>;
290 ti,autoidle-shift = <8>;
291 reg = <0x2db0>;
292 ti,index-starts-at-one;
293 ti,invert-autoidle-bit;
294 };
295
296 dpll_disp_ck: dpll_disp_ck@2e20 {
297 #clock-cells = <0>;
298 compatible = "ti,am3-dpll-clock";
299 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
300 reg = <0x2e20>, <0x2e24>, <0x2e2c>;
301 };
302
303 dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
304 #clock-cells = <0>;
305 compatible = "ti,divider-clock";
306 clocks = <&dpll_disp_ck>;
307 ti,max-div = <31>;
308 ti,autoidle-shift = <8>;
309 reg = <0x2e30>;
310 ti,index-starts-at-one;
311 ti,invert-autoidle-bit;
312 ti,set-rate-parent;
313 };
314
315 dpll_per_ck: dpll_per_ck@2de0 {
316 #clock-cells = <0>;
317 compatible = "ti,am3-dpll-j-type-clock";
318 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
319 reg = <0x2de0>, <0x2de4>, <0x2dec>;
320 };
321
322 dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
323 #clock-cells = <0>;
324 compatible = "ti,divider-clock";
325 clocks = <&dpll_per_ck>;
326 ti,max-div = <127>;
327 ti,autoidle-shift = <8>;
328 reg = <0x2df0>;
329 ti,index-starts-at-one;
330 ti,invert-autoidle-bit;
331 };
332
333 dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
334 #clock-cells = <0>;
335 compatible = "fixed-factor-clock";
336 clocks = <&dpll_per_m2_ck>;
337 clock-mult = <1>;
338 clock-div = <4>;
339 };
340
341 dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
342 #clock-cells = <0>;
343 compatible = "fixed-factor-clock";
344 clocks = <&dpll_per_m2_ck>;
345 clock-mult = <1>;
346 clock-div = <4>;
347 };
348
349 clk_24mhz: clk_24mhz {
350 #clock-cells = <0>;
351 compatible = "fixed-factor-clock";
352 clocks = <&dpll_per_m2_ck>;
353 clock-mult = <1>;
354 clock-div = <8>;
355 };
356
357 clkdiv32k_ck: clkdiv32k_ck {
358 #clock-cells = <0>;
359 compatible = "fixed-factor-clock";
360 clocks = <&clk_24mhz>;
361 clock-mult = <1>;
362 clock-div = <732>;
363 };
364
365 clkdiv32k_ick: clkdiv32k_ick@2a38 {
366 #clock-cells = <0>;
367 compatible = "ti,gate-clock";
368 clocks = <&clkdiv32k_ck>;
369 ti,bit-shift = <8>;
370 reg = <0x2a38>;
371 };
372
373 sysclk_div: sysclk_div {
374 #clock-cells = <0>;
375 compatible = "fixed-factor-clock";
376 clocks = <&dpll_core_m4_ck>;
377 clock-mult = <1>;
378 clock-div = <1>;
379 };
380
381 pruss_ocp_gclk: pruss_ocp_gclk@4248 {
382 #clock-cells = <0>;
383 compatible = "ti,mux-clock";
384 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
385 reg = <0x4248>;
386 };
387
388 clk_32k_tpm_ck: clk_32k_tpm_ck {
389 #clock-cells = <0>;
390 compatible = "fixed-clock";
391 clock-frequency = <32768>;
392 };
393
394 timer1_fck: timer1_fck@4200 {
395 #clock-cells = <0>;
396 compatible = "ti,mux-clock";
397 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
398 reg = <0x4200>;
399 };
400
401 timer2_fck: timer2_fck@4204 {
402 #clock-cells = <0>;
403 compatible = "ti,mux-clock";
404 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
405 reg = <0x4204>;
406 };
407
408 timer3_fck: timer3_fck@4208 {
409 #clock-cells = <0>;
410 compatible = "ti,mux-clock";
411 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
412 reg = <0x4208>;
413 };
414
415 timer4_fck: timer4_fck@420c {
416 #clock-cells = <0>;
417 compatible = "ti,mux-clock";
418 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
419 reg = <0x420c>;
420 };
421
422 timer5_fck: timer5_fck@4210 {
423 #clock-cells = <0>;
424 compatible = "ti,mux-clock";
425 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
426 reg = <0x4210>;
427 };
428
429 timer6_fck: timer6_fck@4214 {
430 #clock-cells = <0>;
431 compatible = "ti,mux-clock";
432 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
433 reg = <0x4214>;
434 };
435
436 timer7_fck: timer7_fck@4218 {
437 #clock-cells = <0>;
438 compatible = "ti,mux-clock";
439 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
440 reg = <0x4218>;
441 };
442
443 wdt1_fck: wdt1_fck@422c {
444 #clock-cells = <0>;
445 compatible = "ti,mux-clock";
446 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
447 reg = <0x422c>;
448 };
449
450 l3_gclk: l3_gclk {
451 #clock-cells = <0>;
452 compatible = "fixed-factor-clock";
453 clocks = <&dpll_core_m4_ck>;
454 clock-mult = <1>;
455 clock-div = <1>;
456 };
457
458 dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
459 #clock-cells = <0>;
460 compatible = "fixed-factor-clock";
461 clocks = <&sysclk_div>;
462 clock-mult = <1>;
463 clock-div = <2>;
464 };
465
466 l4hs_gclk: l4hs_gclk {
467 #clock-cells = <0>;
468 compatible = "fixed-factor-clock";
469 clocks = <&dpll_core_m4_ck>;
470 clock-mult = <1>;
471 clock-div = <1>;
472 };
473
474 l3s_gclk: l3s_gclk {
475 #clock-cells = <0>;
476 compatible = "fixed-factor-clock";
477 clocks = <&dpll_core_m4_div2_ck>;
478 clock-mult = <1>;
479 clock-div = <1>;
480 };
481
482 l4ls_gclk: l4ls_gclk {
483 #clock-cells = <0>;
484 compatible = "fixed-factor-clock";
485 clocks = <&dpll_core_m4_div2_ck>;
486 clock-mult = <1>;
487 clock-div = <1>;
488 };
489
490 cpsw_125mhz_gclk: cpsw_125mhz_gclk {
491 #clock-cells = <0>;
492 compatible = "fixed-factor-clock";
493 clocks = <&dpll_core_m5_ck>;
494 clock-mult = <1>;
495 clock-div = <2>;
496 };
497
498 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 {
499 #clock-cells = <0>;
500 compatible = "ti,mux-clock";
501 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
502 reg = <0x4238>;
503 };
504
505 dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 {
506 #clock-cells = <0>;
507 compatible = "ti,divider-clock";
508 clocks = <&dpll_core_m5_ck>;
509 reg = <0x4234>;
510 ti,bit-shift = <2>;
511 ti,dividers = <2>, <5>;
512 };
513
514 clk_32k_mosc_ck: clk_32k_mosc_ck {
515 #clock-cells = <0>;
516 compatible = "fixed-clock";
517 clock-frequency = <32768>;
518 };
519
520 gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
521 #clock-cells = <0>;
522 compatible = "ti,mux-clock";
523 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
524 reg = <0x4240>;
525 };
526
527 mmc_clk: mmc_clk {
528 #clock-cells = <0>;
529 compatible = "fixed-factor-clock";
530 clocks = <&dpll_per_m2_ck>;
531 clock-mult = <1>;
532 clock-div = <2>;
533 };
534
535 gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c {
536 #clock-cells = <0>;
537 compatible = "ti,mux-clock";
538 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
539 ti,bit-shift = <1>;
540 reg = <0x423c>;
541 };
542
543 gfx_fck_div_ck: gfx_fck_div_ck@423c {
544 #clock-cells = <0>;
545 compatible = "ti,divider-clock";
546 clocks = <&gfx_fclk_clksel_ck>;
547 reg = <0x423c>;
548 ti,max-div = <2>;
549 };
550
551 disp_clk: disp_clk@4244 {
552 #clock-cells = <0>;
553 compatible = "ti,mux-clock";
554 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
555 reg = <0x4244>;
556 ti,set-rate-parent;
557 };
558
559 dpll_extdev_ck: dpll_extdev_ck@2e60 {
560 #clock-cells = <0>;
561 compatible = "ti,am3-dpll-clock";
562 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
563 reg = <0x2e60>, <0x2e64>, <0x2e6c>;
564 };
565
566 dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
567 #clock-cells = <0>;
568 compatible = "ti,divider-clock";
569 clocks = <&dpll_extdev_ck>;
570 ti,max-div = <127>;
571 ti,autoidle-shift = <8>;
572 reg = <0x2e70>;
573 ti,index-starts-at-one;
574 ti,invert-autoidle-bit;
575 };
576
577 mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
578 #clock-cells = <0>;
579 compatible = "ti,mux-clock";
580 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
581 reg = <0x4230>;
582 };
583
584 timer8_fck: timer8_fck@421c {
585 #clock-cells = <0>;
586 compatible = "ti,mux-clock";
587 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
588 reg = <0x421c>;
589 };
590
591 timer9_fck: timer9_fck@4220 {
592 #clock-cells = <0>;
593 compatible = "ti,mux-clock";
594 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
595 reg = <0x4220>;
596 };
597
598 timer10_fck: timer10_fck@4224 {
599 #clock-cells = <0>;
600 compatible = "ti,mux-clock";
601 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
602 reg = <0x4224>;
603 };
604
605 timer11_fck: timer11_fck@4228 {
606 #clock-cells = <0>;
607 compatible = "ti,mux-clock";
608 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
609 reg = <0x4228>;
610 };
611
612 cpsw_50m_clkdiv: cpsw_50m_clkdiv {
613 #clock-cells = <0>;
614 compatible = "fixed-factor-clock";
615 clocks = <&dpll_core_m5_ck>;
616 clock-mult = <1>;
617 clock-div = <1>;
618 };
619
620 cpsw_5m_clkdiv: cpsw_5m_clkdiv {
621 #clock-cells = <0>;
622 compatible = "fixed-factor-clock";
623 clocks = <&cpsw_50m_clkdiv>;
624 clock-mult = <1>;
625 clock-div = <10>;
626 };
627
628 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
629 #clock-cells = <0>;
630 compatible = "ti,am3-dpll-x2-clock";
631 clocks = <&dpll_ddr_ck>;
632 };
633
634 dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 {
635 #clock-cells = <0>;
636 compatible = "ti,divider-clock";
637 clocks = <&dpll_ddr_x2_ck>;
638 ti,max-div = <31>;
639 ti,autoidle-shift = <8>;
640 reg = <0x2db8>;
641 ti,index-starts-at-one;
642 ti,invert-autoidle-bit;
643 };
644
645 dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 {
646 #clock-cells = <0>;
647 compatible = "ti,fixed-factor-clock";
648 clocks = <&dpll_per_ck>;
649 ti,clock-mult = <1>;
650 ti,clock-div = <1>;
651 ti,autoidle-shift = <8>;
652 reg = <0x2e14>;
653 ti,invert-autoidle-bit;
654 };
655
656 dll_aging_clk_div: dll_aging_clk_div@4250 {
657 #clock-cells = <0>;
658 compatible = "ti,divider-clock";
659 clocks = <&sys_clkin_ck>;
660 reg = <0x4250>;
661 ti,dividers = <8>, <16>, <32>;
662 };
663
664 div_core_25m_ck: div_core_25m_ck {
665 #clock-cells = <0>;
666 compatible = "fixed-factor-clock";
667 clocks = <&sysclk_div>;
668 clock-mult = <1>;
669 clock-div = <8>;
670 };
671
672 func_12m_clk: func_12m_clk {
673 #clock-cells = <0>;
674 compatible = "fixed-factor-clock";
675 clocks = <&dpll_per_m2_ck>;
676 clock-mult = <1>;
677 clock-div = <16>;
678 };
679
680 vtp_clk_div: vtp_clk_div {
681 #clock-cells = <0>;
682 compatible = "fixed-factor-clock";
683 clocks = <&sys_clkin_ck>;
684 clock-mult = <1>;
685 clock-div = <2>;
686 };
687
688 usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 {
689 #clock-cells = <0>;
690 compatible = "ti,mux-clock";
691 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
692 reg = <0x4260>;
693 };
694
695 usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
696 #clock-cells = <0>;
697 compatible = "ti,gate-clock";
698 clocks = <&usbphy_32khz_clkmux>;
699 ti,bit-shift = <8>;
700 reg = <0x2a40>;
701 };
702
703 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
704 #clock-cells = <0>;
705 compatible = "ti,gate-clock";
706 clocks = <&usbphy_32khz_clkmux>;
707 ti,bit-shift = <8>;
708 reg = <0x2a48>;
709 };
710};
711
712&prcm {
713 l4_wkup_cm: l4_wkup_cm@2800 {
714 compatible = "ti,omap4-cm";
715 reg = <0x2800 0x400>;
716 #address-cells = <1>;
717 #size-cells = <1>;
718 ranges = <0 0x2800 0x400>;
719
720 l4_wkup_clkctrl: clk@20 {
721 compatible = "ti,clkctrl";
722 reg = <0x20 0x34c>;
723 #clock-cells = <2>;
724 };
725 };
726
727 mpu_cm: mpu_cm@8300 {
728 compatible = "ti,omap4-cm";
729 reg = <0x8300 0x100>;
730 #address-cells = <1>;
731 #size-cells = <1>;
732 ranges = <0 0x8300 0x100>;
733
734 mpu_clkctrl: clk@20 {
735 compatible = "ti,clkctrl";
736 reg = <0x20 0x4>;
737 #clock-cells = <2>;
738 };
739 };
740
741 gfx_l3_cm: gfx_l3_cm@8400 {
742 compatible = "ti,omap4-cm";
743 reg = <0x8400 0x100>;
744 #address-cells = <1>;
745 #size-cells = <1>;
746 ranges = <0 0x8400 0x100>;
747
748 gfx_l3_clkctrl: clk@20 {
749 compatible = "ti,clkctrl";
750 reg = <0x20 0x4>;
751 #clock-cells = <2>;
752 };
753 };
754
755 l4_rtc_cm: l4_rtc_cm@8500 {
756 compatible = "ti,omap4-cm";
757 reg = <0x8500 0x100>;
758 #address-cells = <1>;
759 #size-cells = <1>;
760 ranges = <0 0x8500 0x100>;
761
762 l4_rtc_clkctrl: clk@20 {
763 compatible = "ti,clkctrl";
764 reg = <0x20 0x4>;
765 #clock-cells = <2>;
766 };
767 };
768
769 l4_per_cm: l4_per_cm@8800 {
770 compatible = "ti,omap4-cm";
771 reg = <0x8800 0xc00>;
772 #address-cells = <1>;
773 #size-cells = <1>;
774 ranges = <0 0x8800 0xc00>;
775
776 l4_per_clkctrl: clk@20 {
777 compatible = "ti,clkctrl";
778 reg = <0x20 0xb04>;
779 #clock-cells = <2>;
780 };
781 };
782};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for AM43xx clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7&scm_clocks {
8 sys_clkin_ck: sys_clkin_ck@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
12 ti,bit-shift = <31>;
13 reg = <0x0040>;
14 };
15
16 crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
17 #clock-cells = <0>;
18 compatible = "ti,mux-clock";
19 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
20 ti,bit-shift = <29>;
21 reg = <0x0040>;
22 };
23
24 sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
25 #clock-cells = <0>;
26 compatible = "ti,mux-clock";
27 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
28 ti,bit-shift = <22>;
29 reg = <0x0040>;
30 };
31
32 adc_tsc_fck: adc_tsc_fck {
33 #clock-cells = <0>;
34 compatible = "fixed-factor-clock";
35 clocks = <&sys_clkin_ck>;
36 clock-mult = <1>;
37 clock-div = <1>;
38 };
39
40 dcan0_fck: dcan0_fck {
41 #clock-cells = <0>;
42 compatible = "fixed-factor-clock";
43 clocks = <&sys_clkin_ck>;
44 clock-mult = <1>;
45 clock-div = <1>;
46 };
47
48 dcan1_fck: dcan1_fck {
49 #clock-cells = <0>;
50 compatible = "fixed-factor-clock";
51 clocks = <&sys_clkin_ck>;
52 clock-mult = <1>;
53 clock-div = <1>;
54 };
55
56 mcasp0_fck: mcasp0_fck {
57 #clock-cells = <0>;
58 compatible = "fixed-factor-clock";
59 clocks = <&sys_clkin_ck>;
60 clock-mult = <1>;
61 clock-div = <1>;
62 };
63
64 mcasp1_fck: mcasp1_fck {
65 #clock-cells = <0>;
66 compatible = "fixed-factor-clock";
67 clocks = <&sys_clkin_ck>;
68 clock-mult = <1>;
69 clock-div = <1>;
70 };
71
72 smartreflex0_fck: smartreflex0_fck {
73 #clock-cells = <0>;
74 compatible = "fixed-factor-clock";
75 clocks = <&sys_clkin_ck>;
76 clock-mult = <1>;
77 clock-div = <1>;
78 };
79
80 smartreflex1_fck: smartreflex1_fck {
81 #clock-cells = <0>;
82 compatible = "fixed-factor-clock";
83 clocks = <&sys_clkin_ck>;
84 clock-mult = <1>;
85 clock-div = <1>;
86 };
87
88 sha0_fck: sha0_fck {
89 #clock-cells = <0>;
90 compatible = "fixed-factor-clock";
91 clocks = <&sys_clkin_ck>;
92 clock-mult = <1>;
93 clock-div = <1>;
94 };
95
96 aes0_fck: aes0_fck {
97 #clock-cells = <0>;
98 compatible = "fixed-factor-clock";
99 clocks = <&sys_clkin_ck>;
100 clock-mult = <1>;
101 clock-div = <1>;
102 };
103
104 rng_fck: rng_fck {
105 #clock-cells = <0>;
106 compatible = "fixed-factor-clock";
107 clocks = <&sys_clkin_ck>;
108 clock-mult = <1>;
109 clock-div = <1>;
110 };
111
112 ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
113 #clock-cells = <0>;
114 compatible = "ti,gate-clock";
115 clocks = <&l4ls_gclk>;
116 ti,bit-shift = <0>;
117 reg = <0x0664>;
118 };
119
120 ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
121 #clock-cells = <0>;
122 compatible = "ti,gate-clock";
123 clocks = <&l4ls_gclk>;
124 ti,bit-shift = <1>;
125 reg = <0x0664>;
126 };
127
128 ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
129 #clock-cells = <0>;
130 compatible = "ti,gate-clock";
131 clocks = <&l4ls_gclk>;
132 ti,bit-shift = <2>;
133 reg = <0x0664>;
134 };
135
136 ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
137 #clock-cells = <0>;
138 compatible = "ti,gate-clock";
139 clocks = <&l4ls_gclk>;
140 ti,bit-shift = <4>;
141 reg = <0x0664>;
142 };
143
144 ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
145 #clock-cells = <0>;
146 compatible = "ti,gate-clock";
147 clocks = <&l4ls_gclk>;
148 ti,bit-shift = <5>;
149 reg = <0x0664>;
150 };
151
152 ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
153 #clock-cells = <0>;
154 compatible = "ti,gate-clock";
155 clocks = <&l4ls_gclk>;
156 ti,bit-shift = <6>;
157 reg = <0x0664>;
158 };
159};
160&prcm_clocks {
161 clk_32768_ck: clk_32768_ck {
162 #clock-cells = <0>;
163 compatible = "fixed-clock";
164 clock-frequency = <32768>;
165 };
166
167 clk_rc32k_ck: clk_rc32k_ck {
168 #clock-cells = <0>;
169 compatible = "fixed-clock";
170 clock-frequency = <32768>;
171 };
172
173 virt_19200000_ck: virt_19200000_ck {
174 #clock-cells = <0>;
175 compatible = "fixed-clock";
176 clock-frequency = <19200000>;
177 };
178
179 virt_24000000_ck: virt_24000000_ck {
180 #clock-cells = <0>;
181 compatible = "fixed-clock";
182 clock-frequency = <24000000>;
183 };
184
185 virt_25000000_ck: virt_25000000_ck {
186 #clock-cells = <0>;
187 compatible = "fixed-clock";
188 clock-frequency = <25000000>;
189 };
190
191 virt_26000000_ck: virt_26000000_ck {
192 #clock-cells = <0>;
193 compatible = "fixed-clock";
194 clock-frequency = <26000000>;
195 };
196
197 tclkin_ck: tclkin_ck {
198 #clock-cells = <0>;
199 compatible = "fixed-clock";
200 clock-frequency = <26000000>;
201 };
202
203 dpll_core_ck: dpll_core_ck@2d20 {
204 #clock-cells = <0>;
205 compatible = "ti,am3-dpll-core-clock";
206 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
207 reg = <0x2d20>, <0x2d24>, <0x2d2c>;
208 };
209
210 dpll_core_x2_ck: dpll_core_x2_ck {
211 #clock-cells = <0>;
212 compatible = "ti,am3-dpll-x2-clock";
213 clocks = <&dpll_core_ck>;
214 };
215
216 dpll_core_m4_ck: dpll_core_m4_ck@2d38 {
217 #clock-cells = <0>;
218 compatible = "ti,divider-clock";
219 clocks = <&dpll_core_x2_ck>;
220 ti,max-div = <31>;
221 ti,autoidle-shift = <8>;
222 reg = <0x2d38>;
223 ti,index-starts-at-one;
224 ti,invert-autoidle-bit;
225 };
226
227 dpll_core_m5_ck: dpll_core_m5_ck@2d3c {
228 #clock-cells = <0>;
229 compatible = "ti,divider-clock";
230 clocks = <&dpll_core_x2_ck>;
231 ti,max-div = <31>;
232 ti,autoidle-shift = <8>;
233 reg = <0x2d3c>;
234 ti,index-starts-at-one;
235 ti,invert-autoidle-bit;
236 };
237
238 dpll_core_m6_ck: dpll_core_m6_ck@2d40 {
239 #clock-cells = <0>;
240 compatible = "ti,divider-clock";
241 clocks = <&dpll_core_x2_ck>;
242 ti,max-div = <31>;
243 ti,autoidle-shift = <8>;
244 reg = <0x2d40>;
245 ti,index-starts-at-one;
246 ti,invert-autoidle-bit;
247 };
248
249 dpll_mpu_ck: dpll_mpu_ck@2d60 {
250 #clock-cells = <0>;
251 compatible = "ti,am3-dpll-clock";
252 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
253 reg = <0x2d60>, <0x2d64>, <0x2d6c>;
254 };
255
256 dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
257 #clock-cells = <0>;
258 compatible = "ti,divider-clock";
259 clocks = <&dpll_mpu_ck>;
260 ti,max-div = <31>;
261 ti,autoidle-shift = <8>;
262 reg = <0x2d70>;
263 ti,index-starts-at-one;
264 ti,invert-autoidle-bit;
265 };
266
267 mpu_periphclk: mpu_periphclk {
268 #clock-cells = <0>;
269 compatible = "fixed-factor-clock";
270 clocks = <&dpll_mpu_m2_ck>;
271 clock-mult = <1>;
272 clock-div = <2>;
273 };
274
275 dpll_ddr_ck: dpll_ddr_ck@2da0 {
276 #clock-cells = <0>;
277 compatible = "ti,am3-dpll-clock";
278 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
279 reg = <0x2da0>, <0x2da4>, <0x2dac>;
280 };
281
282 dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
283 #clock-cells = <0>;
284 compatible = "ti,divider-clock";
285 clocks = <&dpll_ddr_ck>;
286 ti,max-div = <31>;
287 ti,autoidle-shift = <8>;
288 reg = <0x2db0>;
289 ti,index-starts-at-one;
290 ti,invert-autoidle-bit;
291 };
292
293 dpll_disp_ck: dpll_disp_ck@2e20 {
294 #clock-cells = <0>;
295 compatible = "ti,am3-dpll-clock";
296 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
297 reg = <0x2e20>, <0x2e24>, <0x2e2c>;
298 };
299
300 dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
301 #clock-cells = <0>;
302 compatible = "ti,divider-clock";
303 clocks = <&dpll_disp_ck>;
304 ti,max-div = <31>;
305 ti,autoidle-shift = <8>;
306 reg = <0x2e30>;
307 ti,index-starts-at-one;
308 ti,invert-autoidle-bit;
309 ti,set-rate-parent;
310 };
311
312 dpll_per_ck: dpll_per_ck@2de0 {
313 #clock-cells = <0>;
314 compatible = "ti,am3-dpll-j-type-clock";
315 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
316 reg = <0x2de0>, <0x2de4>, <0x2dec>;
317 };
318
319 dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
320 #clock-cells = <0>;
321 compatible = "ti,divider-clock";
322 clocks = <&dpll_per_ck>;
323 ti,max-div = <127>;
324 ti,autoidle-shift = <8>;
325 reg = <0x2df0>;
326 ti,index-starts-at-one;
327 ti,invert-autoidle-bit;
328 };
329
330 dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
331 #clock-cells = <0>;
332 compatible = "fixed-factor-clock";
333 clocks = <&dpll_per_m2_ck>;
334 clock-mult = <1>;
335 clock-div = <4>;
336 };
337
338 dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
339 #clock-cells = <0>;
340 compatible = "fixed-factor-clock";
341 clocks = <&dpll_per_m2_ck>;
342 clock-mult = <1>;
343 clock-div = <4>;
344 };
345
346 clk_24mhz: clk_24mhz {
347 #clock-cells = <0>;
348 compatible = "fixed-factor-clock";
349 clocks = <&dpll_per_m2_ck>;
350 clock-mult = <1>;
351 clock-div = <8>;
352 };
353
354 clkdiv32k_ck: clkdiv32k_ck {
355 #clock-cells = <0>;
356 compatible = "fixed-factor-clock";
357 clocks = <&clk_24mhz>;
358 clock-mult = <1>;
359 clock-div = <732>;
360 };
361
362 clkdiv32k_ick: clkdiv32k_ick@2a38 {
363 #clock-cells = <0>;
364 compatible = "ti,gate-clock";
365 clocks = <&clkdiv32k_ck>;
366 ti,bit-shift = <8>;
367 reg = <0x2a38>;
368 };
369
370 sysclk_div: sysclk_div {
371 #clock-cells = <0>;
372 compatible = "fixed-factor-clock";
373 clocks = <&dpll_core_m4_ck>;
374 clock-mult = <1>;
375 clock-div = <1>;
376 };
377
378 pruss_ocp_gclk: pruss_ocp_gclk@4248 {
379 #clock-cells = <0>;
380 compatible = "ti,mux-clock";
381 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
382 reg = <0x4248>;
383 };
384
385 clk_32k_tpm_ck: clk_32k_tpm_ck {
386 #clock-cells = <0>;
387 compatible = "fixed-clock";
388 clock-frequency = <32768>;
389 };
390
391 timer1_fck: timer1_fck@4200 {
392 #clock-cells = <0>;
393 compatible = "ti,mux-clock";
394 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
395 reg = <0x4200>;
396 };
397
398 timer2_fck: timer2_fck@4204 {
399 #clock-cells = <0>;
400 compatible = "ti,mux-clock";
401 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
402 reg = <0x4204>;
403 };
404
405 timer3_fck: timer3_fck@4208 {
406 #clock-cells = <0>;
407 compatible = "ti,mux-clock";
408 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
409 reg = <0x4208>;
410 };
411
412 timer4_fck: timer4_fck@420c {
413 #clock-cells = <0>;
414 compatible = "ti,mux-clock";
415 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
416 reg = <0x420c>;
417 };
418
419 timer5_fck: timer5_fck@4210 {
420 #clock-cells = <0>;
421 compatible = "ti,mux-clock";
422 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
423 reg = <0x4210>;
424 };
425
426 timer6_fck: timer6_fck@4214 {
427 #clock-cells = <0>;
428 compatible = "ti,mux-clock";
429 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
430 reg = <0x4214>;
431 };
432
433 timer7_fck: timer7_fck@4218 {
434 #clock-cells = <0>;
435 compatible = "ti,mux-clock";
436 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
437 reg = <0x4218>;
438 };
439
440 wdt1_fck: wdt1_fck@422c {
441 #clock-cells = <0>;
442 compatible = "ti,mux-clock";
443 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
444 reg = <0x422c>;
445 };
446
447 l3_gclk: l3_gclk {
448 #clock-cells = <0>;
449 compatible = "fixed-factor-clock";
450 clocks = <&dpll_core_m4_ck>;
451 clock-mult = <1>;
452 clock-div = <1>;
453 };
454
455 dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
456 #clock-cells = <0>;
457 compatible = "fixed-factor-clock";
458 clocks = <&sysclk_div>;
459 clock-mult = <1>;
460 clock-div = <2>;
461 };
462
463 l4hs_gclk: l4hs_gclk {
464 #clock-cells = <0>;
465 compatible = "fixed-factor-clock";
466 clocks = <&dpll_core_m4_ck>;
467 clock-mult = <1>;
468 clock-div = <1>;
469 };
470
471 l3s_gclk: l3s_gclk {
472 #clock-cells = <0>;
473 compatible = "fixed-factor-clock";
474 clocks = <&dpll_core_m4_div2_ck>;
475 clock-mult = <1>;
476 clock-div = <1>;
477 };
478
479 l4ls_gclk: l4ls_gclk {
480 #clock-cells = <0>;
481 compatible = "fixed-factor-clock";
482 clocks = <&dpll_core_m4_div2_ck>;
483 clock-mult = <1>;
484 clock-div = <1>;
485 };
486
487 cpsw_125mhz_gclk: cpsw_125mhz_gclk {
488 #clock-cells = <0>;
489 compatible = "fixed-factor-clock";
490 clocks = <&dpll_core_m5_ck>;
491 clock-mult = <1>;
492 clock-div = <2>;
493 };
494
495 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 {
496 #clock-cells = <0>;
497 compatible = "ti,mux-clock";
498 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
499 reg = <0x4238>;
500 };
501
502 dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 {
503 #clock-cells = <0>;
504 compatible = "ti,divider-clock";
505 clocks = <&dpll_core_m5_ck>;
506 reg = <0x4234>;
507 ti,bit-shift = <2>;
508 ti,dividers = <2>, <5>;
509 };
510
511 clk_32k_mosc_ck: clk_32k_mosc_ck {
512 #clock-cells = <0>;
513 compatible = "fixed-clock";
514 clock-frequency = <32768>;
515 };
516
517 gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
518 #clock-cells = <0>;
519 compatible = "ti,mux-clock";
520 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
521 reg = <0x4240>;
522 };
523
524 mmc_clk: mmc_clk {
525 #clock-cells = <0>;
526 compatible = "fixed-factor-clock";
527 clocks = <&dpll_per_m2_ck>;
528 clock-mult = <1>;
529 clock-div = <2>;
530 };
531
532 gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c {
533 #clock-cells = <0>;
534 compatible = "ti,mux-clock";
535 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
536 ti,bit-shift = <1>;
537 reg = <0x423c>;
538 };
539
540 gfx_fck_div_ck: gfx_fck_div_ck@423c {
541 #clock-cells = <0>;
542 compatible = "ti,divider-clock";
543 clocks = <&gfx_fclk_clksel_ck>;
544 reg = <0x423c>;
545 ti,max-div = <2>;
546 };
547
548 disp_clk: disp_clk@4244 {
549 #clock-cells = <0>;
550 compatible = "ti,mux-clock";
551 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
552 reg = <0x4244>;
553 ti,set-rate-parent;
554 };
555
556 dpll_extdev_ck: dpll_extdev_ck@2e60 {
557 #clock-cells = <0>;
558 compatible = "ti,am3-dpll-clock";
559 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
560 reg = <0x2e60>, <0x2e64>, <0x2e6c>;
561 };
562
563 dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
564 #clock-cells = <0>;
565 compatible = "ti,divider-clock";
566 clocks = <&dpll_extdev_ck>;
567 ti,max-div = <127>;
568 ti,autoidle-shift = <8>;
569 reg = <0x2e70>;
570 ti,index-starts-at-one;
571 ti,invert-autoidle-bit;
572 };
573
574 mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
575 #clock-cells = <0>;
576 compatible = "ti,mux-clock";
577 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
578 reg = <0x4230>;
579 };
580
581 timer8_fck: timer8_fck@421c {
582 #clock-cells = <0>;
583 compatible = "ti,mux-clock";
584 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
585 reg = <0x421c>;
586 };
587
588 timer9_fck: timer9_fck@4220 {
589 #clock-cells = <0>;
590 compatible = "ti,mux-clock";
591 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
592 reg = <0x4220>;
593 };
594
595 timer10_fck: timer10_fck@4224 {
596 #clock-cells = <0>;
597 compatible = "ti,mux-clock";
598 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
599 reg = <0x4224>;
600 };
601
602 timer11_fck: timer11_fck@4228 {
603 #clock-cells = <0>;
604 compatible = "ti,mux-clock";
605 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
606 reg = <0x4228>;
607 };
608
609 cpsw_50m_clkdiv: cpsw_50m_clkdiv {
610 #clock-cells = <0>;
611 compatible = "fixed-factor-clock";
612 clocks = <&dpll_core_m5_ck>;
613 clock-mult = <1>;
614 clock-div = <1>;
615 };
616
617 cpsw_5m_clkdiv: cpsw_5m_clkdiv {
618 #clock-cells = <0>;
619 compatible = "fixed-factor-clock";
620 clocks = <&cpsw_50m_clkdiv>;
621 clock-mult = <1>;
622 clock-div = <10>;
623 };
624
625 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
626 #clock-cells = <0>;
627 compatible = "ti,am3-dpll-x2-clock";
628 clocks = <&dpll_ddr_ck>;
629 };
630
631 dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 {
632 #clock-cells = <0>;
633 compatible = "ti,divider-clock";
634 clocks = <&dpll_ddr_x2_ck>;
635 ti,max-div = <31>;
636 ti,autoidle-shift = <8>;
637 reg = <0x2db8>;
638 ti,index-starts-at-one;
639 ti,invert-autoidle-bit;
640 };
641
642 dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 {
643 #clock-cells = <0>;
644 compatible = "ti,fixed-factor-clock";
645 clocks = <&dpll_per_ck>;
646 ti,clock-mult = <1>;
647 ti,clock-div = <1>;
648 ti,autoidle-shift = <8>;
649 reg = <0x2e14>;
650 ti,invert-autoidle-bit;
651 };
652
653 dll_aging_clk_div: dll_aging_clk_div@4250 {
654 #clock-cells = <0>;
655 compatible = "ti,divider-clock";
656 clocks = <&sys_clkin_ck>;
657 reg = <0x4250>;
658 ti,dividers = <8>, <16>, <32>;
659 };
660
661 div_core_25m_ck: div_core_25m_ck {
662 #clock-cells = <0>;
663 compatible = "fixed-factor-clock";
664 clocks = <&sysclk_div>;
665 clock-mult = <1>;
666 clock-div = <8>;
667 };
668
669 func_12m_clk: func_12m_clk {
670 #clock-cells = <0>;
671 compatible = "fixed-factor-clock";
672 clocks = <&dpll_per_m2_ck>;
673 clock-mult = <1>;
674 clock-div = <16>;
675 };
676
677 vtp_clk_div: vtp_clk_div {
678 #clock-cells = <0>;
679 compatible = "fixed-factor-clock";
680 clocks = <&sys_clkin_ck>;
681 clock-mult = <1>;
682 clock-div = <2>;
683 };
684
685 usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 {
686 #clock-cells = <0>;
687 compatible = "ti,mux-clock";
688 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
689 reg = <0x4260>;
690 };
691
692 usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
693 #clock-cells = <0>;
694 compatible = "ti,gate-clock";
695 clocks = <&usbphy_32khz_clkmux>;
696 ti,bit-shift = <8>;
697 reg = <0x2a40>;
698 };
699
700 usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
701 #clock-cells = <0>;
702 compatible = "ti,gate-clock";
703 clocks = <&usbphy_32khz_clkmux>;
704 ti,bit-shift = <8>;
705 reg = <0x2a48>;
706 };
707};
708
709&prcm {
710 wkup_cm: wkup-cm@2800 {
711 compatible = "ti,omap4-cm";
712 reg = <0x2800 0x400>;
713 #address-cells = <1>;
714 #size-cells = <1>;
715 ranges = <0 0x2800 0x400>;
716
717 l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 {
718 compatible = "ti,clkctrl";
719 reg = <0x120 0x4>;
720 #clock-cells = <2>;
721 };
722
723 l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 {
724 compatible = "ti,clkctrl";
725 reg = <0x228 0xc>;
726 #clock-cells = <2>;
727 };
728
729 l4_wkup_clkctrl: l4-wkup-clkctrl@220 {
730 compatible = "ti,clkctrl";
731 reg = <0x220 0x4>, <0x328 0x44>;
732 #clock-cells = <2>;
733 };
734
735 };
736
737 mpu_cm: mpu-cm@8300 {
738 compatible = "ti,omap4-cm";
739 reg = <0x8300 0x100>;
740 #address-cells = <1>;
741 #size-cells = <1>;
742 ranges = <0 0x8300 0x100>;
743
744 mpu_clkctrl: mpu-clkctrl@20 {
745 compatible = "ti,clkctrl";
746 reg = <0x20 0x4>;
747 #clock-cells = <2>;
748 };
749 };
750
751 gfx_l3_cm: gfx-l3-cm@8400 {
752 compatible = "ti,omap4-cm";
753 reg = <0x8400 0x100>;
754 #address-cells = <1>;
755 #size-cells = <1>;
756 ranges = <0 0x8400 0x100>;
757
758 gfx_l3_clkctrl: gfx-l3-clkctrl@20 {
759 compatible = "ti,clkctrl";
760 reg = <0x20 0x4>;
761 #clock-cells = <2>;
762 };
763 };
764
765 l4_rtc_cm: l4-rtc-cm@8500 {
766 compatible = "ti,omap4-cm";
767 reg = <0x8500 0x100>;
768 #address-cells = <1>;
769 #size-cells = <1>;
770 ranges = <0 0x8500 0x100>;
771
772 l4_rtc_clkctrl: l4-rtc-clkctrl@20 {
773 compatible = "ti,clkctrl";
774 reg = <0x20 0x4>;
775 #clock-cells = <2>;
776 };
777 };
778
779 per_cm: per-cm@8800 {
780 compatible = "ti,omap4-cm";
781 reg = <0x8800 0xc00>;
782 #address-cells = <1>;
783 #size-cells = <1>;
784 ranges = <0 0x8800 0xc00>;
785
786 l3_clkctrl: l3-clkctrl@20 {
787 compatible = "ti,clkctrl";
788 reg = <0x20 0x3c>, <0x78 0x2c>;
789 #clock-cells = <2>;
790 };
791
792 l3s_clkctrl: l3s-clkctrl@68 {
793 compatible = "ti,clkctrl";
794 reg = <0x68 0xc>, <0x220 0x4c>;
795 #clock-cells = <2>;
796 };
797
798 pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 {
799 compatible = "ti,clkctrl";
800 reg = <0x320 0x4>;
801 #clock-cells = <2>;
802 };
803
804 l4ls_clkctrl: l4ls-clkctrl@420 {
805 compatible = "ti,clkctrl";
806 reg = <0x420 0x1a4>;
807 #clock-cells = <2>;
808 };
809
810 emif_clkctrl: emif-clkctrl@720 {
811 compatible = "ti,clkctrl";
812 reg = <0x720 0x4>;
813 #clock-cells = <2>;
814 };
815
816 dss_clkctrl: dss-clkctrl@a20 {
817 compatible = "ti,clkctrl";
818 reg = <0xa20 0x4>;
819 #clock-cells = <2>;
820 };
821
822 cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 {
823 compatible = "ti,clkctrl";
824 reg = <0xb20 0x4>;
825 #clock-cells = <2>;
826 };
827
828 };
829};