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1/*
2 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Device Tree for ARC HS Development Kit
11 */
12/dts-v1/;
13
14#include <dt-bindings/net/ti-dp83867.h>
15#include <dt-bindings/reset/snps,hsdk-reset.h>
16
17/ {
18 model = "snps,hsdk";
19 compatible = "snps,hsdk";
20
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 chosen {
25 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 device_type = "cpu";
34 compatible = "snps,archs38";
35 reg = <0>;
36 clocks = <&core_clk>;
37 };
38
39 cpu@1 {
40 device_type = "cpu";
41 compatible = "snps,archs38";
42 reg = <1>;
43 clocks = <&core_clk>;
44 };
45
46 cpu@2 {
47 device_type = "cpu";
48 compatible = "snps,archs38";
49 reg = <2>;
50 clocks = <&core_clk>;
51 };
52
53 cpu@3 {
54 device_type = "cpu";
55 compatible = "snps,archs38";
56 reg = <3>;
57 clocks = <&core_clk>;
58 };
59 };
60
61 input_clk: input-clk {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 clock-frequency = <33333333>;
65 };
66
67 cpu_intc: cpu-interrupt-controller {
68 compatible = "snps,archs-intc";
69 interrupt-controller;
70 #interrupt-cells = <1>;
71 };
72
73 idu_intc: idu-interrupt-controller {
74 compatible = "snps,archs-idu-intc";
75 interrupt-controller;
76 #interrupt-cells = <1>;
77 interrupt-parent = <&cpu_intc>;
78 };
79
80 arcpct: pct {
81 compatible = "snps,archs-pct";
82 };
83
84 /* TIMER0 with interrupt for clockevent */
85 timer {
86 compatible = "snps,arc-timer";
87 interrupts = <16>;
88 interrupt-parent = <&cpu_intc>;
89 clocks = <&core_clk>;
90 };
91
92 /* 64-bit Global Free Running Counter */
93 gfrc {
94 compatible = "snps,archs-timer-gfrc";
95 clocks = <&core_clk>;
96 };
97
98 soc {
99 compatible = "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 interrupt-parent = <&idu_intc>;
103
104 ranges = <0x00000000 0xf0000000 0x10000000>;
105
106 cgu_rst: reset-controller@8a0 {
107 compatible = "snps,hsdk-reset";
108 #reset-cells = <1>;
109 reg = <0x8A0 0x4>, <0xFF0 0x4>;
110 };
111
112 core_clk: core-clk@0 {
113 compatible = "snps,hsdk-core-pll-clock";
114 reg = <0x00 0x10>, <0x14B8 0x4>;
115 #clock-cells = <0>;
116 clocks = <&input_clk>;
117
118 /*
119 * Set initial core pll output frequency to 1GHz.
120 * It will be applied at the core pll driver probing
121 * on early boot.
122 */
123 assigned-clocks = <&core_clk>;
124 assigned-clock-rates = <1000000000>;
125 };
126
127 serial: serial@5000 {
128 compatible = "snps,dw-apb-uart";
129 reg = <0x5000 0x100>;
130 clock-frequency = <33330000>;
131 interrupts = <6>;
132 baud = <115200>;
133 reg-shift = <2>;
134 reg-io-width = <4>;
135 };
136
137 gmacclk: gmacclk {
138 compatible = "fixed-clock";
139 clock-frequency = <400000000>;
140 #clock-cells = <0>;
141 };
142
143 mmcclk_ciu: mmcclk-ciu {
144 compatible = "fixed-clock";
145 /*
146 * DW sdio controller has external ciu clock divider
147 * controlled via register in SDIO IP. Due to its
148 * unexpected default value (it should divide by 1
149 * but it divides by 8) SDIO IP uses wrong clock and
150 * works unstable (see STAR 9001204800)
151 * We switched to the minimum possible value of the
152 * divisor (div-by-2) in HSDK platform code.
153 * So add temporary fix and change clock frequency
154 * to 50000000 Hz until we fix dw sdio driver itself.
155 */
156 clock-frequency = <50000000>;
157 #clock-cells = <0>;
158 };
159
160 mmcclk_biu: mmcclk-biu {
161 compatible = "fixed-clock";
162 clock-frequency = <400000000>;
163 #clock-cells = <0>;
164 };
165
166 ethernet@8000 {
167 #interrupt-cells = <1>;
168 compatible = "snps,dwmac";
169 reg = <0x8000 0x2000>;
170 interrupts = <10>;
171 interrupt-names = "macirq";
172 phy-mode = "rgmii";
173 snps,pbl = <32>;
174 clocks = <&gmacclk>;
175 clock-names = "stmmaceth";
176 phy-handle = <&phy0>;
177 resets = <&cgu_rst HSDK_ETH_RESET>;
178 reset-names = "stmmaceth";
179
180 mdio {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "snps,dwmac-mdio";
184 phy0: ethernet-phy@0 {
185 reg = <0>;
186 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
187 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
188 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
189 };
190 };
191 };
192
193 ohci@60000 {
194 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
195 reg = <0x60000 0x100>;
196 interrupts = <15>;
197 };
198
199 ehci@40000 {
200 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
201 reg = <0x40000 0x100>;
202 interrupts = <15>;
203 };
204
205 mmc@a000 {
206 compatible = "altr,socfpga-dw-mshc";
207 reg = <0xa000 0x400>;
208 num-slots = <1>;
209 fifo-depth = <16>;
210 card-detect-delay = <200>;
211 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
212 clock-names = "biu", "ciu";
213 interrupts = <12>;
214 bus-width = <4>;
215 };
216 };
217
218 memory@80000000 {
219 #address-cells = <1>;
220 #size-cells = <1>;
221 device_type = "memory";
222 reg = <0x80000000 0x40000000>; /* 1 GiB */
223 };
224};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
4 */
5
6/*
7 * Device Tree for ARC HS Development Kit
8 */
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/reset/snps,hsdk-reset.h>
13
14/ {
15 model = "snps,hsdk";
16 compatible = "snps,hsdk";
17
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen {
22 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
23 };
24
25 aliases {
26 ethernet = &gmac;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "snps,archs38";
36 reg = <0>;
37 clocks = <&core_clk>;
38 };
39
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "snps,archs38";
43 reg = <1>;
44 clocks = <&core_clk>;
45 };
46
47 cpu@2 {
48 device_type = "cpu";
49 compatible = "snps,archs38";
50 reg = <2>;
51 clocks = <&core_clk>;
52 };
53
54 cpu@3 {
55 device_type = "cpu";
56 compatible = "snps,archs38";
57 reg = <3>;
58 clocks = <&core_clk>;
59 };
60 };
61
62 input_clk: input-clk {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <33333333>;
66 };
67
68 reg_5v0: regulator-5v0 {
69 compatible = "regulator-fixed";
70
71 regulator-name = "5v0-supply";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
74 };
75
76 cpu_intc: cpu-interrupt-controller {
77 compatible = "snps,archs-intc";
78 interrupt-controller;
79 #interrupt-cells = <1>;
80 };
81
82 idu_intc: idu-interrupt-controller {
83 compatible = "snps,archs-idu-intc";
84 interrupt-controller;
85 #interrupt-cells = <1>;
86 interrupt-parent = <&cpu_intc>;
87 };
88
89 arcpct: pct {
90 compatible = "snps,archs-pct";
91 };
92
93 /* TIMER0 with interrupt for clockevent */
94 timer {
95 compatible = "snps,arc-timer";
96 interrupts = <16>;
97 interrupt-parent = <&cpu_intc>;
98 clocks = <&core_clk>;
99 };
100
101 /* 64-bit Global Free Running Counter */
102 gfrc {
103 compatible = "snps,archs-timer-gfrc";
104 clocks = <&core_clk>;
105 };
106
107 soc {
108 compatible = "simple-bus";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 interrupt-parent = <&idu_intc>;
112
113 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
114
115 cgu_rst: reset-controller@8a0 {
116 compatible = "snps,hsdk-reset";
117 #reset-cells = <1>;
118 reg = <0x8a0 0x4>, <0xff0 0x4>;
119 };
120
121 core_clk: core-clk@0 {
122 compatible = "snps,hsdk-core-pll-clock";
123 reg = <0x00 0x10>, <0x14b8 0x4>;
124 #clock-cells = <0>;
125 clocks = <&input_clk>;
126
127 /*
128 * Set initial core pll output frequency to 1GHz.
129 * It will be applied at the core pll driver probing
130 * on early boot.
131 */
132 assigned-clocks = <&core_clk>;
133 assigned-clock-rates = <1000000000>;
134 };
135
136 serial: serial@5000 {
137 compatible = "snps,dw-apb-uart";
138 reg = <0x5000 0x100>;
139 clock-frequency = <33330000>;
140 interrupts = <6>;
141 baud = <115200>;
142 reg-shift = <2>;
143 reg-io-width = <4>;
144 };
145
146 gmacclk: gmacclk {
147 compatible = "fixed-clock";
148 clock-frequency = <400000000>;
149 #clock-cells = <0>;
150 };
151
152 mmcclk_ciu: mmcclk-ciu {
153 compatible = "fixed-clock";
154 /*
155 * DW sdio controller has external ciu clock divider
156 * controlled via register in SDIO IP. Due to its
157 * unexpected default value (it should divide by 1
158 * but it divides by 8) SDIO IP uses wrong clock and
159 * works unstable (see STAR 9001204800)
160 * We switched to the minimum possible value of the
161 * divisor (div-by-2) in HSDK platform code.
162 * So add temporary fix and change clock frequency
163 * to 50000000 Hz until we fix dw sdio driver itself.
164 */
165 clock-frequency = <50000000>;
166 #clock-cells = <0>;
167 };
168
169 mmcclk_biu: mmcclk-biu {
170 compatible = "fixed-clock";
171 clock-frequency = <400000000>;
172 #clock-cells = <0>;
173 };
174
175 gpu_core_clk: gpu-core-clk {
176 compatible = "fixed-clock";
177 clock-frequency = <400000000>;
178 #clock-cells = <0>;
179 };
180
181 gpu_dma_clk: gpu-dma-clk {
182 compatible = "fixed-clock";
183 clock-frequency = <400000000>;
184 #clock-cells = <0>;
185 };
186
187 gpu_cfg_clk: gpu-cfg-clk {
188 compatible = "fixed-clock";
189 clock-frequency = <200000000>;
190 #clock-cells = <0>;
191 };
192
193 dmac_core_clk: dmac-core-clk {
194 compatible = "fixed-clock";
195 clock-frequency = <400000000>;
196 #clock-cells = <0>;
197 };
198
199 dmac_cfg_clk: dmac-gpu-cfg-clk {
200 compatible = "fixed-clock";
201 clock-frequency = <200000000>;
202 #clock-cells = <0>;
203 };
204
205 gmac: ethernet@8000 {
206 #interrupt-cells = <1>;
207 compatible = "snps,dwmac";
208 reg = <0x8000 0x2000>;
209 interrupts = <10>;
210 interrupt-names = "macirq";
211 phy-mode = "rgmii";
212 snps,pbl = <32>;
213 snps,multicast-filter-bins = <256>;
214 clocks = <&gmacclk>;
215 clock-names = "stmmaceth";
216 phy-handle = <&phy0>;
217 resets = <&cgu_rst HSDK_ETH_RESET>;
218 reset-names = "stmmaceth";
219 mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
220 dma-coherent;
221
222 tx-fifo-depth = <4096>;
223 rx-fifo-depth = <4096>;
224
225 mdio {
226 #address-cells = <1>;
227 #size-cells = <0>;
228 compatible = "snps,dwmac-mdio";
229 phy0: ethernet-phy@0 {
230 reg = <0>;
231 };
232 };
233 };
234
235 ohci@60000 {
236 compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
237 reg = <0x60000 0x100>;
238 interrupts = <15>;
239 resets = <&cgu_rst HSDK_USB_RESET>;
240 dma-coherent;
241 };
242
243 ehci@40000 {
244 compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
245 reg = <0x40000 0x100>;
246 interrupts = <15>;
247 resets = <&cgu_rst HSDK_USB_RESET>;
248 dma-coherent;
249 };
250
251 mmc@a000 {
252 compatible = "altr,socfpga-dw-mshc";
253 reg = <0xa000 0x400>;
254 num-slots = <1>;
255 fifo-depth = <16>;
256 card-detect-delay = <200>;
257 clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
258 clock-names = "biu", "ciu";
259 interrupts = <12>;
260 bus-width = <4>;
261 dma-coherent;
262 };
263
264 spi0: spi@20000 {
265 compatible = "snps,dw-apb-ssi";
266 reg = <0x20000 0x100>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 interrupts = <16>;
270 num-cs = <2>;
271 reg-io-width = <4>;
272 clocks = <&input_clk>;
273 cs-gpios = <&creg_gpio 0 GPIO_ACTIVE_LOW>,
274 <&creg_gpio 1 GPIO_ACTIVE_LOW>;
275
276 spi-flash@0 {
277 compatible = "sst26wf016b", "jedec,spi-nor";
278 reg = <0>;
279 #address-cells = <1>;
280 #size-cells = <1>;
281 spi-max-frequency = <4000000>;
282 };
283
284 adc@1 {
285 compatible = "ti,adc108s102";
286 reg = <1>;
287 vref-supply = <®_5v0>;
288 spi-max-frequency = <1000000>;
289 };
290 };
291
292 creg_gpio: gpio@14b0 {
293 compatible = "snps,creg-gpio-hsdk";
294 reg = <0x14b0 0x4>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 ngpios = <2>;
298 };
299
300 gpio: gpio@3000 {
301 compatible = "snps,dw-apb-gpio";
302 reg = <0x3000 0x20>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305
306 gpio_port_a: gpio-controller@0 {
307 compatible = "snps,dw-apb-gpio-port";
308 gpio-controller;
309 #gpio-cells = <2>;
310 snps,nr-gpios = <24>;
311 reg = <0>;
312 };
313 };
314
315 gpu_3d: gpu@90000 {
316 compatible = "vivante,gc";
317 reg = <0x90000 0x4000>;
318 clocks = <&gpu_dma_clk>,
319 <&gpu_cfg_clk>,
320 <&gpu_core_clk>,
321 <&gpu_core_clk>;
322 clock-names = "bus", "reg", "core", "shader";
323 interrupts = <28>;
324 };
325
326 dmac: dmac@80000 {
327 compatible = "snps,axi-dma-1.01a";
328 reg = <0x80000 0x400>;
329 interrupts = <27>;
330 clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
331 clock-names = "core-clk", "cfgr-clk";
332
333 dma-channels = <4>;
334 snps,dma-masters = <2>;
335 snps,data-width = <3>;
336 snps,block-size = <4096 4096 4096 4096>;
337 snps,priority = <0 1 2 3>;
338 snps,axi-max-burst-len = <16>;
339 };
340 };
341
342 memory@80000000 {
343 #address-cells = <2>;
344 #size-cells = <2>;
345 device_type = "memory";
346 reg = <0x0 0x80000000 0x0 0x40000000>; /* 1 GB lowmem */
347 /* 0x1 0x00000000 0x0 0x40000000>; 1 GB highmem */
348 };
349};