Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4/* Machine-generated file */
5
6#ifndef _ICE_HW_AUTOGEN_H_
7#define _ICE_HW_AUTOGEN_H_
8
9#define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))
10#define PF_FW_ARQBAH 0x00080180
11#define PF_FW_ARQBAL 0x00080080
12#define PF_FW_ARQH 0x00080380
13#define PF_FW_ARQH_ARQH_S 0
14#define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, PF_FW_ARQH_ARQH_S)
15#define PF_FW_ARQLEN 0x00080280
16#define PF_FW_ARQLEN_ARQLEN_S 0
17#define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, PF_FW_ARQLEN_ARQLEN_S)
18#define PF_FW_ARQLEN_ARQVFE_S 28
19#define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S)
20#define PF_FW_ARQLEN_ARQOVFL_S 29
21#define PF_FW_ARQLEN_ARQOVFL_M BIT(PF_FW_ARQLEN_ARQOVFL_S)
22#define PF_FW_ARQLEN_ARQCRIT_S 30
23#define PF_FW_ARQLEN_ARQCRIT_M BIT(PF_FW_ARQLEN_ARQCRIT_S)
24#define PF_FW_ARQLEN_ARQENABLE_S 31
25#define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S)
26#define PF_FW_ARQT 0x00080480
27#define PF_FW_ATQBAH 0x00080100
28#define PF_FW_ATQBAL 0x00080000
29#define PF_FW_ATQH 0x00080300
30#define PF_FW_ATQH_ATQH_S 0
31#define PF_FW_ATQH_ATQH_M ICE_M(0x3FF, PF_FW_ATQH_ATQH_S)
32#define PF_FW_ATQLEN 0x00080200
33#define PF_FW_ATQLEN_ATQLEN_S 0
34#define PF_FW_ATQLEN_ATQLEN_M ICE_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S)
35#define PF_FW_ATQLEN_ATQVFE_S 28
36#define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S)
37#define PF_FW_ATQLEN_ATQOVFL_S 29
38#define PF_FW_ATQLEN_ATQOVFL_M BIT(PF_FW_ATQLEN_ATQOVFL_S)
39#define PF_FW_ATQLEN_ATQCRIT_S 30
40#define PF_FW_ATQLEN_ATQCRIT_M BIT(PF_FW_ATQLEN_ATQCRIT_S)
41#define PF_FW_ATQLEN_ATQENABLE_S 31
42#define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S)
43#define PF_FW_ATQT 0x00080400
44
45#define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256))
46#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S 0
47#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M ICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
48#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S 8
49#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M ICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S)
50#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S 16
51#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M ICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S)
52#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S 24
53#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M ICE_M(0x3F, GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S)
54#define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045c800 + ((_i) * 4))
55#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0
56#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M ICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S)
57#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30
58#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M ICE_M(0x3, GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S)
59#define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045c900 + ((_i) * 4))
60#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0
61#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M ICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S)
62#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30
63#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M ICE_M(0x3, GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S)
64#define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045ca00 + ((_i) * 4))
65#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0
66#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M ICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S)
67#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30
68#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M ICE_M(0x3, GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S)
69#define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045cb00 + ((_i) * 4))
70#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0
71#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M ICE_M(0xFF, GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S)
72#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30
73#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M ICE_M(0x3, GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S)
74
75#define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4))
76#define QRXFLXP_CNTXT_RXDID_IDX_S 0
77#define QRXFLXP_CNTXT_RXDID_IDX_M ICE_M(0x3F, QRXFLXP_CNTXT_RXDID_IDX_S)
78#define QRXFLXP_CNTXT_RXDID_PRIO_S 8
79#define QRXFLXP_CNTXT_RXDID_PRIO_M ICE_M(0x7, QRXFLXP_CNTXT_RXDID_PRIO_S)
80#define QRXFLXP_CNTXT_TS_S 11
81#define QRXFLXP_CNTXT_TS_M BIT(QRXFLXP_CNTXT_TS_S)
82#define GLGEN_RSTAT 0x000B8188
83#define GLGEN_RSTAT_DEVSTATE_S 0
84#define GLGEN_RSTAT_DEVSTATE_M ICE_M(0x3, GLGEN_RSTAT_DEVSTATE_S)
85#define GLGEN_RSTCTL 0x000B8180
86#define GLGEN_RSTCTL_GRSTDEL_S 0
87#define GLGEN_RSTCTL_GRSTDEL_M ICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
88#define GLGEN_RSTAT_RESET_TYPE_S 2
89#define GLGEN_RSTAT_RESET_TYPE_M ICE_M(0x3, GLGEN_RSTAT_RESET_TYPE_S)
90#define GLGEN_RTRIG 0x000B8190
91#define GLGEN_RTRIG_CORER_S 0
92#define GLGEN_RTRIG_CORER_M BIT(GLGEN_RTRIG_CORER_S)
93#define GLGEN_RTRIG_GLOBR_S 1
94#define GLGEN_RTRIG_GLOBR_M BIT(GLGEN_RTRIG_GLOBR_S)
95#define GLGEN_STAT 0x000B612C
96#define PFGEN_CTRL 0x00091000
97#define PFGEN_CTRL_PFSWR_S 0
98#define PFGEN_CTRL_PFSWR_M BIT(PFGEN_CTRL_PFSWR_S)
99#define PFGEN_STATE 0x00088000
100#define PRTGEN_STATUS 0x000B8100
101#define PFHMC_ERRORDATA 0x00520500
102#define PFHMC_ERRORINFO 0x00520400
103#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4))
104#define GLINT_DYN_CTL_INTENA_S 0
105#define GLINT_DYN_CTL_INTENA_M BIT(GLINT_DYN_CTL_INTENA_S)
106#define GLINT_DYN_CTL_CLEARPBA_S 1
107#define GLINT_DYN_CTL_CLEARPBA_M BIT(GLINT_DYN_CTL_CLEARPBA_S)
108#define GLINT_DYN_CTL_SWINT_TRIG_S 2
109#define GLINT_DYN_CTL_SWINT_TRIG_M BIT(GLINT_DYN_CTL_SWINT_TRIG_S)
110#define GLINT_DYN_CTL_ITR_INDX_S 3
111#define GLINT_DYN_CTL_SW_ITR_INDX_S 25
112#define GLINT_DYN_CTL_SW_ITR_INDX_M ICE_M(0x3, GLINT_DYN_CTL_SW_ITR_INDX_S)
113#define GLINT_DYN_CTL_INTENA_MSK_S 31
114#define GLINT_DYN_CTL_INTENA_MSK_M BIT(GLINT_DYN_CTL_INTENA_MSK_S)
115#define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4))
116#define PFINT_FW_CTL 0x0016C800
117#define PFINT_FW_CTL_MSIX_INDX_S 0
118#define PFINT_FW_CTL_MSIX_INDX_M ICE_M(0x7FF, PFINT_FW_CTL_MSIX_INDX_S)
119#define PFINT_FW_CTL_ITR_INDX_S 11
120#define PFINT_FW_CTL_ITR_INDX_M ICE_M(0x3, PFINT_FW_CTL_ITR_INDX_S)
121#define PFINT_FW_CTL_CAUSE_ENA_S 30
122#define PFINT_FW_CTL_CAUSE_ENA_M BIT(PFINT_FW_CTL_CAUSE_ENA_S)
123#define PFINT_OICR 0x0016CA00
124#define PFINT_OICR_HLP_RDY_S 14
125#define PFINT_OICR_HLP_RDY_M BIT(PFINT_OICR_HLP_RDY_S)
126#define PFINT_OICR_CPM_RDY_S 15
127#define PFINT_OICR_CPM_RDY_M BIT(PFINT_OICR_CPM_RDY_S)
128#define PFINT_OICR_ECC_ERR_S 16
129#define PFINT_OICR_ECC_ERR_M BIT(PFINT_OICR_ECC_ERR_S)
130#define PFINT_OICR_MAL_DETECT_S 19
131#define PFINT_OICR_MAL_DETECT_M BIT(PFINT_OICR_MAL_DETECT_S)
132#define PFINT_OICR_GRST_S 20
133#define PFINT_OICR_GRST_M BIT(PFINT_OICR_GRST_S)
134#define PFINT_OICR_PCI_EXCEPTION_S 21
135#define PFINT_OICR_PCI_EXCEPTION_M BIT(PFINT_OICR_PCI_EXCEPTION_S)
136#define PFINT_OICR_GPIO_S 22
137#define PFINT_OICR_GPIO_M BIT(PFINT_OICR_GPIO_S)
138#define PFINT_OICR_STORM_DETECT_S 24
139#define PFINT_OICR_STORM_DETECT_M BIT(PFINT_OICR_STORM_DETECT_S)
140#define PFINT_OICR_HMC_ERR_S 26
141#define PFINT_OICR_HMC_ERR_M BIT(PFINT_OICR_HMC_ERR_S)
142#define PFINT_OICR_PE_CRITERR_S 28
143#define PFINT_OICR_PE_CRITERR_M BIT(PFINT_OICR_PE_CRITERR_S)
144#define PFINT_OICR_CTL 0x0016CA80
145#define PFINT_OICR_CTL_MSIX_INDX_S 0
146#define PFINT_OICR_CTL_MSIX_INDX_M ICE_M(0x7FF, PFINT_OICR_CTL_MSIX_INDX_S)
147#define PFINT_OICR_CTL_ITR_INDX_S 11
148#define PFINT_OICR_CTL_ITR_INDX_M ICE_M(0x3, PFINT_OICR_CTL_ITR_INDX_S)
149#define PFINT_OICR_CTL_CAUSE_ENA_S 30
150#define PFINT_OICR_CTL_CAUSE_ENA_M BIT(PFINT_OICR_CTL_CAUSE_ENA_S)
151#define PFINT_OICR_ENA 0x0016C900
152#define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4))
153#define QINT_RQCTL_MSIX_INDX_S 0
154#define QINT_RQCTL_ITR_INDX_S 11
155#define QINT_RQCTL_CAUSE_ENA_S 30
156#define QINT_RQCTL_CAUSE_ENA_M BIT(QINT_RQCTL_CAUSE_ENA_S)
157#define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4))
158#define QINT_TQCTL_MSIX_INDX_S 0
159#define QINT_TQCTL_ITR_INDX_S 11
160#define QINT_TQCTL_CAUSE_ENA_S 30
161#define QINT_TQCTL_CAUSE_ENA_M BIT(QINT_TQCTL_CAUSE_ENA_S)
162#define GLLAN_RCTL_0 0x002941F8
163#define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4))
164#define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4))
165#define QRX_CTRL_MAX_INDEX 2047
166#define QRX_CTRL_QENA_REQ_S 0
167#define QRX_CTRL_QENA_REQ_M BIT(QRX_CTRL_QENA_REQ_S)
168#define QRX_CTRL_QENA_STAT_S 2
169#define QRX_CTRL_QENA_STAT_M BIT(QRX_CTRL_QENA_STAT_S)
170#define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4))
171#define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4))
172#define GLNVM_FLA 0x000B6108
173#define GLNVM_FLA_LOCKED_S 6
174#define GLNVM_FLA_LOCKED_M BIT(GLNVM_FLA_LOCKED_S)
175#define GLNVM_GENS 0x000B6100
176#define GLNVM_GENS_SR_SIZE_S 5
177#define GLNVM_GENS_SR_SIZE_M ICE_M(0x7, GLNVM_GENS_SR_SIZE_S)
178#define GLNVM_ULD 0x000B6008
179#define GLNVM_ULD_CORER_DONE_S 3
180#define GLNVM_ULD_CORER_DONE_M BIT(GLNVM_ULD_CORER_DONE_S)
181#define GLNVM_ULD_GLOBR_DONE_S 4
182#define GLNVM_ULD_GLOBR_DONE_M BIT(GLNVM_ULD_GLOBR_DONE_S)
183#define PF_FUNC_RID 0x0009E880
184#define PF_FUNC_RID_FUNC_NUM_S 0
185#define PF_FUNC_RID_FUNC_NUM_M ICE_M(0x7, PF_FUNC_RID_FUNC_NUM_S)
186#define GLPRT_BPRCH(_i) (0x00381384 + ((_i) * 8))
187#define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8))
188#define GLPRT_BPTCH(_i) (0x00381244 + ((_i) * 8))
189#define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8))
190#define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8))
191#define GLPRT_GORCH(_i) (0x00380004 + ((_i) * 8))
192#define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8))
193#define GLPRT_GOTCH(_i) (0x00380B44 + ((_i) * 8))
194#define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8))
195#define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8))
196#define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8))
197#define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8))
198#define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8))
199#define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8))
200#define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8))
201#define GLPRT_MPRCH(_i) (0x00381344 + ((_i) * 8))
202#define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8))
203#define GLPRT_MPTCH(_i) (0x00381204 + ((_i) * 8))
204#define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8))
205#define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8))
206#define GLPRT_PRC1023H(_i) (0x00380A04 + ((_i) * 8))
207#define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8))
208#define GLPRT_PRC127H(_i) (0x00380944 + ((_i) * 8))
209#define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8))
210#define GLPRT_PRC1522H(_i) (0x00380A44 + ((_i) * 8))
211#define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8))
212#define GLPRT_PRC255H(_i) (0x00380984 + ((_i) * 8))
213#define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8))
214#define GLPRT_PRC511H(_i) (0x003809C4 + ((_i) * 8))
215#define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8))
216#define GLPRT_PRC64H(_i) (0x00380904 + ((_i) * 8))
217#define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8))
218#define GLPRT_PRC9522H(_i) (0x00380A84 + ((_i) * 8))
219#define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8))
220#define GLPRT_PTC1023H(_i) (0x00380C84 + ((_i) * 8))
221#define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8))
222#define GLPRT_PTC127H(_i) (0x00380BC4 + ((_i) * 8))
223#define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8))
224#define GLPRT_PTC1522H(_i) (0x00380CC4 + ((_i) * 8))
225#define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8))
226#define GLPRT_PTC255H(_i) (0x00380C04 + ((_i) * 8))
227#define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8))
228#define GLPRT_PTC511H(_i) (0x00380C44 + ((_i) * 8))
229#define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8))
230#define GLPRT_PTC64H(_i) (0x00380B84 + ((_i) * 8))
231#define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8))
232#define GLPRT_PTC9522H(_i) (0x00380D04 + ((_i) * 8))
233#define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8))
234#define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8))
235#define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8))
236#define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8))
237#define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8))
238#define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8))
239#define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8))
240#define GLPRT_UPRCH(_i) (0x00381304 + ((_i) * 8))
241#define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8))
242#define GLPRT_UPTCH(_i) (0x003811C4 + ((_i) * 8))
243#define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8))
244#define GLV_BPRCH(_i) (0x003B6004 + ((_i) * 8))
245#define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8))
246#define GLV_BPTCH(_i) (0x0030E004 + ((_i) * 8))
247#define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8))
248#define GLV_GORCH(_i) (0x003B0004 + ((_i) * 8))
249#define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8))
250#define GLV_GOTCH(_i) (0x00300004 + ((_i) * 8))
251#define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8))
252#define GLV_MPRCH(_i) (0x003B4004 + ((_i) * 8))
253#define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8))
254#define GLV_MPTCH(_i) (0x0030C004 + ((_i) * 8))
255#define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8))
256#define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4))
257#define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4))
258#define GLV_UPRCH(_i) (0x003B2004 + ((_i) * 8))
259#define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8))
260#define GLV_UPTCH(_i) (0x0030A004 + ((_i) * 8))
261#define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8))
262#define VSIQF_HKEY_MAX_INDEX 12
263
264#endif /* _ICE_HW_AUTOGEN_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4/* Machine-generated file */
5
6#ifndef _ICE_HW_AUTOGEN_H_
7#define _ICE_HW_AUTOGEN_H_
8
9#define PF0INT_ITR_0(_i) (0x03000004 + ((_i) * 4096))
10#define PF0INT_ITR_1(_i) (0x03000008 + ((_i) * 4096))
11#define PF0INT_ITR_2(_i) (0x0300000C + ((_i) * 4096))
12#define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))
13#define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4))
14#define QTX_COMM_HEAD_HEAD_S 0
15#define QTX_COMM_HEAD_HEAD_M ICE_M(0x1FFF, 0)
16#define PF_FW_ARQBAH 0x00080180
17#define PF_FW_ARQBAL 0x00080080
18#define PF_FW_ARQH 0x00080380
19#define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, 0)
20#define PF_FW_ARQLEN 0x00080280
21#define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0)
22#define PF_FW_ARQLEN_ARQVFE_M BIT(28)
23#define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
24#define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
25#define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
26#define PF_FW_ARQT 0x00080480
27#define PF_FW_ATQBAH 0x00080100
28#define PF_FW_ATQBAL 0x00080000
29#define PF_FW_ATQH 0x00080300
30#define PF_FW_ATQH_ATQH_M ICE_M(0x3FF, 0)
31#define PF_FW_ATQLEN 0x00080200
32#define PF_FW_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0)
33#define PF_FW_ATQLEN_ATQVFE_M BIT(28)
34#define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
35#define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
36#define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4))
37#define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
38#define PF_FW_ATQT 0x00080400
39#define PF_MBX_ARQBAH 0x0022E400
40#define PF_MBX_ARQBAL 0x0022E380
41#define PF_MBX_ARQH 0x0022E500
42#define PF_MBX_ARQH_ARQH_M ICE_M(0x3FF, 0)
43#define PF_MBX_ARQLEN 0x0022E480
44#define PF_MBX_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0)
45#define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
46#define PF_MBX_ARQT 0x0022E580
47#define PF_MBX_ATQBAH 0x0022E180
48#define PF_MBX_ATQBAL 0x0022E100
49#define PF_MBX_ATQH 0x0022E280
50#define PF_MBX_ATQH_ATQH_M ICE_M(0x3FF, 0)
51#define PF_MBX_ATQLEN 0x0022E200
52#define PF_MBX_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0)
53#define PF_MBX_ATQLEN_ATQENABLE_M BIT(31)
54#define PF_MBX_ATQT 0x0022E300
55#define PRTDCB_GENS 0x00083020
56#define PRTDCB_GENS_DCBX_STATUS_S 0
57#define PRTDCB_GENS_DCBX_STATUS_M ICE_M(0x7, 0)
58#define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4))
59#define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4))
60#define GLFLXP_RXDID_FLAGS(_i, _j) (0x0045D000 + ((_i) * 4 + (_j) * 256))
61#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S 0
62#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M ICE_M(0x3F, 0)
63#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S 8
64#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M ICE_M(0x3F, 8)
65#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S 16
66#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M ICE_M(0x3F, 16)
67#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S 24
68#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M ICE_M(0x3F, 24)
69#define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045c800 + ((_i) * 4))
70#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0
71#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M ICE_M(0xFF, 0)
72#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30
73#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M ICE_M(0x3, 30)
74#define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045c900 + ((_i) * 4))
75#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0
76#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M ICE_M(0xFF, 0)
77#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30
78#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M ICE_M(0x3, 30)
79#define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045ca00 + ((_i) * 4))
80#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0
81#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M ICE_M(0xFF, 0)
82#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30
83#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M ICE_M(0x3, 30)
84#define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045cb00 + ((_i) * 4))
85#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0
86#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M ICE_M(0xFF, 0)
87#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30
88#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M ICE_M(0x3, 30)
89#define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4))
90#define QRXFLXP_CNTXT_RXDID_IDX_S 0
91#define QRXFLXP_CNTXT_RXDID_IDX_M ICE_M(0x3F, 0)
92#define QRXFLXP_CNTXT_RXDID_PRIO_S 8
93#define QRXFLXP_CNTXT_RXDID_PRIO_M ICE_M(0x7, 8)
94#define GLGEN_RSTAT 0x000B8188
95#define GLGEN_RSTAT_DEVSTATE_M ICE_M(0x3, 0)
96#define GLGEN_RSTCTL 0x000B8180
97#define GLGEN_RSTCTL_GRSTDEL_S 0
98#define GLGEN_RSTCTL_GRSTDEL_M ICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
99#define GLGEN_RSTAT_RESET_TYPE_S 2
100#define GLGEN_RSTAT_RESET_TYPE_M ICE_M(0x3, 2)
101#define GLGEN_RTRIG 0x000B8190
102#define GLGEN_RTRIG_CORER_M BIT(0)
103#define GLGEN_RTRIG_GLOBR_M BIT(1)
104#define GLGEN_STAT 0x000B612C
105#define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4))
106#define PFGEN_CTRL 0x00091000
107#define PFGEN_CTRL_PFSWR_M BIT(0)
108#define PFGEN_STATE 0x00088000
109#define PRTGEN_STATUS 0x000B8100
110#define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4))
111#define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4))
112#define VPGEN_VFRSTAT_VFRD_M BIT(0)
113#define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4))
114#define VPGEN_VFRTRIG_VFSWR_M BIT(0)
115#define PFHMC_ERRORDATA 0x00520500
116#define PFHMC_ERRORINFO 0x00520400
117#define GLINT_CTL 0x0016CC54
118#define GLINT_CTL_DIS_AUTOMASK_M BIT(0)
119#define GLINT_CTL_ITR_GRAN_200_S 16
120#define GLINT_CTL_ITR_GRAN_200_M ICE_M(0xF, 16)
121#define GLINT_CTL_ITR_GRAN_100_S 20
122#define GLINT_CTL_ITR_GRAN_100_M ICE_M(0xF, 20)
123#define GLINT_CTL_ITR_GRAN_50_S 24
124#define GLINT_CTL_ITR_GRAN_50_M ICE_M(0xF, 24)
125#define GLINT_CTL_ITR_GRAN_25_S 28
126#define GLINT_CTL_ITR_GRAN_25_M ICE_M(0xF, 28)
127#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4))
128#define GLINT_DYN_CTL_INTENA_M BIT(0)
129#define GLINT_DYN_CTL_CLEARPBA_M BIT(1)
130#define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2)
131#define GLINT_DYN_CTL_ITR_INDX_S 3
132#define GLINT_DYN_CTL_ITR_INDX_M ICE_M(0x3, 3)
133#define GLINT_DYN_CTL_INTERVAL_S 5
134#define GLINT_DYN_CTL_INTERVAL_M ICE_M(0xFFF, 5)
135#define GLINT_DYN_CTL_SW_ITR_INDX_M ICE_M(0x3, 25)
136#define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30)
137#define GLINT_DYN_CTL_INTENA_MSK_M BIT(31)
138#define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4))
139#define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4))
140#define GLINT_RATE_INTRL_ENA_M BIT(6)
141#define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4))
142#define GLINT_VECT2FUNC_VF_NUM_S 0
143#define GLINT_VECT2FUNC_VF_NUM_M ICE_M(0xFF, 0)
144#define GLINT_VECT2FUNC_PF_NUM_S 12
145#define GLINT_VECT2FUNC_PF_NUM_M ICE_M(0x7, 12)
146#define GLINT_VECT2FUNC_IS_PF_S 16
147#define GLINT_VECT2FUNC_IS_PF_M BIT(16)
148#define PFINT_FW_CTL 0x0016C800
149#define PFINT_FW_CTL_MSIX_INDX_M ICE_M(0x7FF, 0)
150#define PFINT_FW_CTL_ITR_INDX_S 11
151#define PFINT_FW_CTL_ITR_INDX_M ICE_M(0x3, 11)
152#define PFINT_FW_CTL_CAUSE_ENA_M BIT(30)
153#define PFINT_MBX_CTL 0x0016B280
154#define PFINT_MBX_CTL_MSIX_INDX_M ICE_M(0x7FF, 0)
155#define PFINT_MBX_CTL_ITR_INDX_S 11
156#define PFINT_MBX_CTL_ITR_INDX_M ICE_M(0x3, 11)
157#define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30)
158#define PFINT_OICR 0x0016CA00
159#define PFINT_OICR_ECC_ERR_M BIT(16)
160#define PFINT_OICR_MAL_DETECT_M BIT(19)
161#define PFINT_OICR_GRST_M BIT(20)
162#define PFINT_OICR_PCI_EXCEPTION_M BIT(21)
163#define PFINT_OICR_HMC_ERR_M BIT(26)
164#define PFINT_OICR_PE_CRITERR_M BIT(28)
165#define PFINT_OICR_VFLR_M BIT(29)
166#define PFINT_OICR_SWINT_M BIT(31)
167#define PFINT_OICR_CTL 0x0016CA80
168#define PFINT_OICR_CTL_MSIX_INDX_M ICE_M(0x7FF, 0)
169#define PFINT_OICR_CTL_ITR_INDX_S 11
170#define PFINT_OICR_CTL_ITR_INDX_M ICE_M(0x3, 11)
171#define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30)
172#define PFINT_OICR_ENA 0x0016C900
173#define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4))
174#define QINT_RQCTL_MSIX_INDX_S 0
175#define QINT_RQCTL_MSIX_INDX_M ICE_M(0x7FF, 0)
176#define QINT_RQCTL_ITR_INDX_S 11
177#define QINT_RQCTL_ITR_INDX_M ICE_M(0x3, 11)
178#define QINT_RQCTL_CAUSE_ENA_M BIT(30)
179#define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4))
180#define QINT_TQCTL_MSIX_INDX_S 0
181#define QINT_TQCTL_MSIX_INDX_M ICE_M(0x7FF, 0)
182#define QINT_TQCTL_ITR_INDX_S 11
183#define QINT_TQCTL_ITR_INDX_M ICE_M(0x3, 11)
184#define QINT_TQCTL_CAUSE_ENA_M BIT(30)
185#define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4))
186#define VPINT_ALLOC_FIRST_S 0
187#define VPINT_ALLOC_FIRST_M ICE_M(0x7FF, 0)
188#define VPINT_ALLOC_LAST_S 12
189#define VPINT_ALLOC_LAST_M ICE_M(0x7FF, 12)
190#define VPINT_ALLOC_VALID_M BIT(31)
191#define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4))
192#define VPINT_ALLOC_PCI_FIRST_S 0
193#define VPINT_ALLOC_PCI_FIRST_M ICE_M(0x7FF, 0)
194#define VPINT_ALLOC_PCI_LAST_S 12
195#define VPINT_ALLOC_PCI_LAST_M ICE_M(0x7FF, 12)
196#define VPINT_ALLOC_PCI_VALID_M BIT(31)
197#define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4))
198#define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30)
199#define GLLAN_RCTL_0 0x002941F8
200#define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4))
201#define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4))
202#define QRX_CTRL_MAX_INDEX 2047
203#define QRX_CTRL_QENA_REQ_S 0
204#define QRX_CTRL_QENA_REQ_M BIT(0)
205#define QRX_CTRL_QENA_STAT_S 2
206#define QRX_CTRL_QENA_STAT_M BIT(2)
207#define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4))
208#define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4))
209#define QRX_TAIL_MAX_INDEX 2047
210#define QRX_TAIL_TAIL_S 0
211#define QRX_TAIL_TAIL_M ICE_M(0x1FFF, 0)
212#define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4))
213#define VPLAN_RX_QBASE_VFFIRSTQ_S 0
214#define VPLAN_RX_QBASE_VFFIRSTQ_M ICE_M(0x7FF, 0)
215#define VPLAN_RX_QBASE_VFNUMQ_S 16
216#define VPLAN_RX_QBASE_VFNUMQ_M ICE_M(0xFF, 16)
217#define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4))
218#define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0)
219#define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4))
220#define VPLAN_TX_QBASE_VFFIRSTQ_S 0
221#define VPLAN_TX_QBASE_VFFIRSTQ_M ICE_M(0x3FFF, 0)
222#define VPLAN_TX_QBASE_VFNUMQ_S 16
223#define VPLAN_TX_QBASE_VFNUMQ_M ICE_M(0xFF, 16)
224#define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4))
225#define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
226#define GL_MDET_RX 0x00294C00
227#define GL_MDET_RX_QNUM_S 0
228#define GL_MDET_RX_QNUM_M ICE_M(0x7FFF, 0)
229#define GL_MDET_RX_VF_NUM_S 15
230#define GL_MDET_RX_VF_NUM_M ICE_M(0xFF, 15)
231#define GL_MDET_RX_PF_NUM_S 23
232#define GL_MDET_RX_PF_NUM_M ICE_M(0x7, 23)
233#define GL_MDET_RX_MAL_TYPE_S 26
234#define GL_MDET_RX_MAL_TYPE_M ICE_M(0x1F, 26)
235#define GL_MDET_RX_VALID_M BIT(31)
236#define GL_MDET_TX_PQM 0x002D2E00
237#define GL_MDET_TX_PQM_PF_NUM_S 0
238#define GL_MDET_TX_PQM_PF_NUM_M ICE_M(0x7, 0)
239#define GL_MDET_TX_PQM_VF_NUM_S 4
240#define GL_MDET_TX_PQM_VF_NUM_M ICE_M(0xFF, 4)
241#define GL_MDET_TX_PQM_QNUM_S 12
242#define GL_MDET_TX_PQM_QNUM_M ICE_M(0x3FFF, 12)
243#define GL_MDET_TX_PQM_MAL_TYPE_S 26
244#define GL_MDET_TX_PQM_MAL_TYPE_M ICE_M(0x1F, 26)
245#define GL_MDET_TX_PQM_VALID_M BIT(31)
246#define GL_MDET_TX_TCLAN 0x000FC068
247#define GL_MDET_TX_TCLAN_QNUM_S 0
248#define GL_MDET_TX_TCLAN_QNUM_M ICE_M(0x7FFF, 0)
249#define GL_MDET_TX_TCLAN_VF_NUM_S 15
250#define GL_MDET_TX_TCLAN_VF_NUM_M ICE_M(0xFF, 15)
251#define GL_MDET_TX_TCLAN_PF_NUM_S 23
252#define GL_MDET_TX_TCLAN_PF_NUM_M ICE_M(0x7, 23)
253#define GL_MDET_TX_TCLAN_MAL_TYPE_S 26
254#define GL_MDET_TX_TCLAN_MAL_TYPE_M ICE_M(0x1F, 26)
255#define GL_MDET_TX_TCLAN_VALID_M BIT(31)
256#define PF_MDET_RX 0x00294280
257#define PF_MDET_RX_VALID_M BIT(0)
258#define PF_MDET_TX_PQM 0x002D2C80
259#define PF_MDET_TX_PQM_VALID_M BIT(0)
260#define PF_MDET_TX_TCLAN 0x000FC000
261#define PF_MDET_TX_TCLAN_VALID_M BIT(0)
262#define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4))
263#define VP_MDET_RX_VALID_M BIT(0)
264#define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4))
265#define VP_MDET_TX_PQM_VALID_M BIT(0)
266#define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4))
267#define VP_MDET_TX_TCLAN_VALID_M BIT(0)
268#define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4))
269#define VP_MDET_TX_TDPU_VALID_M BIT(0)
270#define GLNVM_FLA 0x000B6108
271#define GLNVM_FLA_LOCKED_M BIT(6)
272#define GLNVM_GENS 0x000B6100
273#define GLNVM_GENS_SR_SIZE_S 5
274#define GLNVM_GENS_SR_SIZE_M ICE_M(0x7, 5)
275#define GLNVM_ULD 0x000B6008
276#define GLNVM_ULD_CORER_DONE_M BIT(3)
277#define GLNVM_ULD_GLOBR_DONE_M BIT(4)
278#define GLPCI_CNF2 0x000BE004
279#define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1)
280#define PF_FUNC_RID 0x0009E880
281#define PF_FUNC_RID_FUNC_NUM_S 0
282#define PF_FUNC_RID_FUNC_NUM_M ICE_M(0x7, 0)
283#define PF_PCI_CIAA 0x0009E580
284#define PF_PCI_CIAA_VF_NUM_S 12
285#define PF_PCI_CIAD 0x0009E500
286#define GL_PWR_MODE_CTL 0x000B820C
287#define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30
288#define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30)
289#define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8))
290#define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8))
291#define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8))
292#define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8))
293#define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8))
294#define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8))
295#define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8))
296#define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8))
297#define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8))
298#define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8))
299#define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8))
300#define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8))
301#define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8))
302#define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8))
303#define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8))
304#define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8))
305#define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8))
306#define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8))
307#define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8))
308#define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8))
309#define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8))
310#define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8))
311#define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8))
312#define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8))
313#define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8))
314#define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8))
315#define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8))
316#define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8))
317#define GLPRT_PXOFFRXC(_i, _j) (0x00380500 + ((_i) * 8 + (_j) * 64))
318#define GLPRT_PXOFFTXC(_i, _j) (0x00380F40 + ((_i) * 8 + (_j) * 64))
319#define GLPRT_PXONRXC(_i, _j) (0x00380300 + ((_i) * 8 + (_j) * 64))
320#define GLPRT_PXONTXC(_i, _j) (0x00380D40 + ((_i) * 8 + (_j) * 64))
321#define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8))
322#define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8))
323#define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8))
324#define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8))
325#define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8))
326#define GLPRT_RXON2OFFCNT(_i, _j) (0x00380700 + ((_i) * 8 + (_j) * 64))
327#define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8))
328#define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8))
329#define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8))
330#define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8))
331#define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8))
332#define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8))
333#define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8))
334#define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8))
335#define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8))
336#define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4))
337#define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4))
338#define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8))
339#define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8))
340#define PF_VT_PFALLOC_HIF 0x0009DD80
341#define VSIQF_HKEY_MAX_INDEX 12
342#define VSIQF_HLUT_MAX_INDEX 15
343#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4))
344#define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)
345#define PRTRPB_RDPC 0x000AC260
346
347#endif /* _ICE_HW_AUTOGEN_H_ */