1// SPDX-License-Identifier: GPL-2.0
   2/* Ethernet device driver for Cortina Systems Gemini SoC
   3 * Also known as the StorLink SL3512 and SL3516 (SL351x) or Lepus
   4 * Net Engine and Gigabit Ethernet MAC (GMAC)
   5 * This hardware contains a TCP Offload Engine (TOE) but currently the
   6 * driver does not make use of it.
   7 *
   8 * Authors:
   9 * Linus Walleij <linus.walleij@linaro.org>
  10 * Tobias Waldvogel <tobias.waldvogel@gmail.com> (OpenWRT)
  11 * Michał Mirosław <mirq-linux@rere.qmqm.pl>
  12 * Paulius Zaleckas <paulius.zaleckas@gmail.com>
  13 * Giuseppe De Robertis <Giuseppe.DeRobertis@ba.infn.it>
  14 * Gary Chen & Ch Hsu Storlink Semiconductor
  15 */
  16#include <linux/kernel.h>
  17#include <linux/init.h>
  18#include <linux/module.h>
  19#include <linux/platform_device.h>
  20#include <linux/spinlock.h>
  21#include <linux/slab.h>
  22#include <linux/dma-mapping.h>
  23#include <linux/cache.h>
  24#include <linux/interrupt.h>
  25#include <linux/reset.h>
  26#include <linux/clk.h>
  27#include <linux/of.h>
  28#include <linux/of_mdio.h>
  29#include <linux/of_net.h>
  30#include <linux/of_platform.h>
  31#include <linux/etherdevice.h>
  32#include <linux/if_vlan.h>
  33#include <linux/skbuff.h>
  34#include <linux/phy.h>
  35#include <linux/crc32.h>
  36#include <linux/ethtool.h>
  37#include <linux/tcp.h>
  38#include <linux/u64_stats_sync.h>
  39
  40#include <linux/in.h>
  41#include <linux/ip.h>
  42#include <linux/ipv6.h>
  43
  44#include "gemini.h"
  45
  46#define DRV_NAME		"gmac-gemini"
  47#define DRV_VERSION		"1.0"
  48
 
 
 
 
 
  49#define HSIZE_8			0x00
  50#define HSIZE_16		0x01
  51#define HSIZE_32		0x02
  52
  53#define HBURST_SINGLE		0x00
  54#define HBURST_INCR		0x01
  55#define HBURST_INCR4		0x02
  56#define HBURST_INCR8		0x03
  57
  58#define HPROT_DATA_CACHE	BIT(0)
  59#define HPROT_PRIVILIGED	BIT(1)
  60#define HPROT_BUFFERABLE	BIT(2)
  61#define HPROT_CACHABLE		BIT(3)
  62
  63#define DEFAULT_RX_COALESCE_NSECS	0
  64#define DEFAULT_GMAC_RXQ_ORDER		9
  65#define DEFAULT_GMAC_TXQ_ORDER		8
  66#define DEFAULT_RX_BUF_ORDER		11
  67#define DEFAULT_NAPI_WEIGHT		64
  68#define TX_MAX_FRAGS			16
  69#define TX_QUEUE_NUM			1	/* max: 6 */
  70#define RX_MAX_ALLOC_ORDER		2
  71
  72#define GMAC0_IRQ0_2 (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT | \
  73		      GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT)
  74#define GMAC0_IRQ0_TXQ0_INTS (GMAC0_SWTQ00_EOF_INT_BIT | \
  75			      GMAC0_SWTQ00_FIN_INT_BIT)
  76#define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
  77
  78#define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
  79		NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
  80		NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
  81
  82/**
  83 * struct gmac_queue_page - page buffer per-page info
  84 */
  85struct gmac_queue_page {
  86	struct page *page;
  87	dma_addr_t mapping;
  88};
  89
  90struct gmac_txq {
  91	struct gmac_txdesc *ring;
  92	struct sk_buff	**skb;
  93	unsigned int	cptr;
  94	unsigned int	noirq_packets;
  95};
  96
  97struct gemini_ethernet;
  98
  99struct gemini_ethernet_port {
 100	u8 id; /* 0 or 1 */
 101
 102	struct gemini_ethernet *geth;
 103	struct net_device *netdev;
 104	struct device *dev;
 105	void __iomem *dma_base;
 106	void __iomem *gmac_base;
 107	struct clk *pclk;
 108	struct reset_control *reset;
 109	int irq;
 110	__le32 mac_addr[3];
 111
 112	void __iomem		*rxq_rwptr;
 113	struct gmac_rxdesc	*rxq_ring;
 114	unsigned int		rxq_order;
 115
 116	struct napi_struct	napi;
 117	struct hrtimer		rx_coalesce_timer;
 118	unsigned int		rx_coalesce_nsecs;
 119	unsigned int		freeq_refill;
 120	struct gmac_txq		txq[TX_QUEUE_NUM];
 121	unsigned int		txq_order;
 122	unsigned int		irq_every_tx_packets;
 123
 124	dma_addr_t		rxq_dma_base;
 125	dma_addr_t		txq_dma_base;
 126
 127	unsigned int		msg_enable;
 128	spinlock_t		config_lock; /* Locks config register */
 129
 130	struct u64_stats_sync	tx_stats_syncp;
 131	struct u64_stats_sync	rx_stats_syncp;
 132	struct u64_stats_sync	ir_stats_syncp;
 133
 134	struct rtnl_link_stats64 stats;
 135	u64			hw_stats[RX_STATS_NUM];
 136	u64			rx_stats[RX_STATUS_NUM];
 137	u64			rx_csum_stats[RX_CHKSUM_NUM];
 138	u64			rx_napi_exits;
 139	u64			tx_frag_stats[TX_MAX_FRAGS];
 140	u64			tx_frags_linearized;
 141	u64			tx_hw_csummed;
 142};
 143
 144struct gemini_ethernet {
 145	struct device *dev;
 146	void __iomem *base;
 147	struct gemini_ethernet_port *port0;
 148	struct gemini_ethernet_port *port1;
 
 149
 150	spinlock_t	irq_lock; /* Locks IRQ-related registers */
 151	unsigned int	freeq_order;
 152	unsigned int	freeq_frag_order;
 153	struct gmac_rxdesc *freeq_ring;
 154	dma_addr_t	freeq_dma_base;
 155	struct gmac_queue_page	*freeq_pages;
 156	unsigned int	num_freeq_pages;
 157	spinlock_t	freeq_lock; /* Locks queue from reentrance */
 158};
 159
 160#define GMAC_STATS_NUM	( \
 161	RX_STATS_NUM + RX_STATUS_NUM + RX_CHKSUM_NUM + 1 + \
 162	TX_MAX_FRAGS + 2)
 163
 164static const char gmac_stats_strings[GMAC_STATS_NUM][ETH_GSTRING_LEN] = {
 165	"GMAC_IN_DISCARDS",
 166	"GMAC_IN_ERRORS",
 167	"GMAC_IN_MCAST",
 168	"GMAC_IN_BCAST",
 169	"GMAC_IN_MAC1",
 170	"GMAC_IN_MAC2",
 171	"RX_STATUS_GOOD_FRAME",
 172	"RX_STATUS_TOO_LONG_GOOD_CRC",
 173	"RX_STATUS_RUNT_FRAME",
 174	"RX_STATUS_SFD_NOT_FOUND",
 175	"RX_STATUS_CRC_ERROR",
 176	"RX_STATUS_TOO_LONG_BAD_CRC",
 177	"RX_STATUS_ALIGNMENT_ERROR",
 178	"RX_STATUS_TOO_LONG_BAD_ALIGN",
 179	"RX_STATUS_RX_ERR",
 180	"RX_STATUS_DA_FILTERED",
 181	"RX_STATUS_BUFFER_FULL",
 182	"RX_STATUS_11",
 183	"RX_STATUS_12",
 184	"RX_STATUS_13",
 185	"RX_STATUS_14",
 186	"RX_STATUS_15",
 187	"RX_CHKSUM_IP_UDP_TCP_OK",
 188	"RX_CHKSUM_IP_OK_ONLY",
 189	"RX_CHKSUM_NONE",
 190	"RX_CHKSUM_3",
 191	"RX_CHKSUM_IP_ERR_UNKNOWN",
 192	"RX_CHKSUM_IP_ERR",
 193	"RX_CHKSUM_TCP_UDP_ERR",
 194	"RX_CHKSUM_7",
 195	"RX_NAPI_EXITS",
 196	"TX_FRAGS[1]",
 197	"TX_FRAGS[2]",
 198	"TX_FRAGS[3]",
 199	"TX_FRAGS[4]",
 200	"TX_FRAGS[5]",
 201	"TX_FRAGS[6]",
 202	"TX_FRAGS[7]",
 203	"TX_FRAGS[8]",
 204	"TX_FRAGS[9]",
 205	"TX_FRAGS[10]",
 206	"TX_FRAGS[11]",
 207	"TX_FRAGS[12]",
 208	"TX_FRAGS[13]",
 209	"TX_FRAGS[14]",
 210	"TX_FRAGS[15]",
 211	"TX_FRAGS[16+]",
 212	"TX_FRAGS_LINEARIZED",
 213	"TX_HW_CSUMMED",
 214};
 215
 216static void gmac_dump_dma_state(struct net_device *netdev);
 217
 218static void gmac_update_config0_reg(struct net_device *netdev,
 219				    u32 val, u32 vmask)
 220{
 221	struct gemini_ethernet_port *port = netdev_priv(netdev);
 222	unsigned long flags;
 223	u32 reg;
 224
 225	spin_lock_irqsave(&port->config_lock, flags);
 226
 227	reg = readl(port->gmac_base + GMAC_CONFIG0);
 228	reg = (reg & ~vmask) | val;
 229	writel(reg, port->gmac_base + GMAC_CONFIG0);
 230
 231	spin_unlock_irqrestore(&port->config_lock, flags);
 232}
 233
 234static void gmac_enable_tx_rx(struct net_device *netdev)
 235{
 236	struct gemini_ethernet_port *port = netdev_priv(netdev);
 237	unsigned long flags;
 238	u32 reg;
 239
 240	spin_lock_irqsave(&port->config_lock, flags);
 241
 242	reg = readl(port->gmac_base + GMAC_CONFIG0);
 243	reg &= ~CONFIG0_TX_RX_DISABLE;
 244	writel(reg, port->gmac_base + GMAC_CONFIG0);
 245
 246	spin_unlock_irqrestore(&port->config_lock, flags);
 247}
 248
 249static void gmac_disable_tx_rx(struct net_device *netdev)
 250{
 251	struct gemini_ethernet_port *port = netdev_priv(netdev);
 252	unsigned long flags;
 253	u32 val;
 254
 255	spin_lock_irqsave(&port->config_lock, flags);
 256
 257	val = readl(port->gmac_base + GMAC_CONFIG0);
 258	val |= CONFIG0_TX_RX_DISABLE;
 259	writel(val, port->gmac_base + GMAC_CONFIG0);
 260
 261	spin_unlock_irqrestore(&port->config_lock, flags);
 262
 263	mdelay(10);	/* let GMAC consume packet */
 264}
 265
 266static void gmac_set_flow_control(struct net_device *netdev, bool tx, bool rx)
 267{
 268	struct gemini_ethernet_port *port = netdev_priv(netdev);
 269	unsigned long flags;
 270	u32 val;
 271
 272	spin_lock_irqsave(&port->config_lock, flags);
 273
 274	val = readl(port->gmac_base + GMAC_CONFIG0);
 275	val &= ~CONFIG0_FLOW_CTL;
 276	if (tx)
 277		val |= CONFIG0_FLOW_TX;
 278	if (rx)
 279		val |= CONFIG0_FLOW_RX;
 280	writel(val, port->gmac_base + GMAC_CONFIG0);
 281
 282	spin_unlock_irqrestore(&port->config_lock, flags);
 283}
 284
 285static void gmac_speed_set(struct net_device *netdev)
 286{
 287	struct gemini_ethernet_port *port = netdev_priv(netdev);
 288	struct phy_device *phydev = netdev->phydev;
 289	union gmac_status status, old_status;
 290	int pause_tx = 0;
 291	int pause_rx = 0;
 292
 293	status.bits32 = readl(port->gmac_base + GMAC_STATUS);
 294	old_status.bits32 = status.bits32;
 295	status.bits.link = phydev->link;
 296	status.bits.duplex = phydev->duplex;
 297
 298	switch (phydev->speed) {
 299	case 1000:
 300		status.bits.speed = GMAC_SPEED_1000;
 301		if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
 302			status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
 303		netdev_info(netdev, "connect to RGMII @ 1Gbit\n");
 
 304		break;
 305	case 100:
 306		status.bits.speed = GMAC_SPEED_100;
 307		if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
 308			status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
 309		netdev_info(netdev, "connect to RGMII @ 100 Mbit\n");
 
 310		break;
 311	case 10:
 312		status.bits.speed = GMAC_SPEED_10;
 313		if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
 314			status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
 315		netdev_info(netdev, "connect to RGMII @ 10 Mbit\n");
 
 316		break;
 317	default:
 318		netdev_warn(netdev, "Not supported PHY speed (%d)\n",
 319			    phydev->speed);
 320	}
 321
 322	if (phydev->duplex == DUPLEX_FULL) {
 323		u16 lcladv = phy_read(phydev, MII_ADVERTISE);
 324		u16 rmtadv = phy_read(phydev, MII_LPA);
 325		u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
 326
 327		if (cap & FLOW_CTRL_RX)
 328			pause_rx = 1;
 329		if (cap & FLOW_CTRL_TX)
 330			pause_tx = 1;
 331	}
 332
 333	gmac_set_flow_control(netdev, pause_tx, pause_rx);
 334
 335	if (old_status.bits32 == status.bits32)
 336		return;
 337
 338	if (netif_msg_link(port)) {
 339		phy_print_status(phydev);
 340		netdev_info(netdev, "link flow control: %s\n",
 341			    phydev->pause
 342			    ? (phydev->asym_pause ? "tx" : "both")
 343			    : (phydev->asym_pause ? "rx" : "none")
 344		);
 345	}
 346
 347	gmac_disable_tx_rx(netdev);
 348	writel(status.bits32, port->gmac_base + GMAC_STATUS);
 349	gmac_enable_tx_rx(netdev);
 350}
 351
 352static int gmac_setup_phy(struct net_device *netdev)
 353{
 354	struct gemini_ethernet_port *port = netdev_priv(netdev);
 355	union gmac_status status = { .bits32 = 0 };
 356	struct device *dev = port->dev;
 357	struct phy_device *phy;
 358
 359	phy = of_phy_get_and_connect(netdev,
 360				     dev->of_node,
 361				     gmac_speed_set);
 362	if (!phy)
 363		return -ENODEV;
 364	netdev->phydev = phy;
 365
 366	netdev_info(netdev, "connected to PHY \"%s\"\n",
 367		    phydev_name(phy));
 368	phy_attached_print(phy, "phy_id=0x%.8lx, phy_mode=%s\n",
 369			   (unsigned long)phy->phy_id,
 370			   phy_modes(phy->interface));
 371
 372	phy->supported &= PHY_GBIT_FEATURES;
 373	phy->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause;
 374	phy->advertising = phy->supported;
 375
 376	/* set PHY interface type */
 377	switch (phy->interface) {
 378	case PHY_INTERFACE_MODE_MII:
 379		netdev_info(netdev, "set GMAC0 to GMII mode, GMAC1 disabled\n");
 
 380		status.bits.mii_rmii = GMAC_PHY_MII;
 381		netdev_info(netdev, "connect to MII\n");
 382		break;
 383	case PHY_INTERFACE_MODE_GMII:
 384		netdev_info(netdev, "set GMAC0 to GMII mode, GMAC1 disabled\n");
 
 385		status.bits.mii_rmii = GMAC_PHY_GMII;
 386		netdev_info(netdev, "connect to GMII\n");
 387		break;
 388	case PHY_INTERFACE_MODE_RGMII:
 389		dev_info(dev, "set GMAC0 and GMAC1 to MII/RGMII mode\n");
 
 390		status.bits.mii_rmii = GMAC_PHY_RGMII_100_10;
 391		netdev_info(netdev, "connect to RGMII\n");
 392		break;
 393	default:
 394		netdev_err(netdev, "Unsupported MII interface\n");
 395		phy_disconnect(phy);
 396		netdev->phydev = NULL;
 397		return -EINVAL;
 398	}
 399	writel(status.bits32, port->gmac_base + GMAC_STATUS);
 400
 
 
 
 401	return 0;
 402}
 403
 404static int gmac_pick_rx_max_len(int max_l3_len)
 405{
 406	/* index = CONFIG_MAXLEN_XXX values */
 407	static const int max_len[8] = {
 408		1536, 1518, 1522, 1542,
 409		9212, 10236, 1518, 1518
 410	};
 411	int i, n = 5;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 412
 413	max_l3_len += ETH_HLEN + VLAN_HLEN;
 
 
 
 
 414
 415	if (max_l3_len > max_len[n])
 416		return -1;
 417
 418	for (i = 0; i < 5; i++) {
 419		if (max_len[i] >= max_l3_len && max_len[i] < max_len[n])
 420			n = i;
 
 421	}
 422
 423	return n;
 424}
 425
 426static int gmac_init(struct net_device *netdev)
 427{
 428	struct gemini_ethernet_port *port = netdev_priv(netdev);
 429	union gmac_config0 config0 = { .bits = {
 430		.dis_tx = 1,
 431		.dis_rx = 1,
 432		.ipv4_rx_chksum = 1,
 433		.ipv6_rx_chksum = 1,
 434		.rx_err_detect = 1,
 435		.rgmm_edge = 1,
 436		.port0_chk_hwq = 1,
 437		.port1_chk_hwq = 1,
 438		.port0_chk_toeq = 1,
 439		.port1_chk_toeq = 1,
 440		.port0_chk_classq = 1,
 441		.port1_chk_classq = 1,
 442	} };
 443	union gmac_ahb_weight ahb_weight = { .bits = {
 444		.rx_weight = 1,
 445		.tx_weight = 1,
 446		.hash_weight = 1,
 447		.pre_req = 0x1f,
 448		.tq_dv_threshold = 0,
 449	} };
 450	union gmac_tx_wcr0 hw_weigh = { .bits = {
 451		.hw_tq3 = 1,
 452		.hw_tq2 = 1,
 453		.hw_tq1 = 1,
 454		.hw_tq0 = 1,
 455	} };
 456	union gmac_tx_wcr1 sw_weigh = { .bits = {
 457		.sw_tq5 = 1,
 458		.sw_tq4 = 1,
 459		.sw_tq3 = 1,
 460		.sw_tq2 = 1,
 461		.sw_tq1 = 1,
 462		.sw_tq0 = 1,
 463	} };
 464	union gmac_config1 config1 = { .bits = {
 465		.set_threshold = 16,
 466		.rel_threshold = 24,
 467	} };
 468	union gmac_config2 config2 = { .bits = {
 469		.set_threshold = 16,
 470		.rel_threshold = 32,
 471	} };
 472	union gmac_config3 config3 = { .bits = {
 473		.set_threshold = 0,
 474		.rel_threshold = 0,
 475	} };
 476	union gmac_config0 tmp;
 477	u32 val;
 478
 479	config0.bits.max_len = gmac_pick_rx_max_len(netdev->mtu);
 480	tmp.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
 481	config0.bits.reserved = tmp.bits.reserved;
 482	writel(config0.bits32, port->gmac_base + GMAC_CONFIG0);
 483	writel(config1.bits32, port->gmac_base + GMAC_CONFIG1);
 484	writel(config2.bits32, port->gmac_base + GMAC_CONFIG2);
 485	writel(config3.bits32, port->gmac_base + GMAC_CONFIG3);
 486
 487	val = readl(port->dma_base + GMAC_AHB_WEIGHT_REG);
 488	writel(ahb_weight.bits32, port->dma_base + GMAC_AHB_WEIGHT_REG);
 489
 490	writel(hw_weigh.bits32,
 491	       port->dma_base + GMAC_TX_WEIGHTING_CTRL_0_REG);
 492	writel(sw_weigh.bits32,
 493	       port->dma_base + GMAC_TX_WEIGHTING_CTRL_1_REG);
 494
 495	port->rxq_order = DEFAULT_GMAC_RXQ_ORDER;
 496	port->txq_order = DEFAULT_GMAC_TXQ_ORDER;
 497	port->rx_coalesce_nsecs = DEFAULT_RX_COALESCE_NSECS;
 498
 499	/* Mark every quarter of the queue a packet for interrupt
 500	 * in order to be able to wake up the queue if it was stopped
 501	 */
 502	port->irq_every_tx_packets = 1 << (port->txq_order - 2);
 503
 504	return 0;
 505}
 506
 507static void gmac_uninit(struct net_device *netdev)
 508{
 509	if (netdev->phydev)
 510		phy_disconnect(netdev->phydev);
 511}
 512
 513static int gmac_setup_txqs(struct net_device *netdev)
 514{
 515	struct gemini_ethernet_port *port = netdev_priv(netdev);
 516	unsigned int n_txq = netdev->num_tx_queues;
 517	struct gemini_ethernet *geth = port->geth;
 518	size_t entries = 1 << port->txq_order;
 519	struct gmac_txq *txq = port->txq;
 520	struct gmac_txdesc *desc_ring;
 521	size_t len = n_txq * entries;
 522	struct sk_buff **skb_tab;
 523	void __iomem *rwptr_reg;
 524	unsigned int r;
 525	int i;
 526
 527	rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
 528
 529	skb_tab = kcalloc(len, sizeof(*skb_tab), GFP_KERNEL);
 530	if (!skb_tab)
 531		return -ENOMEM;
 532
 533	desc_ring = dma_alloc_coherent(geth->dev, len * sizeof(*desc_ring),
 534				       &port->txq_dma_base, GFP_KERNEL);
 535
 536	if (!desc_ring) {
 537		kfree(skb_tab);
 538		return -ENOMEM;
 539	}
 540
 541	if (port->txq_dma_base & ~DMA_Q_BASE_MASK) {
 542		dev_warn(geth->dev, "TX queue base it not aligned\n");
 543		kfree(skb_tab);
 544		return -ENOMEM;
 545	}
 546
 547	writel(port->txq_dma_base | port->txq_order,
 548	       port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
 549
 550	for (i = 0; i < n_txq; i++) {
 551		txq->ring = desc_ring;
 552		txq->skb = skb_tab;
 553		txq->noirq_packets = 0;
 554
 555		r = readw(rwptr_reg);
 556		rwptr_reg += 2;
 557		writew(r, rwptr_reg);
 558		rwptr_reg += 2;
 559		txq->cptr = r;
 560
 561		txq++;
 562		desc_ring += entries;
 563		skb_tab += entries;
 564	}
 565
 566	return 0;
 567}
 568
 569static void gmac_clean_txq(struct net_device *netdev, struct gmac_txq *txq,
 570			   unsigned int r)
 571{
 572	struct gemini_ethernet_port *port = netdev_priv(netdev);
 573	unsigned int m = (1 << port->txq_order) - 1;
 574	struct gemini_ethernet *geth = port->geth;
 575	unsigned int c = txq->cptr;
 576	union gmac_txdesc_0 word0;
 577	union gmac_txdesc_1 word1;
 578	unsigned int hwchksum = 0;
 579	unsigned long bytes = 0;
 580	struct gmac_txdesc *txd;
 581	unsigned short nfrags;
 582	unsigned int errs = 0;
 583	unsigned int pkts = 0;
 584	unsigned int word3;
 585	dma_addr_t mapping;
 586
 587	if (c == r)
 588		return;
 589
 590	while (c != r) {
 591		txd = txq->ring + c;
 592		word0 = txd->word0;
 593		word1 = txd->word1;
 594		mapping = txd->word2.buf_adr;
 595		word3 = txd->word3.bits32;
 596
 597		dma_unmap_single(geth->dev, mapping,
 598				 word0.bits.buffer_size, DMA_TO_DEVICE);
 599
 600		if (word3 & EOF_BIT)
 601			dev_kfree_skb(txq->skb[c]);
 602
 603		c++;
 604		c &= m;
 605
 606		if (!(word3 & SOF_BIT))
 607			continue;
 608
 609		if (!word0.bits.status_tx_ok) {
 610			errs++;
 611			continue;
 612		}
 613
 614		pkts++;
 615		bytes += txd->word1.bits.byte_count;
 616
 617		if (word1.bits32 & TSS_CHECKUM_ENABLE)
 618			hwchksum++;
 619
 620		nfrags = word0.bits.desc_count - 1;
 621		if (nfrags) {
 622			if (nfrags >= TX_MAX_FRAGS)
 623				nfrags = TX_MAX_FRAGS - 1;
 624
 625			u64_stats_update_begin(&port->tx_stats_syncp);
 626			port->tx_frag_stats[nfrags]++;
 627			u64_stats_update_end(&port->ir_stats_syncp);
 628		}
 629	}
 630
 631	u64_stats_update_begin(&port->ir_stats_syncp);
 632	port->stats.tx_errors += errs;
 633	port->stats.tx_packets += pkts;
 634	port->stats.tx_bytes += bytes;
 635	port->tx_hw_csummed += hwchksum;
 636	u64_stats_update_end(&port->ir_stats_syncp);
 637
 638	txq->cptr = c;
 639}
 640
 641static void gmac_cleanup_txqs(struct net_device *netdev)
 642{
 643	struct gemini_ethernet_port *port = netdev_priv(netdev);
 644	unsigned int n_txq = netdev->num_tx_queues;
 645	struct gemini_ethernet *geth = port->geth;
 646	void __iomem *rwptr_reg;
 647	unsigned int r, i;
 648
 649	rwptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
 650
 651	for (i = 0; i < n_txq; i++) {
 652		r = readw(rwptr_reg);
 653		rwptr_reg += 2;
 654		writew(r, rwptr_reg);
 655		rwptr_reg += 2;
 656
 657		gmac_clean_txq(netdev, port->txq + i, r);
 658	}
 659	writel(0, port->dma_base + GMAC_SW_TX_QUEUE_BASE_REG);
 660
 661	kfree(port->txq->skb);
 662	dma_free_coherent(geth->dev,
 663			  n_txq * sizeof(*port->txq->ring) << port->txq_order,
 664			  port->txq->ring, port->txq_dma_base);
 665}
 666
 667static int gmac_setup_rxq(struct net_device *netdev)
 668{
 669	struct gemini_ethernet_port *port = netdev_priv(netdev);
 670	struct gemini_ethernet *geth = port->geth;
 671	struct nontoe_qhdr __iomem *qhdr;
 672
 673	qhdr = geth->base + TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
 674	port->rxq_rwptr = &qhdr->word1;
 675
 676	/* Remap a slew of memory to use for the RX queue */
 677	port->rxq_ring = dma_alloc_coherent(geth->dev,
 678				sizeof(*port->rxq_ring) << port->rxq_order,
 679				&port->rxq_dma_base, GFP_KERNEL);
 680	if (!port->rxq_ring)
 681		return -ENOMEM;
 682	if (port->rxq_dma_base & ~NONTOE_QHDR0_BASE_MASK) {
 683		dev_warn(geth->dev, "RX queue base it not aligned\n");
 684		return -ENOMEM;
 685	}
 686
 687	writel(port->rxq_dma_base | port->rxq_order, &qhdr->word0);
 688	writel(0, port->rxq_rwptr);
 689	return 0;
 690}
 691
 692static struct gmac_queue_page *
 693gmac_get_queue_page(struct gemini_ethernet *geth,
 694		    struct gemini_ethernet_port *port,
 695		    dma_addr_t addr)
 696{
 697	struct gmac_queue_page *gpage;
 698	dma_addr_t mapping;
 699	int i;
 700
 701	/* Only look for even pages */
 702	mapping = addr & PAGE_MASK;
 703
 704	if (!geth->freeq_pages) {
 705		dev_err(geth->dev, "try to get page with no page list\n");
 706		return NULL;
 707	}
 708
 709	/* Look up a ring buffer page from virtual mapping */
 710	for (i = 0; i < geth->num_freeq_pages; i++) {
 711		gpage = &geth->freeq_pages[i];
 712		if (gpage->mapping == mapping)
 713			return gpage;
 714	}
 715
 716	return NULL;
 717}
 718
 719static void gmac_cleanup_rxq(struct net_device *netdev)
 720{
 721	struct gemini_ethernet_port *port = netdev_priv(netdev);
 722	struct gemini_ethernet *geth = port->geth;
 723	struct gmac_rxdesc *rxd = port->rxq_ring;
 724	static struct gmac_queue_page *gpage;
 725	struct nontoe_qhdr __iomem *qhdr;
 726	void __iomem *dma_reg;
 727	void __iomem *ptr_reg;
 728	dma_addr_t mapping;
 729	union dma_rwptr rw;
 730	unsigned int r, w;
 731
 732	qhdr = geth->base +
 733		TOE_DEFAULT_Q_HDR_BASE(netdev->dev_id);
 734	dma_reg = &qhdr->word0;
 735	ptr_reg = &qhdr->word1;
 736
 737	rw.bits32 = readl(ptr_reg);
 738	r = rw.bits.rptr;
 739	w = rw.bits.wptr;
 740	writew(r, ptr_reg + 2);
 741
 742	writel(0, dma_reg);
 743
 744	/* Loop from read pointer to write pointer of the RX queue
 745	 * and free up all pages by the queue.
 746	 */
 747	while (r != w) {
 748		mapping = rxd[r].word2.buf_adr;
 749		r++;
 750		r &= ((1 << port->rxq_order) - 1);
 751
 752		if (!mapping)
 753			continue;
 754
 755		/* Freeq pointers are one page off */
 756		gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
 757		if (!gpage) {
 758			dev_err(geth->dev, "could not find page\n");
 759			continue;
 760		}
 761		/* Release the RX queue reference to the page */
 762		put_page(gpage->page);
 763	}
 764
 765	dma_free_coherent(geth->dev, sizeof(*port->rxq_ring) << port->rxq_order,
 766			  port->rxq_ring, port->rxq_dma_base);
 767}
 768
 769static struct page *geth_freeq_alloc_map_page(struct gemini_ethernet *geth,
 770					      int pn)
 771{
 772	struct gmac_rxdesc *freeq_entry;
 773	struct gmac_queue_page *gpage;
 774	unsigned int fpp_order;
 775	unsigned int frag_len;
 776	dma_addr_t mapping;
 777	struct page *page;
 778	int i;
 779
 780	/* First allocate and DMA map a single page */
 781	page = alloc_page(GFP_ATOMIC);
 782	if (!page)
 783		return NULL;
 784
 785	mapping = dma_map_single(geth->dev, page_address(page),
 786				 PAGE_SIZE, DMA_FROM_DEVICE);
 787	if (dma_mapping_error(geth->dev, mapping)) {
 788		put_page(page);
 789		return NULL;
 790	}
 791
 792	/* The assign the page mapping (physical address) to the buffer address
 793	 * in the hardware queue. PAGE_SHIFT on ARM is 12 (1 page is 4096 bytes,
 794	 * 4k), and the default RX frag order is 11 (fragments are up 20 2048
 795	 * bytes, 2k) so fpp_order (fragments per page order) is default 1. Thus
 796	 * each page normally needs two entries in the queue.
 797	 */
 798	frag_len = 1 << geth->freeq_frag_order; /* Usually 2048 */
 799	fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
 800	freeq_entry = geth->freeq_ring + (pn << fpp_order);
 801	dev_dbg(geth->dev, "allocate page %d fragment length %d fragments per page %d, freeq entry %p\n",
 802		 pn, frag_len, (1 << fpp_order), freeq_entry);
 803	for (i = (1 << fpp_order); i > 0; i--) {
 804		freeq_entry->word2.buf_adr = mapping;
 805		freeq_entry++;
 806		mapping += frag_len;
 807	}
 808
 809	/* If the freeq entry already has a page mapped, then unmap it. */
 810	gpage = &geth->freeq_pages[pn];
 811	if (gpage->page) {
 812		mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
 813		dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
 814		/* This should be the last reference to the page so it gets
 815		 * released
 816		 */
 817		put_page(gpage->page);
 818	}
 819
 820	/* Then put our new mapping into the page table */
 821	dev_dbg(geth->dev, "page %d, DMA addr: %08x, page %p\n",
 822		pn, (unsigned int)mapping, page);
 823	gpage->mapping = mapping;
 824	gpage->page = page;
 825
 826	return page;
 827}
 828
 829/**
 830 * geth_fill_freeq() - Fill the freeq with empty fragments to use
 831 * @geth: the ethernet adapter
 832 * @refill: whether to reset the queue by filling in all freeq entries or
 833 * just refill it, usually the interrupt to refill the queue happens when
 834 * the queue is half empty.
 835 */
 836static unsigned int geth_fill_freeq(struct gemini_ethernet *geth, bool refill)
 837{
 838	unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
 839	unsigned int count = 0;
 840	unsigned int pn, epn;
 841	unsigned long flags;
 842	union dma_rwptr rw;
 843	unsigned int m_pn;
 844
 845	/* Mask for page */
 846	m_pn = (1 << (geth->freeq_order - fpp_order)) - 1;
 847
 848	spin_lock_irqsave(&geth->freeq_lock, flags);
 849
 850	rw.bits32 = readl(geth->base + GLOBAL_SWFQ_RWPTR_REG);
 851	pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order;
 852	epn = (rw.bits.rptr >> fpp_order) - 1;
 853	epn &= m_pn;
 854
 855	/* Loop over the freeq ring buffer entries */
 856	while (pn != epn) {
 857		struct gmac_queue_page *gpage;
 858		struct page *page;
 859
 860		gpage = &geth->freeq_pages[pn];
 861		page = gpage->page;
 862
 863		dev_dbg(geth->dev, "fill entry %d page ref count %d add %d refs\n",
 864			pn, page_ref_count(page), 1 << fpp_order);
 865
 866		if (page_ref_count(page) > 1) {
 867			unsigned int fl = (pn - epn) & m_pn;
 868
 869			if (fl > 64 >> fpp_order)
 870				break;
 871
 872			page = geth_freeq_alloc_map_page(geth, pn);
 873			if (!page)
 874				break;
 875		}
 876
 877		/* Add one reference per fragment in the page */
 878		page_ref_add(page, 1 << fpp_order);
 879		count += 1 << fpp_order;
 880		pn++;
 881		pn &= m_pn;
 882	}
 883
 884	writew(pn << fpp_order, geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
 885
 886	spin_unlock_irqrestore(&geth->freeq_lock, flags);
 887
 888	return count;
 889}
 890
 891static int geth_setup_freeq(struct gemini_ethernet *geth)
 892{
 893	unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
 894	unsigned int frag_len = 1 << geth->freeq_frag_order;
 895	unsigned int len = 1 << geth->freeq_order;
 896	unsigned int pages = len >> fpp_order;
 897	union queue_threshold qt;
 898	union dma_skb_size skbsz;
 899	unsigned int filled;
 900	unsigned int pn;
 901
 902	geth->freeq_ring = dma_alloc_coherent(geth->dev,
 903		sizeof(*geth->freeq_ring) << geth->freeq_order,
 904		&geth->freeq_dma_base, GFP_KERNEL);
 905	if (!geth->freeq_ring)
 906		return -ENOMEM;
 907	if (geth->freeq_dma_base & ~DMA_Q_BASE_MASK) {
 908		dev_warn(geth->dev, "queue ring base it not aligned\n");
 909		goto err_freeq;
 910	}
 911
 912	/* Allocate a mapping to page look-up index */
 913	geth->freeq_pages = kzalloc(pages * sizeof(*geth->freeq_pages),
 914				   GFP_KERNEL);
 915	if (!geth->freeq_pages)
 916		goto err_freeq;
 917	geth->num_freeq_pages = pages;
 918
 919	dev_info(geth->dev, "allocate %d pages for queue\n", pages);
 920	for (pn = 0; pn < pages; pn++)
 921		if (!geth_freeq_alloc_map_page(geth, pn))
 922			goto err_freeq_alloc;
 923
 924	filled = geth_fill_freeq(geth, false);
 925	if (!filled)
 926		goto err_freeq_alloc;
 927
 928	qt.bits32 = readl(geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
 929	qt.bits.swfq_empty = 32;
 930	writel(qt.bits32, geth->base + GLOBAL_QUEUE_THRESHOLD_REG);
 931
 932	skbsz.bits.sw_skb_size = 1 << geth->freeq_frag_order;
 933	writel(skbsz.bits32, geth->base + GLOBAL_DMA_SKB_SIZE_REG);
 934	writel(geth->freeq_dma_base | geth->freeq_order,
 935	       geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
 936
 937	return 0;
 938
 939err_freeq_alloc:
 940	while (pn > 0) {
 941		struct gmac_queue_page *gpage;
 942		dma_addr_t mapping;
 943
 944		--pn;
 945		mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
 946		dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
 947		gpage = &geth->freeq_pages[pn];
 948		put_page(gpage->page);
 949	}
 950
 951	kfree(geth->freeq_pages);
 952err_freeq:
 953	dma_free_coherent(geth->dev,
 954			  sizeof(*geth->freeq_ring) << geth->freeq_order,
 955			  geth->freeq_ring, geth->freeq_dma_base);
 956	geth->freeq_ring = NULL;
 957	return -ENOMEM;
 958}
 959
 960/**
 961 * geth_cleanup_freeq() - cleanup the DMA mappings and free the queue
 962 * @geth: the Gemini global ethernet state
 963 */
 964static void geth_cleanup_freeq(struct gemini_ethernet *geth)
 965{
 966	unsigned int fpp_order = PAGE_SHIFT - geth->freeq_frag_order;
 967	unsigned int frag_len = 1 << geth->freeq_frag_order;
 968	unsigned int len = 1 << geth->freeq_order;
 969	unsigned int pages = len >> fpp_order;
 970	unsigned int pn;
 971
 972	writew(readw(geth->base + GLOBAL_SWFQ_RWPTR_REG),
 973	       geth->base + GLOBAL_SWFQ_RWPTR_REG + 2);
 974	writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
 975
 976	for (pn = 0; pn < pages; pn++) {
 977		struct gmac_queue_page *gpage;
 978		dma_addr_t mapping;
 979
 980		mapping = geth->freeq_ring[pn << fpp_order].word2.buf_adr;
 981		dma_unmap_single(geth->dev, mapping, frag_len, DMA_FROM_DEVICE);
 982
 983		gpage = &geth->freeq_pages[pn];
 984		while (page_ref_count(gpage->page) > 0)
 985			put_page(gpage->page);
 986	}
 987
 988	kfree(geth->freeq_pages);
 989
 990	dma_free_coherent(geth->dev,
 991			  sizeof(*geth->freeq_ring) << geth->freeq_order,
 992			  geth->freeq_ring, geth->freeq_dma_base);
 993}
 994
 995/**
 996 * geth_resize_freeq() - resize the software queue depth
 997 * @port: the port requesting the change
 998 *
 999 * This gets called at least once during probe() so the device queue gets
1000 * "resized" from the hardware defaults. Since both ports/net devices share
1001 * the same hardware queue, some synchronization between the ports is
1002 * needed.
1003 */
1004static int geth_resize_freeq(struct gemini_ethernet_port *port)
1005{
1006	struct gemini_ethernet *geth = port->geth;
1007	struct net_device *netdev = port->netdev;
1008	struct gemini_ethernet_port *other_port;
1009	struct net_device *other_netdev;
1010	unsigned int new_size = 0;
1011	unsigned int new_order;
1012	unsigned long flags;
1013	u32 en;
1014	int ret;
1015
1016	if (netdev->dev_id == 0)
1017		other_netdev = geth->port1->netdev;
1018	else
1019		other_netdev = geth->port0->netdev;
1020
1021	if (other_netdev && netif_running(other_netdev))
1022		return -EBUSY;
1023
1024	new_size = 1 << (port->rxq_order + 1);
1025	netdev_dbg(netdev, "port %d size: %d order %d\n",
1026		   netdev->dev_id,
1027		   new_size,
1028		   port->rxq_order);
1029	if (other_netdev) {
1030		other_port = netdev_priv(other_netdev);
1031		new_size += 1 << (other_port->rxq_order + 1);
1032		netdev_dbg(other_netdev, "port %d size: %d order %d\n",
1033			   other_netdev->dev_id,
1034			   (1 << (other_port->rxq_order + 1)),
1035			   other_port->rxq_order);
1036	}
1037
1038	new_order = min(15, ilog2(new_size - 1) + 1);
1039	dev_dbg(geth->dev, "set shared queue to size %d order %d\n",
1040		new_size, new_order);
1041	if (geth->freeq_order == new_order)
1042		return 0;
1043
1044	spin_lock_irqsave(&geth->irq_lock, flags);
1045
1046	/* Disable the software queue IRQs */
1047	en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1048	en &= ~SWFQ_EMPTY_INT_BIT;
1049	writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1050	spin_unlock_irqrestore(&geth->irq_lock, flags);
1051
1052	/* Drop the old queue */
1053	if (geth->freeq_ring)
1054		geth_cleanup_freeq(geth);
1055
1056	/* Allocate a new queue with the desired order */
1057	geth->freeq_order = new_order;
1058	ret = geth_setup_freeq(geth);
1059
1060	/* Restart the interrupts - NOTE if this is the first resize
1061	 * after probe(), this is where the interrupts get turned on
1062	 * in the first place.
1063	 */
1064	spin_lock_irqsave(&geth->irq_lock, flags);
1065	en |= SWFQ_EMPTY_INT_BIT;
1066	writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1067	spin_unlock_irqrestore(&geth->irq_lock, flags);
1068
1069	return ret;
1070}
1071
1072static void gmac_tx_irq_enable(struct net_device *netdev,
1073			       unsigned int txq, int en)
1074{
1075	struct gemini_ethernet_port *port = netdev_priv(netdev);
1076	struct gemini_ethernet *geth = port->geth;
1077	u32 val, mask;
1078
1079	netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
1080
1081	mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
1082
1083	if (en)
1084		writel(mask, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1085
1086	val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1087	val = en ? val | mask : val & ~mask;
1088	writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1089}
1090
1091static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
1092{
1093	struct netdev_queue *ntxq = netdev_get_tx_queue(netdev, txq_num);
1094
1095	gmac_tx_irq_enable(netdev, txq_num, 0);
1096	netif_tx_wake_queue(ntxq);
1097}
1098
1099static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb,
1100			    struct gmac_txq *txq, unsigned short *desc)
1101{
1102	struct gemini_ethernet_port *port = netdev_priv(netdev);
1103	struct skb_shared_info *skb_si =  skb_shinfo(skb);
1104	unsigned short m = (1 << port->txq_order) - 1;
1105	short frag, last_frag = skb_si->nr_frags - 1;
1106	struct gemini_ethernet *geth = port->geth;
1107	unsigned int word1, word3, buflen;
1108	unsigned short w = *desc;
1109	struct gmac_txdesc *txd;
1110	skb_frag_t *skb_frag;
1111	dma_addr_t mapping;
1112	unsigned short mtu;
1113	void *buffer;
1114
1115	mtu  = ETH_HLEN;
1116	mtu += netdev->mtu;
1117	if (skb->protocol == htons(ETH_P_8021Q))
1118		mtu += VLAN_HLEN;
1119
1120	word1 = skb->len;
1121	word3 = SOF_BIT;
1122
1123	if (word1 > mtu) {
1124		word1 |= TSS_MTU_ENABLE_BIT;
1125		word3 |= mtu;
1126	}
1127
1128	if (skb->ip_summed != CHECKSUM_NONE) {
1129		int tcp = 0;
1130
1131		if (skb->protocol == htons(ETH_P_IP)) {
1132			word1 |= TSS_IP_CHKSUM_BIT;
1133			tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
1134		} else { /* IPv6 */
1135			word1 |= TSS_IPV6_ENABLE_BIT;
1136			tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
1137		}
1138
1139		word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
1140	}
1141
1142	frag = -1;
1143	while (frag <= last_frag) {
1144		if (frag == -1) {
1145			buffer = skb->data;
1146			buflen = skb_headlen(skb);
1147		} else {
1148			skb_frag = skb_si->frags + frag;
1149			buffer = page_address(skb_frag_page(skb_frag)) +
1150				 skb_frag->page_offset;
1151			buflen = skb_frag->size;
1152		}
1153
1154		if (frag == last_frag) {
1155			word3 |= EOF_BIT;
1156			txq->skb[w] = skb;
1157		}
1158
1159		mapping = dma_map_single(geth->dev, buffer, buflen,
1160					 DMA_TO_DEVICE);
1161		if (dma_mapping_error(geth->dev, mapping))
1162			goto map_error;
1163
1164		txd = txq->ring + w;
1165		txd->word0.bits32 = buflen;
1166		txd->word1.bits32 = word1;
1167		txd->word2.buf_adr = mapping;
1168		txd->word3.bits32 = word3;
1169
1170		word3 &= MTU_SIZE_BIT_MASK;
1171		w++;
1172		w &= m;
1173		frag++;
1174	}
1175
1176	*desc = w;
1177	return 0;
1178
1179map_error:
1180	while (w != *desc) {
1181		w--;
1182		w &= m;
1183
1184		dma_unmap_page(geth->dev, txq->ring[w].word2.buf_adr,
1185			       txq->ring[w].word0.bits.buffer_size,
1186			       DMA_TO_DEVICE);
1187	}
1188	return -ENOMEM;
1189}
1190
1191static int gmac_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1192{
1193	struct gemini_ethernet_port *port = netdev_priv(netdev);
1194	unsigned short m = (1 << port->txq_order) - 1;
1195	struct netdev_queue *ntxq;
1196	unsigned short r, w, d;
1197	void __iomem *ptr_reg;
1198	struct gmac_txq *txq;
1199	int txq_num, nfrags;
1200	union dma_rwptr rw;
1201
1202	SKB_FRAG_ASSERT(skb);
1203
1204	if (skb->len >= 0x10000)
1205		goto out_drop_free;
1206
1207	txq_num = skb_get_queue_mapping(skb);
1208	ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE_PTR_REG(txq_num);
1209	txq = &port->txq[txq_num];
1210	ntxq = netdev_get_tx_queue(netdev, txq_num);
1211	nfrags = skb_shinfo(skb)->nr_frags;
1212
1213	rw.bits32 = readl(ptr_reg);
1214	r = rw.bits.rptr;
1215	w = rw.bits.wptr;
1216
1217	d = txq->cptr - w - 1;
1218	d &= m;
1219
1220	if (d < nfrags + 2) {
1221		gmac_clean_txq(netdev, txq, r);
1222		d = txq->cptr - w - 1;
1223		d &= m;
1224
1225		if (d < nfrags + 2) {
1226			netif_tx_stop_queue(ntxq);
1227
1228			d = txq->cptr + nfrags + 16;
1229			d &= m;
1230			txq->ring[d].word3.bits.eofie = 1;
1231			gmac_tx_irq_enable(netdev, txq_num, 1);
1232
1233			u64_stats_update_begin(&port->tx_stats_syncp);
1234			netdev->stats.tx_fifo_errors++;
1235			u64_stats_update_end(&port->tx_stats_syncp);
1236			return NETDEV_TX_BUSY;
1237		}
1238	}
1239
1240	if (gmac_map_tx_bufs(netdev, skb, txq, &w)) {
1241		if (skb_linearize(skb))
1242			goto out_drop;
1243
1244		u64_stats_update_begin(&port->tx_stats_syncp);
1245		port->tx_frags_linearized++;
1246		u64_stats_update_end(&port->tx_stats_syncp);
1247
1248		if (gmac_map_tx_bufs(netdev, skb, txq, &w))
1249			goto out_drop_free;
1250	}
1251
1252	writew(w, ptr_reg + 2);
1253
1254	gmac_clean_txq(netdev, txq, r);
1255	return NETDEV_TX_OK;
1256
1257out_drop_free:
1258	dev_kfree_skb(skb);
1259out_drop:
1260	u64_stats_update_begin(&port->tx_stats_syncp);
1261	port->stats.tx_dropped++;
1262	u64_stats_update_end(&port->tx_stats_syncp);
1263	return NETDEV_TX_OK;
1264}
1265
1266static void gmac_tx_timeout(struct net_device *netdev)
1267{
1268	netdev_err(netdev, "Tx timeout\n");
1269	gmac_dump_dma_state(netdev);
1270}
1271
1272static void gmac_enable_irq(struct net_device *netdev, int enable)
1273{
1274	struct gemini_ethernet_port *port = netdev_priv(netdev);
1275	struct gemini_ethernet *geth = port->geth;
1276	unsigned long flags;
1277	u32 val, mask;
1278
1279	netdev_info(netdev, "%s device %d %s\n", __func__,
1280		    netdev->dev_id, enable ? "enable" : "disable");
1281	spin_lock_irqsave(&geth->irq_lock, flags);
1282
1283	mask = GMAC0_IRQ0_2 << (netdev->dev_id * 2);
1284	val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1285	val = enable ? (val | mask) : (val & ~mask);
1286	writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1287
1288	mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1289	val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1290	val = enable ? (val | mask) : (val & ~mask);
1291	writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1292
1293	mask = GMAC0_IRQ4_8 << (netdev->dev_id * 8);
1294	val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1295	val = enable ? (val | mask) : (val & ~mask);
1296	writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1297
1298	spin_unlock_irqrestore(&geth->irq_lock, flags);
1299}
1300
1301static void gmac_enable_rx_irq(struct net_device *netdev, int enable)
1302{
1303	struct gemini_ethernet_port *port = netdev_priv(netdev);
1304	struct gemini_ethernet *geth = port->geth;
1305	unsigned long flags;
1306	u32 val, mask;
1307
1308	netdev_dbg(netdev, "%s device %d %s\n", __func__, netdev->dev_id,
1309		   enable ? "enable" : "disable");
1310	spin_lock_irqsave(&geth->irq_lock, flags);
1311	mask = DEFAULT_Q0_INT_BIT << netdev->dev_id;
1312
1313	val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1314	val = enable ? (val | mask) : (val & ~mask);
1315	writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1316
1317	spin_unlock_irqrestore(&geth->irq_lock, flags);
1318}
1319
1320static struct sk_buff *gmac_skb_if_good_frame(struct gemini_ethernet_port *port,
1321					      union gmac_rxdesc_0 word0,
1322					      unsigned int frame_len)
1323{
1324	unsigned int rx_csum = word0.bits.chksum_status;
1325	unsigned int rx_status = word0.bits.status;
1326	struct sk_buff *skb = NULL;
1327
1328	port->rx_stats[rx_status]++;
1329	port->rx_csum_stats[rx_csum]++;
1330
1331	if (word0.bits.derr || word0.bits.perr ||
1332	    rx_status || frame_len < ETH_ZLEN ||
1333	    rx_csum >= RX_CHKSUM_IP_ERR_UNKNOWN) {
1334		port->stats.rx_errors++;
1335
1336		if (frame_len < ETH_ZLEN || RX_ERROR_LENGTH(rx_status))
1337			port->stats.rx_length_errors++;
1338		if (RX_ERROR_OVER(rx_status))
1339			port->stats.rx_over_errors++;
1340		if (RX_ERROR_CRC(rx_status))
1341			port->stats.rx_crc_errors++;
1342		if (RX_ERROR_FRAME(rx_status))
1343			port->stats.rx_frame_errors++;
1344		return NULL;
1345	}
1346
1347	skb = napi_get_frags(&port->napi);
1348	if (!skb)
1349		goto update_exit;
1350
1351	if (rx_csum == RX_CHKSUM_IP_UDP_TCP_OK)
1352		skb->ip_summed = CHECKSUM_UNNECESSARY;
1353
1354update_exit:
1355	port->stats.rx_bytes += frame_len;
1356	port->stats.rx_packets++;
1357	return skb;
1358}
1359
1360static unsigned int gmac_rx(struct net_device *netdev, unsigned int budget)
1361{
1362	struct gemini_ethernet_port *port = netdev_priv(netdev);
1363	unsigned short m = (1 << port->rxq_order) - 1;
1364	struct gemini_ethernet *geth = port->geth;
1365	void __iomem *ptr_reg = port->rxq_rwptr;
1366	unsigned int frame_len, frag_len;
1367	struct gmac_rxdesc *rx = NULL;
1368	struct gmac_queue_page *gpage;
1369	static struct sk_buff *skb;
1370	union gmac_rxdesc_0 word0;
1371	union gmac_rxdesc_1 word1;
1372	union gmac_rxdesc_3 word3;
1373	struct page *page = NULL;
1374	unsigned int page_offs;
1375	unsigned short r, w;
1376	union dma_rwptr rw;
1377	dma_addr_t mapping;
1378	int frag_nr = 0;
1379
1380	rw.bits32 = readl(ptr_reg);
1381	/* Reset interrupt as all packages until here are taken into account */
1382	writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
1383	       geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1384	r = rw.bits.rptr;
1385	w = rw.bits.wptr;
1386
1387	while (budget && w != r) {
1388		rx = port->rxq_ring + r;
1389		word0 = rx->word0;
1390		word1 = rx->word1;
1391		mapping = rx->word2.buf_adr;
1392		word3 = rx->word3;
1393
1394		r++;
1395		r &= m;
1396
1397		frag_len = word0.bits.buffer_size;
1398		frame_len = word1.bits.byte_count;
1399		page_offs = mapping & ~PAGE_MASK;
1400
1401		if (!mapping) {
1402			netdev_err(netdev,
1403				   "rxq[%u]: HW BUG: zero DMA desc\n", r);
1404			goto err_drop;
1405		}
1406
1407		/* Freeq pointers are one page off */
1408		gpage = gmac_get_queue_page(geth, port, mapping + PAGE_SIZE);
1409		if (!gpage) {
1410			dev_err(geth->dev, "could not find mapping\n");
1411			continue;
1412		}
1413		page = gpage->page;
1414
1415		if (word3.bits32 & SOF_BIT) {
1416			if (skb) {
1417				napi_free_frags(&port->napi);
1418				port->stats.rx_dropped++;
1419			}
1420
1421			skb = gmac_skb_if_good_frame(port, word0, frame_len);
1422			if (!skb)
1423				goto err_drop;
1424
1425			page_offs += NET_IP_ALIGN;
1426			frag_len -= NET_IP_ALIGN;
1427			frag_nr = 0;
1428
1429		} else if (!skb) {
1430			put_page(page);
1431			continue;
1432		}
1433
1434		if (word3.bits32 & EOF_BIT)
1435			frag_len = frame_len - skb->len;
1436
1437		/* append page frag to skb */
1438		if (frag_nr == MAX_SKB_FRAGS)
1439			goto err_drop;
1440
1441		if (frag_len == 0)
1442			netdev_err(netdev, "Received fragment with len = 0\n");
1443
1444		skb_fill_page_desc(skb, frag_nr, page, page_offs, frag_len);
1445		skb->len += frag_len;
1446		skb->data_len += frag_len;
1447		skb->truesize += frag_len;
1448		frag_nr++;
1449
1450		if (word3.bits32 & EOF_BIT) {
1451			napi_gro_frags(&port->napi);
1452			skb = NULL;
1453			--budget;
1454		}
1455		continue;
1456
1457err_drop:
1458		if (skb) {
1459			napi_free_frags(&port->napi);
1460			skb = NULL;
1461		}
1462
1463		if (mapping)
1464			put_page(page);
1465
1466		port->stats.rx_dropped++;
1467	}
1468
1469	writew(r, ptr_reg);
1470	return budget;
1471}
1472
1473static int gmac_napi_poll(struct napi_struct *napi, int budget)
1474{
1475	struct gemini_ethernet_port *port = netdev_priv(napi->dev);
1476	struct gemini_ethernet *geth = port->geth;
1477	unsigned int freeq_threshold;
1478	unsigned int received;
1479
1480	freeq_threshold = 1 << (geth->freeq_order - 1);
1481	u64_stats_update_begin(&port->rx_stats_syncp);
1482
1483	received = gmac_rx(napi->dev, budget);
1484	if (received < budget) {
1485		napi_gro_flush(napi, false);
1486		napi_complete_done(napi, received);
1487		gmac_enable_rx_irq(napi->dev, 1);
1488		++port->rx_napi_exits;
1489	}
1490
1491	port->freeq_refill += (budget - received);
1492	if (port->freeq_refill > freeq_threshold) {
1493		port->freeq_refill -= freeq_threshold;
1494		geth_fill_freeq(geth, true);
1495	}
1496
1497	u64_stats_update_end(&port->rx_stats_syncp);
1498	return received;
1499}
1500
1501static void gmac_dump_dma_state(struct net_device *netdev)
1502{
1503	struct gemini_ethernet_port *port = netdev_priv(netdev);
1504	struct gemini_ethernet *geth = port->geth;
1505	void __iomem *ptr_reg;
1506	u32 reg[5];
1507
1508	/* Interrupt status */
1509	reg[0] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
1510	reg[1] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
1511	reg[2] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
1512	reg[3] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
1513	reg[4] = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1514	netdev_err(netdev, "IRQ status: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1515		   reg[0], reg[1], reg[2], reg[3], reg[4]);
1516
1517	/* Interrupt enable */
1518	reg[0] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
1519	reg[1] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
1520	reg[2] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
1521	reg[3] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
1522	reg[4] = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
1523	netdev_err(netdev, "IRQ enable: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
1524		   reg[0], reg[1], reg[2], reg[3], reg[4]);
1525
1526	/* RX DMA status */
1527	reg[0] = readl(port->dma_base + GMAC_DMA_RX_FIRST_DESC_REG);
1528	reg[1] = readl(port->dma_base + GMAC_DMA_RX_CURR_DESC_REG);
1529	reg[2] = GET_RPTR(port->rxq_rwptr);
1530	reg[3] = GET_WPTR(port->rxq_rwptr);
1531	netdev_err(netdev, "RX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1532		   reg[0], reg[1], reg[2], reg[3]);
1533
1534	reg[0] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD0_REG);
1535	reg[1] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD1_REG);
1536	reg[2] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD2_REG);
1537	reg[3] = readl(port->dma_base + GMAC_DMA_RX_DESC_WORD3_REG);
1538	netdev_err(netdev, "RX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1539		   reg[0], reg[1], reg[2], reg[3]);
1540
1541	/* TX DMA status */
1542	ptr_reg = port->dma_base + GMAC_SW_TX_QUEUE0_PTR_REG;
1543
1544	reg[0] = readl(port->dma_base + GMAC_DMA_TX_FIRST_DESC_REG);
1545	reg[1] = readl(port->dma_base + GMAC_DMA_TX_CURR_DESC_REG);
1546	reg[2] = GET_RPTR(ptr_reg);
1547	reg[3] = GET_WPTR(ptr_reg);
1548	netdev_err(netdev, "TX DMA regs: 0x%08x 0x%08x, ptr: %u %u\n",
1549		   reg[0], reg[1], reg[2], reg[3]);
1550
1551	reg[0] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD0_REG);
1552	reg[1] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD1_REG);
1553	reg[2] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD2_REG);
1554	reg[3] = readl(port->dma_base + GMAC_DMA_TX_DESC_WORD3_REG);
1555	netdev_err(netdev, "TX DMA descriptor: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1556		   reg[0], reg[1], reg[2], reg[3]);
1557
1558	/* FREE queues status */
1559	ptr_reg = geth->base + GLOBAL_SWFQ_RWPTR_REG;
1560
1561	reg[0] = GET_RPTR(ptr_reg);
1562	reg[1] = GET_WPTR(ptr_reg);
1563
1564	ptr_reg = geth->base + GLOBAL_HWFQ_RWPTR_REG;
1565
1566	reg[2] = GET_RPTR(ptr_reg);
1567	reg[3] = GET_WPTR(ptr_reg);
1568	netdev_err(netdev, "FQ SW ptr: %u %u, HW ptr: %u %u\n",
1569		   reg[0], reg[1], reg[2], reg[3]);
1570}
1571
1572static void gmac_update_hw_stats(struct net_device *netdev)
1573{
1574	struct gemini_ethernet_port *port = netdev_priv(netdev);
1575	unsigned int rx_discards, rx_mcast, rx_bcast;
1576	struct gemini_ethernet *geth = port->geth;
1577	unsigned long flags;
1578
1579	spin_lock_irqsave(&geth->irq_lock, flags);
1580	u64_stats_update_begin(&port->ir_stats_syncp);
1581
1582	rx_discards = readl(port->gmac_base + GMAC_IN_DISCARDS);
1583	port->hw_stats[0] += rx_discards;
1584	port->hw_stats[1] += readl(port->gmac_base + GMAC_IN_ERRORS);
1585	rx_mcast = readl(port->gmac_base + GMAC_IN_MCAST);
1586	port->hw_stats[2] += rx_mcast;
1587	rx_bcast = readl(port->gmac_base + GMAC_IN_BCAST);
1588	port->hw_stats[3] += rx_bcast;
1589	port->hw_stats[4] += readl(port->gmac_base + GMAC_IN_MAC1);
1590	port->hw_stats[5] += readl(port->gmac_base + GMAC_IN_MAC2);
1591
1592	port->stats.rx_missed_errors += rx_discards;
1593	port->stats.multicast += rx_mcast;
1594	port->stats.multicast += rx_bcast;
1595
1596	writel(GMAC0_MIB_INT_BIT << (netdev->dev_id * 8),
1597	       geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1598
1599	u64_stats_update_end(&port->ir_stats_syncp);
1600	spin_unlock_irqrestore(&geth->irq_lock, flags);
1601}
1602
1603/**
1604 * gmac_get_intr_flags() - get interrupt status flags for a port from
1605 * @netdev: the net device for the port to get flags from
1606 * @i: the interrupt status register 0..4
1607 */
1608static u32 gmac_get_intr_flags(struct net_device *netdev, int i)
1609{
1610	struct gemini_ethernet_port *port = netdev_priv(netdev);
1611	struct gemini_ethernet *geth = port->geth;
1612	void __iomem *irqif_reg, *irqen_reg;
1613	unsigned int offs, val;
1614
1615	/* Calculate the offset using the stride of the status registers */
1616	offs = i * (GLOBAL_INTERRUPT_STATUS_1_REG -
1617		    GLOBAL_INTERRUPT_STATUS_0_REG);
1618
1619	irqif_reg = geth->base + GLOBAL_INTERRUPT_STATUS_0_REG + offs;
1620	irqen_reg = geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG + offs;
1621
1622	val = readl(irqif_reg) & readl(irqen_reg);
1623	return val;
1624}
1625
1626static enum hrtimer_restart gmac_coalesce_delay_expired(struct hrtimer *timer)
1627{
1628	struct gemini_ethernet_port *port =
1629		container_of(timer, struct gemini_ethernet_port,
1630			     rx_coalesce_timer);
1631
1632	napi_schedule(&port->napi);
1633	return HRTIMER_NORESTART;
1634}
1635
1636static irqreturn_t gmac_irq(int irq, void *data)
1637{
1638	struct gemini_ethernet_port *port;
1639	struct net_device *netdev = data;
1640	struct gemini_ethernet *geth;
1641	u32 val, orr = 0;
1642
1643	port = netdev_priv(netdev);
1644	geth = port->geth;
1645
1646	val = gmac_get_intr_flags(netdev, 0);
1647	orr |= val;
1648
1649	if (val & (GMAC0_IRQ0_2 << (netdev->dev_id * 2))) {
1650		/* Oh, crap */
1651		netdev_err(netdev, "hw failure/sw bug\n");
1652		gmac_dump_dma_state(netdev);
1653
1654		/* don't know how to recover, just reduce losses */
1655		gmac_enable_irq(netdev, 0);
1656		return IRQ_HANDLED;
1657	}
1658
1659	if (val & (GMAC0_IRQ0_TXQ0_INTS << (netdev->dev_id * 6)))
1660		gmac_tx_irq(netdev, 0);
1661
1662	val = gmac_get_intr_flags(netdev, 1);
1663	orr |= val;
1664
1665	if (val & (DEFAULT_Q0_INT_BIT << netdev->dev_id)) {
1666		gmac_enable_rx_irq(netdev, 0);
1667
1668		if (!port->rx_coalesce_nsecs) {
1669			napi_schedule(&port->napi);
1670		} else {
1671			ktime_t ktime;
1672
1673			ktime = ktime_set(0, port->rx_coalesce_nsecs);
1674			hrtimer_start(&port->rx_coalesce_timer, ktime,
1675				      HRTIMER_MODE_REL);
1676		}
1677	}
1678
1679	val = gmac_get_intr_flags(netdev, 4);
1680	orr |= val;
1681
1682	if (val & (GMAC0_MIB_INT_BIT << (netdev->dev_id * 8)))
1683		gmac_update_hw_stats(netdev);
1684
1685	if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
1686		writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
1687		       geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
1688
1689		spin_lock(&geth->irq_lock);
1690		u64_stats_update_begin(&port->ir_stats_syncp);
1691		++port->stats.rx_fifo_errors;
1692		u64_stats_update_end(&port->ir_stats_syncp);
1693		spin_unlock(&geth->irq_lock);
1694	}
1695
1696	return orr ? IRQ_HANDLED : IRQ_NONE;
1697}
1698
1699static void gmac_start_dma(struct gemini_ethernet_port *port)
1700{
1701	void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1702	union gmac_dma_ctrl dma_ctrl;
1703
1704	dma_ctrl.bits32 = readl(dma_ctrl_reg);
1705	dma_ctrl.bits.rd_enable = 1;
1706	dma_ctrl.bits.td_enable = 1;
1707	dma_ctrl.bits.loopback = 0;
1708	dma_ctrl.bits.drop_small_ack = 0;
1709	dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
1710	dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
1711	dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
1712	dma_ctrl.bits.rd_bus = HSIZE_8;
1713	dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
1714	dma_ctrl.bits.td_burst_size = HBURST_INCR8;
1715	dma_ctrl.bits.td_bus = HSIZE_8;
1716
1717	writel(dma_ctrl.bits32, dma_ctrl_reg);
1718}
1719
1720static void gmac_stop_dma(struct gemini_ethernet_port *port)
1721{
1722	void __iomem *dma_ctrl_reg = port->dma_base + GMAC_DMA_CTRL_REG;
1723	union gmac_dma_ctrl dma_ctrl;
1724
1725	dma_ctrl.bits32 = readl(dma_ctrl_reg);
1726	dma_ctrl.bits.rd_enable = 0;
1727	dma_ctrl.bits.td_enable = 0;
1728	writel(dma_ctrl.bits32, dma_ctrl_reg);
1729}
1730
1731static int gmac_open(struct net_device *netdev)
1732{
1733	struct gemini_ethernet_port *port = netdev_priv(netdev);
1734	int err;
1735
1736	if (!netdev->phydev) {
1737		err = gmac_setup_phy(netdev);
1738		if (err) {
1739			netif_err(port, ifup, netdev,
1740				  "PHY init failed: %d\n", err);
1741			return err;
1742		}
1743	}
1744
1745	err = request_irq(netdev->irq, gmac_irq,
1746			  IRQF_SHARED, netdev->name, netdev);
1747	if (err) {
1748		netdev_err(netdev, "no IRQ\n");
1749		return err;
1750	}
1751
1752	netif_carrier_off(netdev);
1753	phy_start(netdev->phydev);
1754
1755	err = geth_resize_freeq(port);
1756	if (err) {
 
 
 
1757		netdev_err(netdev, "could not resize freeq\n");
1758		goto err_stop_phy;
1759	}
1760
1761	err = gmac_setup_rxq(netdev);
1762	if (err) {
1763		netdev_err(netdev, "could not setup RXQ\n");
1764		goto err_stop_phy;
1765	}
1766
1767	err = gmac_setup_txqs(netdev);
1768	if (err) {
1769		netdev_err(netdev, "could not setup TXQs\n");
1770		gmac_cleanup_rxq(netdev);
1771		goto err_stop_phy;
1772	}
1773
1774	napi_enable(&port->napi);
1775
1776	gmac_start_dma(port);
1777	gmac_enable_irq(netdev, 1);
1778	gmac_enable_tx_rx(netdev);
1779	netif_tx_start_all_queues(netdev);
1780
1781	hrtimer_init(&port->rx_coalesce_timer, CLOCK_MONOTONIC,
1782		     HRTIMER_MODE_REL);
1783	port->rx_coalesce_timer.function = &gmac_coalesce_delay_expired;
1784
1785	netdev_info(netdev, "opened\n");
1786
1787	return 0;
1788
1789err_stop_phy:
1790	phy_stop(netdev->phydev);
1791	free_irq(netdev->irq, netdev);
1792	return err;
1793}
1794
1795static int gmac_stop(struct net_device *netdev)
1796{
1797	struct gemini_ethernet_port *port = netdev_priv(netdev);
1798
1799	hrtimer_cancel(&port->rx_coalesce_timer);
1800	netif_tx_stop_all_queues(netdev);
1801	gmac_disable_tx_rx(netdev);
1802	gmac_stop_dma(port);
1803	napi_disable(&port->napi);
1804
1805	gmac_enable_irq(netdev, 0);
1806	gmac_cleanup_rxq(netdev);
1807	gmac_cleanup_txqs(netdev);
1808
1809	phy_stop(netdev->phydev);
1810	free_irq(netdev->irq, netdev);
1811
1812	gmac_update_hw_stats(netdev);
1813	return 0;
1814}
1815
1816static void gmac_set_rx_mode(struct net_device *netdev)
1817{
1818	struct gemini_ethernet_port *port = netdev_priv(netdev);
1819	union gmac_rx_fltr filter = { .bits = {
1820		.broadcast = 1,
1821		.multicast = 1,
1822		.unicast = 1,
1823	} };
1824	struct netdev_hw_addr *ha;
1825	unsigned int bit_nr;
1826	u32 mc_filter[2];
1827
1828	mc_filter[1] = 0;
1829	mc_filter[0] = 0;
1830
1831	if (netdev->flags & IFF_PROMISC) {
1832		filter.bits.error = 1;
1833		filter.bits.promiscuous = 1;
1834		mc_filter[1] = ~0;
1835		mc_filter[0] = ~0;
1836	} else if (netdev->flags & IFF_ALLMULTI) {
1837		mc_filter[1] = ~0;
1838		mc_filter[0] = ~0;
1839	} else {
1840		netdev_for_each_mc_addr(ha, netdev) {
1841			bit_nr = ~crc32_le(~0, ha->addr, ETH_ALEN) & 0x3f;
1842			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 0x1f);
1843		}
1844	}
1845
1846	writel(mc_filter[0], port->gmac_base + GMAC_MCAST_FIL0);
1847	writel(mc_filter[1], port->gmac_base + GMAC_MCAST_FIL1);
1848	writel(filter.bits32, port->gmac_base + GMAC_RX_FLTR);
1849}
1850
1851static void gmac_write_mac_address(struct net_device *netdev)
1852{
1853	struct gemini_ethernet_port *port = netdev_priv(netdev);
1854	__le32 addr[3];
1855
1856	memset(addr, 0, sizeof(addr));
1857	memcpy(addr, netdev->dev_addr, ETH_ALEN);
1858
1859	writel(le32_to_cpu(addr[0]), port->gmac_base + GMAC_STA_ADD0);
1860	writel(le32_to_cpu(addr[1]), port->gmac_base + GMAC_STA_ADD1);
1861	writel(le32_to_cpu(addr[2]), port->gmac_base + GMAC_STA_ADD2);
1862}
1863
1864static int gmac_set_mac_address(struct net_device *netdev, void *addr)
1865{
1866	struct sockaddr *sa = addr;
1867
1868	memcpy(netdev->dev_addr, sa->sa_data, ETH_ALEN);
1869	gmac_write_mac_address(netdev);
1870
1871	return 0;
1872}
1873
1874static void gmac_clear_hw_stats(struct net_device *netdev)
1875{
1876	struct gemini_ethernet_port *port = netdev_priv(netdev);
1877
1878	readl(port->gmac_base + GMAC_IN_DISCARDS);
1879	readl(port->gmac_base + GMAC_IN_ERRORS);
1880	readl(port->gmac_base + GMAC_IN_MCAST);
1881	readl(port->gmac_base + GMAC_IN_BCAST);
1882	readl(port->gmac_base + GMAC_IN_MAC1);
1883	readl(port->gmac_base + GMAC_IN_MAC2);
1884}
1885
1886static void gmac_get_stats64(struct net_device *netdev,
1887			     struct rtnl_link_stats64 *stats)
1888{
1889	struct gemini_ethernet_port *port = netdev_priv(netdev);
1890	unsigned int start;
1891
1892	gmac_update_hw_stats(netdev);
1893
1894	/* Racing with RX NAPI */
1895	do {
1896		start = u64_stats_fetch_begin(&port->rx_stats_syncp);
1897
1898		stats->rx_packets = port->stats.rx_packets;
1899		stats->rx_bytes = port->stats.rx_bytes;
1900		stats->rx_errors = port->stats.rx_errors;
1901		stats->rx_dropped = port->stats.rx_dropped;
1902
1903		stats->rx_length_errors = port->stats.rx_length_errors;
1904		stats->rx_over_errors = port->stats.rx_over_errors;
1905		stats->rx_crc_errors = port->stats.rx_crc_errors;
1906		stats->rx_frame_errors = port->stats.rx_frame_errors;
1907
1908	} while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
1909
1910	/* Racing with MIB and TX completion interrupts */
1911	do {
1912		start = u64_stats_fetch_begin(&port->ir_stats_syncp);
1913
1914		stats->tx_errors = port->stats.tx_errors;
1915		stats->tx_packets = port->stats.tx_packets;
1916		stats->tx_bytes = port->stats.tx_bytes;
1917
1918		stats->multicast = port->stats.multicast;
1919		stats->rx_missed_errors = port->stats.rx_missed_errors;
1920		stats->rx_fifo_errors = port->stats.rx_fifo_errors;
1921
1922	} while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
1923
1924	/* Racing with hard_start_xmit */
1925	do {
1926		start = u64_stats_fetch_begin(&port->tx_stats_syncp);
1927
1928		stats->tx_dropped = port->stats.tx_dropped;
1929
1930	} while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
1931
1932	stats->rx_dropped += stats->rx_missed_errors;
1933}
1934
1935static int gmac_change_mtu(struct net_device *netdev, int new_mtu)
1936{
1937	int max_len = gmac_pick_rx_max_len(new_mtu);
1938
1939	if (max_len < 0)
1940		return -EINVAL;
1941
1942	gmac_disable_tx_rx(netdev);
1943
1944	netdev->mtu = new_mtu;
1945	gmac_update_config0_reg(netdev, max_len << CONFIG0_MAXLEN_SHIFT,
1946				CONFIG0_MAXLEN_MASK);
1947
1948	netdev_update_features(netdev);
1949
1950	gmac_enable_tx_rx(netdev);
1951
1952	return 0;
1953}
1954
1955static netdev_features_t gmac_fix_features(struct net_device *netdev,
1956					   netdev_features_t features)
1957{
1958	if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK)
1959		features &= ~GMAC_OFFLOAD_FEATURES;
1960
1961	return features;
1962}
1963
1964static int gmac_set_features(struct net_device *netdev,
1965			     netdev_features_t features)
1966{
1967	struct gemini_ethernet_port *port = netdev_priv(netdev);
1968	int enable = features & NETIF_F_RXCSUM;
1969	unsigned long flags;
1970	u32 reg;
1971
1972	spin_lock_irqsave(&port->config_lock, flags);
1973
1974	reg = readl(port->gmac_base + GMAC_CONFIG0);
1975	reg = enable ? reg | CONFIG0_RX_CHKSUM : reg & ~CONFIG0_RX_CHKSUM;
1976	writel(reg, port->gmac_base + GMAC_CONFIG0);
1977
1978	spin_unlock_irqrestore(&port->config_lock, flags);
1979	return 0;
1980}
1981
1982static int gmac_get_sset_count(struct net_device *netdev, int sset)
1983{
1984	return sset == ETH_SS_STATS ? GMAC_STATS_NUM : 0;
1985}
1986
1987static void gmac_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
1988{
1989	if (stringset != ETH_SS_STATS)
1990		return;
1991
1992	memcpy(data, gmac_stats_strings, sizeof(gmac_stats_strings));
1993}
1994
1995static void gmac_get_ethtool_stats(struct net_device *netdev,
1996				   struct ethtool_stats *estats, u64 *values)
1997{
1998	struct gemini_ethernet_port *port = netdev_priv(netdev);
1999	unsigned int start;
2000	u64 *p;
2001	int i;
2002
2003	gmac_update_hw_stats(netdev);
2004
2005	/* Racing with MIB interrupt */
2006	do {
2007		p = values;
2008		start = u64_stats_fetch_begin(&port->ir_stats_syncp);
2009
2010		for (i = 0; i < RX_STATS_NUM; i++)
2011			*p++ = port->hw_stats[i];
2012
2013	} while (u64_stats_fetch_retry(&port->ir_stats_syncp, start));
2014	values = p;
2015
2016	/* Racing with RX NAPI */
2017	do {
2018		p = values;
2019		start = u64_stats_fetch_begin(&port->rx_stats_syncp);
2020
2021		for (i = 0; i < RX_STATUS_NUM; i++)
2022			*p++ = port->rx_stats[i];
2023		for (i = 0; i < RX_CHKSUM_NUM; i++)
2024			*p++ = port->rx_csum_stats[i];
2025		*p++ = port->rx_napi_exits;
2026
2027	} while (u64_stats_fetch_retry(&port->rx_stats_syncp, start));
2028	values = p;
2029
2030	/* Racing with TX start_xmit */
2031	do {
2032		p = values;
2033		start = u64_stats_fetch_begin(&port->tx_stats_syncp);
2034
2035		for (i = 0; i < TX_MAX_FRAGS; i++) {
2036			*values++ = port->tx_frag_stats[i];
2037			port->tx_frag_stats[i] = 0;
2038		}
2039		*values++ = port->tx_frags_linearized;
2040		*values++ = port->tx_hw_csummed;
2041
2042	} while (u64_stats_fetch_retry(&port->tx_stats_syncp, start));
2043}
2044
2045static int gmac_get_ksettings(struct net_device *netdev,
2046			      struct ethtool_link_ksettings *cmd)
2047{
2048	if (!netdev->phydev)
2049		return -ENXIO;
2050	phy_ethtool_ksettings_get(netdev->phydev, cmd);
2051
2052	return 0;
2053}
2054
2055static int gmac_set_ksettings(struct net_device *netdev,
2056			      const struct ethtool_link_ksettings *cmd)
2057{
2058	if (!netdev->phydev)
2059		return -ENXIO;
2060	return phy_ethtool_ksettings_set(netdev->phydev, cmd);
2061}
2062
2063static int gmac_nway_reset(struct net_device *netdev)
2064{
2065	if (!netdev->phydev)
2066		return -ENXIO;
2067	return phy_start_aneg(netdev->phydev);
2068}
2069
2070static void gmac_get_pauseparam(struct net_device *netdev,
2071				struct ethtool_pauseparam *pparam)
2072{
2073	struct gemini_ethernet_port *port = netdev_priv(netdev);
2074	union gmac_config0 config0;
2075
2076	config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
2077
2078	pparam->rx_pause = config0.bits.rx_fc_en;
2079	pparam->tx_pause = config0.bits.tx_fc_en;
2080	pparam->autoneg = true;
2081}
2082
2083static void gmac_get_ringparam(struct net_device *netdev,
2084			       struct ethtool_ringparam *rp)
2085{
2086	struct gemini_ethernet_port *port = netdev_priv(netdev);
2087	union gmac_config0 config0;
2088
2089	config0.bits32 = readl(port->gmac_base + GMAC_CONFIG0);
2090
2091	rp->rx_max_pending = 1 << 15;
2092	rp->rx_mini_max_pending = 0;
2093	rp->rx_jumbo_max_pending = 0;
2094	rp->tx_max_pending = 1 << 15;
2095
2096	rp->rx_pending = 1 << port->rxq_order;
2097	rp->rx_mini_pending = 0;
2098	rp->rx_jumbo_pending = 0;
2099	rp->tx_pending = 1 << port->txq_order;
2100}
2101
2102static int gmac_set_ringparam(struct net_device *netdev,
2103			      struct ethtool_ringparam *rp)
2104{
2105	struct gemini_ethernet_port *port = netdev_priv(netdev);
2106	int err = 0;
2107
2108	if (netif_running(netdev))
2109		return -EBUSY;
2110
2111	if (rp->rx_pending) {
2112		port->rxq_order = min(15, ilog2(rp->rx_pending - 1) + 1);
2113		err = geth_resize_freeq(port);
2114	}
2115	if (rp->tx_pending) {
2116		port->txq_order = min(15, ilog2(rp->tx_pending - 1) + 1);
2117		port->irq_every_tx_packets = 1 << (port->txq_order - 2);
2118	}
2119
2120	return err;
2121}
2122
2123static int gmac_get_coalesce(struct net_device *netdev,
2124			     struct ethtool_coalesce *ecmd)
2125{
2126	struct gemini_ethernet_port *port = netdev_priv(netdev);
2127
2128	ecmd->rx_max_coalesced_frames = 1;
2129	ecmd->tx_max_coalesced_frames = port->irq_every_tx_packets;
2130	ecmd->rx_coalesce_usecs = port->rx_coalesce_nsecs / 1000;
2131
2132	return 0;
2133}
2134
2135static int gmac_set_coalesce(struct net_device *netdev,
2136			     struct ethtool_coalesce *ecmd)
2137{
2138	struct gemini_ethernet_port *port = netdev_priv(netdev);
2139
2140	if (ecmd->tx_max_coalesced_frames < 1)
2141		return -EINVAL;
2142	if (ecmd->tx_max_coalesced_frames >= 1 << port->txq_order)
2143		return -EINVAL;
2144
2145	port->irq_every_tx_packets = ecmd->tx_max_coalesced_frames;
2146	port->rx_coalesce_nsecs = ecmd->rx_coalesce_usecs * 1000;
2147
2148	return 0;
2149}
2150
2151static u32 gmac_get_msglevel(struct net_device *netdev)
2152{
2153	struct gemini_ethernet_port *port = netdev_priv(netdev);
2154
2155	return port->msg_enable;
2156}
2157
2158static void gmac_set_msglevel(struct net_device *netdev, u32 level)
2159{
2160	struct gemini_ethernet_port *port = netdev_priv(netdev);
2161
2162	port->msg_enable = level;
2163}
2164
2165static void gmac_get_drvinfo(struct net_device *netdev,
2166			     struct ethtool_drvinfo *info)
2167{
2168	strcpy(info->driver,  DRV_NAME);
2169	strcpy(info->version, DRV_VERSION);
2170	strcpy(info->bus_info, netdev->dev_id ? "1" : "0");
2171}
2172
2173static const struct net_device_ops gmac_351x_ops = {
2174	.ndo_init		= gmac_init,
2175	.ndo_uninit		= gmac_uninit,
2176	.ndo_open		= gmac_open,
2177	.ndo_stop		= gmac_stop,
2178	.ndo_start_xmit		= gmac_start_xmit,
2179	.ndo_tx_timeout		= gmac_tx_timeout,
2180	.ndo_set_rx_mode	= gmac_set_rx_mode,
2181	.ndo_set_mac_address	= gmac_set_mac_address,
2182	.ndo_get_stats64	= gmac_get_stats64,
2183	.ndo_change_mtu		= gmac_change_mtu,
2184	.ndo_fix_features	= gmac_fix_features,
2185	.ndo_set_features	= gmac_set_features,
2186};
2187
2188static const struct ethtool_ops gmac_351x_ethtool_ops = {
2189	.get_sset_count	= gmac_get_sset_count,
2190	.get_strings	= gmac_get_strings,
2191	.get_ethtool_stats = gmac_get_ethtool_stats,
2192	.get_link	= ethtool_op_get_link,
2193	.get_link_ksettings = gmac_get_ksettings,
2194	.set_link_ksettings = gmac_set_ksettings,
2195	.nway_reset	= gmac_nway_reset,
2196	.get_pauseparam	= gmac_get_pauseparam,
2197	.get_ringparam	= gmac_get_ringparam,
2198	.set_ringparam	= gmac_set_ringparam,
2199	.get_coalesce	= gmac_get_coalesce,
2200	.set_coalesce	= gmac_set_coalesce,
2201	.get_msglevel	= gmac_get_msglevel,
2202	.set_msglevel	= gmac_set_msglevel,
2203	.get_drvinfo	= gmac_get_drvinfo,
2204};
2205
2206static irqreturn_t gemini_port_irq_thread(int irq, void *data)
2207{
2208	unsigned long irqmask = SWFQ_EMPTY_INT_BIT;
2209	struct gemini_ethernet_port *port = data;
2210	struct gemini_ethernet *geth;
2211	unsigned long flags;
2212
2213	geth = port->geth;
2214	/* The queue is half empty so refill it */
2215	geth_fill_freeq(geth, true);
2216
2217	spin_lock_irqsave(&geth->irq_lock, flags);
2218	/* ACK queue interrupt */
2219	writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2220	/* Enable queue interrupt again */
2221	irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2222	writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2223	spin_unlock_irqrestore(&geth->irq_lock, flags);
2224
2225	return IRQ_HANDLED;
2226}
2227
2228static irqreturn_t gemini_port_irq(int irq, void *data)
2229{
2230	struct gemini_ethernet_port *port = data;
2231	struct gemini_ethernet *geth;
2232	irqreturn_t ret = IRQ_NONE;
2233	u32 val, en;
2234
2235	geth = port->geth;
2236	spin_lock(&geth->irq_lock);
2237
2238	val = readl(geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2239	en = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2240
2241	if (val & en & SWFQ_EMPTY_INT_BIT) {
2242		/* Disable the queue empty interrupt while we work on
2243		 * processing the queue. Also disable overrun interrupts
2244		 * as there is not much we can do about it here.
2245		 */
2246		en &= ~(SWFQ_EMPTY_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT
2247					   | GMAC1_RX_OVERRUN_INT_BIT);
2248		writel(en, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2249		ret = IRQ_WAKE_THREAD;
2250	}
2251
2252	spin_unlock(&geth->irq_lock);
2253
2254	return ret;
2255}
2256
2257static void gemini_port_remove(struct gemini_ethernet_port *port)
2258{
2259	if (port->netdev)
2260		unregister_netdev(port->netdev);
2261	clk_disable_unprepare(port->pclk);
2262	geth_cleanup_freeq(port->geth);
2263}
2264
2265static void gemini_ethernet_init(struct gemini_ethernet *geth)
2266{
 
 
 
 
 
 
 
 
2267	writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
2268	writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_1_REG);
2269	writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_2_REG);
2270	writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_3_REG);
2271	writel(0, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG);
2272
2273	/* Interrupt config:
2274	 *
2275	 *	GMAC0 intr bits ------> int0 ----> eth0
2276	 *	GMAC1 intr bits ------> int1 ----> eth1
2277	 *	TOE intr -------------> int1 ----> eth1
2278	 *	Classification Intr --> int0 ----> eth0
2279	 *	Default Q0 -----------> int0 ----> eth0
2280	 *	Default Q1 -----------> int1 ----> eth1
2281	 *	FreeQ intr -----------> int1 ----> eth1
2282	 */
2283	writel(0xCCFC0FC0, geth->base + GLOBAL_INTERRUPT_SELECT_0_REG);
2284	writel(0x00F00002, geth->base + GLOBAL_INTERRUPT_SELECT_1_REG);
2285	writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_2_REG);
2286	writel(0xFFFFFFFF, geth->base + GLOBAL_INTERRUPT_SELECT_3_REG);
2287	writel(0xFF000003, geth->base + GLOBAL_INTERRUPT_SELECT_4_REG);
2288
2289	/* edge-triggered interrupts packed to level-triggered one... */
2290	writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_0_REG);
2291	writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
2292	writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_2_REG);
2293	writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_3_REG);
2294	writel(~0, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
2295
2296	/* Set up queue */
2297	writel(0, geth->base + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
2298	writel(0, geth->base + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
2299	writel(0, geth->base + GLOBAL_SWFQ_RWPTR_REG);
2300	writel(0, geth->base + GLOBAL_HWFQ_RWPTR_REG);
2301
2302	geth->freeq_frag_order = DEFAULT_RX_BUF_ORDER;
2303	/* This makes the queue resize on probe() so that we
2304	 * set up and enable the queue IRQ. FIXME: fragile.
2305	 */
2306	geth->freeq_order = 1;
2307}
2308
2309static void gemini_port_save_mac_addr(struct gemini_ethernet_port *port)
2310{
2311	port->mac_addr[0] =
2312		cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD0));
2313	port->mac_addr[1] =
2314		cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD1));
2315	port->mac_addr[2] =
2316		cpu_to_le32(readl(port->gmac_base + GMAC_STA_ADD2));
2317}
2318
2319static int gemini_ethernet_port_probe(struct platform_device *pdev)
2320{
2321	char *port_names[2] = { "ethernet0", "ethernet1" };
2322	struct gemini_ethernet_port *port;
2323	struct device *dev = &pdev->dev;
2324	struct gemini_ethernet *geth;
2325	struct net_device *netdev;
2326	struct resource *gmacres;
2327	struct resource *dmares;
2328	struct device *parent;
2329	unsigned int id;
2330	int irq;
2331	int ret;
2332
2333	parent = dev->parent;
2334	geth = dev_get_drvdata(parent);
2335
2336	if (!strcmp(dev_name(dev), "60008000.ethernet-port"))
2337		id = 0;
2338	else if (!strcmp(dev_name(dev), "6000c000.ethernet-port"))
2339		id = 1;
2340	else
2341		return -ENODEV;
2342
2343	dev_info(dev, "probe %s ID %d\n", dev_name(dev), id);
2344
2345	netdev = alloc_etherdev_mq(sizeof(*port), TX_QUEUE_NUM);
2346	if (!netdev) {
2347		dev_err(dev, "Can't allocate ethernet device #%d\n", id);
2348		return -ENOMEM;
2349	}
2350
2351	port = netdev_priv(netdev);
2352	SET_NETDEV_DEV(netdev, dev);
2353	port->netdev = netdev;
2354	port->id = id;
2355	port->geth = geth;
2356	port->dev = dev;
 
2357
2358	/* DMA memory */
2359	dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2360	if (!dmares) {
2361		dev_err(dev, "no DMA resource\n");
2362		return -ENODEV;
2363	}
2364	port->dma_base = devm_ioremap_resource(dev, dmares);
2365	if (IS_ERR(port->dma_base))
2366		return PTR_ERR(port->dma_base);
2367
2368	/* GMAC config memory */
2369	gmacres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2370	if (!gmacres) {
2371		dev_err(dev, "no GMAC resource\n");
2372		return -ENODEV;
2373	}
2374	port->gmac_base = devm_ioremap_resource(dev, gmacres);
2375	if (IS_ERR(port->gmac_base))
2376		return PTR_ERR(port->gmac_base);
2377
2378	/* Interrupt */
2379	irq = platform_get_irq(pdev, 0);
2380	if (irq <= 0) {
2381		dev_err(dev, "no IRQ\n");
2382		return irq ? irq : -ENODEV;
2383	}
2384	port->irq = irq;
2385
2386	/* Clock the port */
2387	port->pclk = devm_clk_get(dev, "PCLK");
2388	if (IS_ERR(port->pclk)) {
2389		dev_err(dev, "no PCLK\n");
2390		return PTR_ERR(port->pclk);
2391	}
2392	ret = clk_prepare_enable(port->pclk);
2393	if (ret)
2394		return ret;
2395
2396	/* Maybe there is a nice ethernet address we should use */
2397	gemini_port_save_mac_addr(port);
2398
2399	/* Reset the port */
2400	port->reset = devm_reset_control_get_exclusive(dev, NULL);
2401	if (IS_ERR(port->reset)) {
2402		dev_err(dev, "no reset\n");
2403		return PTR_ERR(port->reset);
2404	}
2405	reset_control_reset(port->reset);
2406	usleep_range(100, 500);
2407
2408	/* Assign pointer in the main state container */
2409	if (!id)
2410		geth->port0 = port;
2411	else
2412		geth->port1 = port;
 
 
 
 
2413	platform_set_drvdata(pdev, port);
2414
2415	/* Set up and register the netdev */
2416	netdev->dev_id = port->id;
2417	netdev->irq = irq;
2418	netdev->netdev_ops = &gmac_351x_ops;
2419	netdev->ethtool_ops = &gmac_351x_ethtool_ops;
2420
2421	spin_lock_init(&port->config_lock);
2422	gmac_clear_hw_stats(netdev);
2423
2424	netdev->hw_features = GMAC_OFFLOAD_FEATURES;
2425	netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO;
 
 
 
 
 
2426
2427	port->freeq_refill = 0;
2428	netif_napi_add(netdev, &port->napi, gmac_napi_poll,
2429		       DEFAULT_NAPI_WEIGHT);
2430
2431	if (is_valid_ether_addr((void *)port->mac_addr)) {
2432		memcpy(netdev->dev_addr, port->mac_addr, ETH_ALEN);
2433	} else {
2434		dev_dbg(dev, "ethernet address 0x%08x%08x%08x invalid\n",
2435			port->mac_addr[0], port->mac_addr[1],
2436			port->mac_addr[2]);
2437		dev_info(dev, "using a random ethernet address\n");
2438		random_ether_addr(netdev->dev_addr);
2439	}
2440	gmac_write_mac_address(netdev);
2441
2442	ret = devm_request_threaded_irq(port->dev,
2443					port->irq,
2444					gemini_port_irq,
2445					gemini_port_irq_thread,
2446					IRQF_SHARED,
2447					port_names[port->id],
2448					port);
2449	if (ret)
2450		return ret;
2451
2452	ret = register_netdev(netdev);
2453	if (!ret) {
2454		netdev_info(netdev,
2455			    "irq %d, DMA @ 0x%pap, GMAC @ 0x%pap\n",
2456			    port->irq, &dmares->start,
2457			    &gmacres->start);
2458		ret = gmac_setup_phy(netdev);
2459		if (ret)
2460			netdev_info(netdev,
2461				    "PHY init failed, deferring to ifup time\n");
2462		return 0;
2463	}
2464
2465	port->netdev = NULL;
2466	free_netdev(netdev);
2467	return ret;
2468}
2469
2470static int gemini_ethernet_port_remove(struct platform_device *pdev)
2471{
2472	struct gemini_ethernet_port *port = platform_get_drvdata(pdev);
2473
2474	gemini_port_remove(port);
 
2475	return 0;
2476}
2477
2478static const struct of_device_id gemini_ethernet_port_of_match[] = {
2479	{
2480		.compatible = "cortina,gemini-ethernet-port",
2481	},
2482	{},
2483};
2484MODULE_DEVICE_TABLE(of, gemini_ethernet_port_of_match);
2485
2486static struct platform_driver gemini_ethernet_port_driver = {
2487	.driver = {
2488		.name = "gemini-ethernet-port",
2489		.of_match_table = of_match_ptr(gemini_ethernet_port_of_match),
2490	},
2491	.probe = gemini_ethernet_port_probe,
2492	.remove = gemini_ethernet_port_remove,
2493};
2494
2495static int gemini_ethernet_probe(struct platform_device *pdev)
2496{
2497	struct device *dev = &pdev->dev;
2498	struct gemini_ethernet *geth;
2499	unsigned int retry = 5;
2500	struct resource *res;
2501	u32 val;
2502
2503	/* Global registers */
2504	geth = devm_kzalloc(dev, sizeof(*geth), GFP_KERNEL);
2505	if (!geth)
2506		return -ENOMEM;
2507	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2508	if (!res)
2509		return -ENODEV;
2510	geth->base = devm_ioremap_resource(dev, res);
2511	if (IS_ERR(geth->base))
2512		return PTR_ERR(geth->base);
2513	geth->dev = dev;
2514
2515	/* Wait for ports to stabilize */
2516	do {
2517		udelay(2);
2518		val = readl(geth->base + GLOBAL_TOE_VERSION_REG);
2519		barrier();
2520	} while (!val && --retry);
2521	if (!retry) {
2522		dev_err(dev, "failed to reset ethernet\n");
2523		return -EIO;
2524	}
2525	dev_info(dev, "Ethernet device ID: 0x%03x, revision 0x%01x\n",
2526		 (val >> 4) & 0xFFFU, val & 0xFU);
2527
2528	spin_lock_init(&geth->irq_lock);
2529	spin_lock_init(&geth->freeq_lock);
2530	gemini_ethernet_init(geth);
2531
2532	/* The children will use this */
2533	platform_set_drvdata(pdev, geth);
2534
2535	/* Spawn child devices for the two ports */
2536	return devm_of_platform_populate(dev);
2537}
2538
2539static int gemini_ethernet_remove(struct platform_device *pdev)
2540{
2541	struct gemini_ethernet *geth = platform_get_drvdata(pdev);
2542
2543	gemini_ethernet_init(geth);
2544	geth_cleanup_freeq(geth);
 
2545
2546	return 0;
2547}
2548
2549static const struct of_device_id gemini_ethernet_of_match[] = {
2550	{
2551		.compatible = "cortina,gemini-ethernet",
2552	},
2553	{},
2554};
2555MODULE_DEVICE_TABLE(of, gemini_ethernet_of_match);
2556
2557static struct platform_driver gemini_ethernet_driver = {
2558	.driver = {
2559		.name = DRV_NAME,
2560		.of_match_table = of_match_ptr(gemini_ethernet_of_match),
2561	},
2562	.probe = gemini_ethernet_probe,
2563	.remove = gemini_ethernet_remove,
2564};
2565
2566static int __init gemini_ethernet_module_init(void)
2567{
2568	int ret;
2569
2570	ret = platform_driver_register(&gemini_ethernet_port_driver);
2571	if (ret)
2572		return ret;
2573
2574	ret = platform_driver_register(&gemini_ethernet_driver);
2575	if (ret) {
2576		platform_driver_unregister(&gemini_ethernet_port_driver);
2577		return ret;
2578	}
2579
2580	return 0;
2581}
2582module_init(gemini_ethernet_module_init);
2583
2584static void __exit gemini_ethernet_module_exit(void)
2585{
2586	platform_driver_unregister(&gemini_ethernet_driver);
2587	platform_driver_unregister(&gemini_ethernet_port_driver);
2588}
2589module_exit(gemini_ethernet_module_exit);
2590
2591MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
2592MODULE_DESCRIPTION("StorLink SL351x (Gemini) ethernet driver");
2593MODULE_LICENSE("GPL");
2594MODULE_ALIAS("platform:" DRV_NAME);