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1/**
2 * emac-rockchip.c - Rockchip EMAC specific glue layer
3 *
4 * Copyright (C) 2014 Romain Perier <romain.perier@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/etherdevice.h>
18#include <linux/mfd/syscon.h>
19#include <linux/module.h>
20#include <linux/of_net.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23#include <linux/regulator/consumer.h>
24
25#include "emac.h"
26
27#define DRV_NAME "rockchip_emac"
28#define DRV_VERSION "1.1"
29
30struct emac_rockchip_soc_data {
31 unsigned int grf_offset;
32 unsigned int grf_mode_offset;
33 unsigned int grf_speed_offset;
34 bool need_div_macclk;
35};
36
37struct rockchip_priv_data {
38 struct arc_emac_priv emac;
39 struct regmap *grf;
40 const struct emac_rockchip_soc_data *soc_data;
41 struct regulator *regulator;
42 struct clk *refclk;
43 struct clk *macclk;
44};
45
46static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
47{
48 struct rockchip_priv_data *emac = priv;
49 u32 speed_offset = emac->soc_data->grf_speed_offset;
50 u32 data;
51 int err = 0;
52
53 switch (speed) {
54 case 10:
55 data = (1 << (speed_offset + 16)) | (0 << speed_offset);
56 break;
57 case 100:
58 data = (1 << (speed_offset + 16)) | (1 << speed_offset);
59 break;
60 default:
61 pr_err("speed %u not supported\n", speed);
62 return;
63 }
64
65 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data);
66 if (err)
67 pr_err("unable to apply speed %u to grf (%d)\n", speed, err);
68}
69
70static const struct emac_rockchip_soc_data emac_rk3036_emac_data = {
71 .grf_offset = 0x140, .grf_mode_offset = 8,
72 .grf_speed_offset = 9, .need_div_macclk = 1,
73};
74
75static const struct emac_rockchip_soc_data emac_rk3066_emac_data = {
76 .grf_offset = 0x154, .grf_mode_offset = 0,
77 .grf_speed_offset = 1, .need_div_macclk = 0,
78};
79
80static const struct emac_rockchip_soc_data emac_rk3188_emac_data = {
81 .grf_offset = 0x0a4, .grf_mode_offset = 0,
82 .grf_speed_offset = 1, .need_div_macclk = 0,
83};
84
85static const struct of_device_id emac_rockchip_dt_ids[] = {
86 {
87 .compatible = "rockchip,rk3036-emac",
88 .data = &emac_rk3036_emac_data,
89 },
90 {
91 .compatible = "rockchip,rk3066-emac",
92 .data = &emac_rk3066_emac_data,
93 },
94 {
95 .compatible = "rockchip,rk3188-emac",
96 .data = &emac_rk3188_emac_data,
97 },
98 { /* Sentinel */ }
99};
100
101MODULE_DEVICE_TABLE(of, emac_rockchip_dt_ids);
102
103static int emac_rockchip_probe(struct platform_device *pdev)
104{
105 struct device *dev = &pdev->dev;
106 struct net_device *ndev;
107 struct rockchip_priv_data *priv;
108 const struct of_device_id *match;
109 u32 data;
110 int err, interface;
111
112 if (!pdev->dev.of_node)
113 return -ENODEV;
114
115 ndev = alloc_etherdev(sizeof(struct rockchip_priv_data));
116 if (!ndev)
117 return -ENOMEM;
118 platform_set_drvdata(pdev, ndev);
119 SET_NETDEV_DEV(ndev, dev);
120
121 priv = netdev_priv(ndev);
122 priv->emac.drv_name = DRV_NAME;
123 priv->emac.drv_version = DRV_VERSION;
124 priv->emac.set_mac_speed = emac_rockchip_set_mac_speed;
125
126 interface = of_get_phy_mode(dev->of_node);
127
128 /* RK3036/RK3066/RK3188 SoCs only support RMII */
129 if (interface != PHY_INTERFACE_MODE_RMII) {
130 dev_err(dev, "unsupported phy interface mode %d\n", interface);
131 err = -ENOTSUPP;
132 goto out_netdev;
133 }
134
135 priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
136 "rockchip,grf");
137 if (IS_ERR(priv->grf)) {
138 dev_err(dev, "failed to retrieve global register file (%ld)\n",
139 PTR_ERR(priv->grf));
140 err = PTR_ERR(priv->grf);
141 goto out_netdev;
142 }
143
144 match = of_match_node(emac_rockchip_dt_ids, dev->of_node);
145 priv->soc_data = match->data;
146
147 priv->emac.clk = devm_clk_get(dev, "hclk");
148 if (IS_ERR(priv->emac.clk)) {
149 dev_err(dev, "failed to retrieve host clock (%ld)\n",
150 PTR_ERR(priv->emac.clk));
151 err = PTR_ERR(priv->emac.clk);
152 goto out_netdev;
153 }
154
155 priv->refclk = devm_clk_get(dev, "macref");
156 if (IS_ERR(priv->refclk)) {
157 dev_err(dev, "failed to retrieve reference clock (%ld)\n",
158 PTR_ERR(priv->refclk));
159 err = PTR_ERR(priv->refclk);
160 goto out_netdev;
161 }
162
163 err = clk_prepare_enable(priv->refclk);
164 if (err) {
165 dev_err(dev, "failed to enable reference clock (%d)\n", err);
166 goto out_netdev;
167 }
168
169 /* Optional regulator for PHY */
170 priv->regulator = devm_regulator_get_optional(dev, "phy");
171 if (IS_ERR(priv->regulator)) {
172 if (PTR_ERR(priv->regulator) == -EPROBE_DEFER) {
173 err = -EPROBE_DEFER;
174 goto out_clk_disable;
175 }
176 dev_err(dev, "no regulator found\n");
177 priv->regulator = NULL;
178 }
179
180 if (priv->regulator) {
181 err = regulator_enable(priv->regulator);
182 if (err) {
183 dev_err(dev, "failed to enable phy-supply (%d)\n", err);
184 goto out_clk_disable;
185 }
186 }
187
188 /* Set speed 100M */
189 data = (1 << (priv->soc_data->grf_speed_offset + 16)) |
190 (1 << priv->soc_data->grf_speed_offset);
191 /* Set RMII mode */
192 data |= (1 << (priv->soc_data->grf_mode_offset + 16)) |
193 (0 << priv->soc_data->grf_mode_offset);
194
195 err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
196 if (err) {
197 dev_err(dev, "unable to apply initial settings to grf (%d)\n",
198 err);
199 goto out_regulator_disable;
200 }
201
202 /* RMII interface needs always a rate of 50MHz */
203 err = clk_set_rate(priv->refclk, 50000000);
204 if (err) {
205 dev_err(dev,
206 "failed to change reference clock rate (%d)\n", err);
207 goto out_regulator_disable;
208 }
209
210 if (priv->soc_data->need_div_macclk) {
211 priv->macclk = devm_clk_get(dev, "macclk");
212 if (IS_ERR(priv->macclk)) {
213 dev_err(dev, "failed to retrieve mac clock (%ld)\n",
214 PTR_ERR(priv->macclk));
215 err = PTR_ERR(priv->macclk);
216 goto out_regulator_disable;
217 }
218
219 err = clk_prepare_enable(priv->macclk);
220 if (err) {
221 dev_err(dev, "failed to enable mac clock (%d)\n", err);
222 goto out_regulator_disable;
223 }
224
225 /* RMII TX/RX needs always a rate of 25MHz */
226 err = clk_set_rate(priv->macclk, 25000000);
227 if (err) {
228 dev_err(dev,
229 "failed to change mac clock rate (%d)\n", err);
230 goto out_clk_disable_macclk;
231 }
232 }
233
234 err = arc_emac_probe(ndev, interface);
235 if (err) {
236 dev_err(dev, "failed to probe arc emac (%d)\n", err);
237 goto out_clk_disable_macclk;
238 }
239
240 return 0;
241
242out_clk_disable_macclk:
243 if (priv->soc_data->need_div_macclk)
244 clk_disable_unprepare(priv->macclk);
245out_regulator_disable:
246 if (priv->regulator)
247 regulator_disable(priv->regulator);
248out_clk_disable:
249 clk_disable_unprepare(priv->refclk);
250out_netdev:
251 free_netdev(ndev);
252 return err;
253}
254
255static int emac_rockchip_remove(struct platform_device *pdev)
256{
257 struct net_device *ndev = platform_get_drvdata(pdev);
258 struct rockchip_priv_data *priv = netdev_priv(ndev);
259 int err;
260
261 err = arc_emac_remove(ndev);
262
263 clk_disable_unprepare(priv->refclk);
264
265 if (priv->regulator)
266 regulator_disable(priv->regulator);
267
268 free_netdev(ndev);
269 return err;
270}
271
272static struct platform_driver emac_rockchip_driver = {
273 .probe = emac_rockchip_probe,
274 .remove = emac_rockchip_remove,
275 .driver = {
276 .name = DRV_NAME,
277 .of_match_table = emac_rockchip_dt_ids,
278 },
279};
280
281module_platform_driver(emac_rockchip_driver);
282
283MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
284MODULE_DESCRIPTION("Rockchip EMAC platform driver");
285MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/**
3 * emac-rockchip.c - Rockchip EMAC specific glue layer
4 *
5 * Copyright (C) 2014 Romain Perier <romain.perier@gmail.com>
6 */
7
8#include <linux/etherdevice.h>
9#include <linux/mfd/syscon.h>
10#include <linux/module.h>
11#include <linux/of_net.h>
12#include <linux/platform_device.h>
13#include <linux/regmap.h>
14#include <linux/regulator/consumer.h>
15
16#include "emac.h"
17
18#define DRV_NAME "rockchip_emac"
19#define DRV_VERSION "1.1"
20
21struct emac_rockchip_soc_data {
22 unsigned int grf_offset;
23 unsigned int grf_mode_offset;
24 unsigned int grf_speed_offset;
25 bool need_div_macclk;
26};
27
28struct rockchip_priv_data {
29 struct arc_emac_priv emac;
30 struct regmap *grf;
31 const struct emac_rockchip_soc_data *soc_data;
32 struct regulator *regulator;
33 struct clk *refclk;
34 struct clk *macclk;
35};
36
37static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
38{
39 struct rockchip_priv_data *emac = priv;
40 u32 speed_offset = emac->soc_data->grf_speed_offset;
41 u32 data;
42 int err = 0;
43
44 switch (speed) {
45 case 10:
46 data = (1 << (speed_offset + 16)) | (0 << speed_offset);
47 break;
48 case 100:
49 data = (1 << (speed_offset + 16)) | (1 << speed_offset);
50 break;
51 default:
52 pr_err("speed %u not supported\n", speed);
53 return;
54 }
55
56 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data);
57 if (err)
58 pr_err("unable to apply speed %u to grf (%d)\n", speed, err);
59}
60
61static const struct emac_rockchip_soc_data emac_rk3036_emac_data = {
62 .grf_offset = 0x140, .grf_mode_offset = 8,
63 .grf_speed_offset = 9, .need_div_macclk = 1,
64};
65
66static const struct emac_rockchip_soc_data emac_rk3066_emac_data = {
67 .grf_offset = 0x154, .grf_mode_offset = 0,
68 .grf_speed_offset = 1, .need_div_macclk = 0,
69};
70
71static const struct emac_rockchip_soc_data emac_rk3188_emac_data = {
72 .grf_offset = 0x0a4, .grf_mode_offset = 0,
73 .grf_speed_offset = 1, .need_div_macclk = 0,
74};
75
76static const struct of_device_id emac_rockchip_dt_ids[] = {
77 {
78 .compatible = "rockchip,rk3036-emac",
79 .data = &emac_rk3036_emac_data,
80 },
81 {
82 .compatible = "rockchip,rk3066-emac",
83 .data = &emac_rk3066_emac_data,
84 },
85 {
86 .compatible = "rockchip,rk3188-emac",
87 .data = &emac_rk3188_emac_data,
88 },
89 { /* Sentinel */ }
90};
91
92MODULE_DEVICE_TABLE(of, emac_rockchip_dt_ids);
93
94static int emac_rockchip_probe(struct platform_device *pdev)
95{
96 struct device *dev = &pdev->dev;
97 struct net_device *ndev;
98 struct rockchip_priv_data *priv;
99 const struct of_device_id *match;
100 u32 data;
101 int err, interface;
102
103 if (!pdev->dev.of_node)
104 return -ENODEV;
105
106 ndev = alloc_etherdev(sizeof(struct rockchip_priv_data));
107 if (!ndev)
108 return -ENOMEM;
109 platform_set_drvdata(pdev, ndev);
110 SET_NETDEV_DEV(ndev, dev);
111
112 priv = netdev_priv(ndev);
113 priv->emac.drv_name = DRV_NAME;
114 priv->emac.drv_version = DRV_VERSION;
115 priv->emac.set_mac_speed = emac_rockchip_set_mac_speed;
116
117 interface = of_get_phy_mode(dev->of_node);
118
119 /* RK3036/RK3066/RK3188 SoCs only support RMII */
120 if (interface != PHY_INTERFACE_MODE_RMII) {
121 dev_err(dev, "unsupported phy interface mode %d\n", interface);
122 err = -ENOTSUPP;
123 goto out_netdev;
124 }
125
126 priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
127 "rockchip,grf");
128 if (IS_ERR(priv->grf)) {
129 dev_err(dev, "failed to retrieve global register file (%ld)\n",
130 PTR_ERR(priv->grf));
131 err = PTR_ERR(priv->grf);
132 goto out_netdev;
133 }
134
135 match = of_match_node(emac_rockchip_dt_ids, dev->of_node);
136 priv->soc_data = match->data;
137
138 priv->emac.clk = devm_clk_get(dev, "hclk");
139 if (IS_ERR(priv->emac.clk)) {
140 dev_err(dev, "failed to retrieve host clock (%ld)\n",
141 PTR_ERR(priv->emac.clk));
142 err = PTR_ERR(priv->emac.clk);
143 goto out_netdev;
144 }
145
146 priv->refclk = devm_clk_get(dev, "macref");
147 if (IS_ERR(priv->refclk)) {
148 dev_err(dev, "failed to retrieve reference clock (%ld)\n",
149 PTR_ERR(priv->refclk));
150 err = PTR_ERR(priv->refclk);
151 goto out_netdev;
152 }
153
154 err = clk_prepare_enable(priv->refclk);
155 if (err) {
156 dev_err(dev, "failed to enable reference clock (%d)\n", err);
157 goto out_netdev;
158 }
159
160 /* Optional regulator for PHY */
161 priv->regulator = devm_regulator_get_optional(dev, "phy");
162 if (IS_ERR(priv->regulator)) {
163 if (PTR_ERR(priv->regulator) == -EPROBE_DEFER) {
164 err = -EPROBE_DEFER;
165 goto out_clk_disable;
166 }
167 dev_err(dev, "no regulator found\n");
168 priv->regulator = NULL;
169 }
170
171 if (priv->regulator) {
172 err = regulator_enable(priv->regulator);
173 if (err) {
174 dev_err(dev, "failed to enable phy-supply (%d)\n", err);
175 goto out_clk_disable;
176 }
177 }
178
179 /* Set speed 100M */
180 data = (1 << (priv->soc_data->grf_speed_offset + 16)) |
181 (1 << priv->soc_data->grf_speed_offset);
182 /* Set RMII mode */
183 data |= (1 << (priv->soc_data->grf_mode_offset + 16)) |
184 (0 << priv->soc_data->grf_mode_offset);
185
186 err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
187 if (err) {
188 dev_err(dev, "unable to apply initial settings to grf (%d)\n",
189 err);
190 goto out_regulator_disable;
191 }
192
193 /* RMII interface needs always a rate of 50MHz */
194 err = clk_set_rate(priv->refclk, 50000000);
195 if (err) {
196 dev_err(dev,
197 "failed to change reference clock rate (%d)\n", err);
198 goto out_regulator_disable;
199 }
200
201 if (priv->soc_data->need_div_macclk) {
202 priv->macclk = devm_clk_get(dev, "macclk");
203 if (IS_ERR(priv->macclk)) {
204 dev_err(dev, "failed to retrieve mac clock (%ld)\n",
205 PTR_ERR(priv->macclk));
206 err = PTR_ERR(priv->macclk);
207 goto out_regulator_disable;
208 }
209
210 err = clk_prepare_enable(priv->macclk);
211 if (err) {
212 dev_err(dev, "failed to enable mac clock (%d)\n", err);
213 goto out_regulator_disable;
214 }
215
216 /* RMII TX/RX needs always a rate of 25MHz */
217 err = clk_set_rate(priv->macclk, 25000000);
218 if (err) {
219 dev_err(dev,
220 "failed to change mac clock rate (%d)\n", err);
221 goto out_clk_disable_macclk;
222 }
223 }
224
225 err = arc_emac_probe(ndev, interface);
226 if (err) {
227 dev_err(dev, "failed to probe arc emac (%d)\n", err);
228 goto out_clk_disable_macclk;
229 }
230
231 return 0;
232
233out_clk_disable_macclk:
234 if (priv->soc_data->need_div_macclk)
235 clk_disable_unprepare(priv->macclk);
236out_regulator_disable:
237 if (priv->regulator)
238 regulator_disable(priv->regulator);
239out_clk_disable:
240 clk_disable_unprepare(priv->refclk);
241out_netdev:
242 free_netdev(ndev);
243 return err;
244}
245
246static int emac_rockchip_remove(struct platform_device *pdev)
247{
248 struct net_device *ndev = platform_get_drvdata(pdev);
249 struct rockchip_priv_data *priv = netdev_priv(ndev);
250 int err;
251
252 err = arc_emac_remove(ndev);
253
254 clk_disable_unprepare(priv->refclk);
255
256 if (priv->regulator)
257 regulator_disable(priv->regulator);
258
259 if (priv->soc_data->need_div_macclk)
260 clk_disable_unprepare(priv->macclk);
261
262 free_netdev(ndev);
263 return err;
264}
265
266static struct platform_driver emac_rockchip_driver = {
267 .probe = emac_rockchip_probe,
268 .remove = emac_rockchip_remove,
269 .driver = {
270 .name = DRV_NAME,
271 .of_match_table = emac_rockchip_dt_ids,
272 },
273};
274
275module_platform_driver(emac_rockchip_driver);
276
277MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
278MODULE_DESCRIPTION("Rockchip EMAC platform driver");
279MODULE_LICENSE("GPL");