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1/*
2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13#include <drm/drmP.h>
14#include <drm/drm_crtc_helper.h>
15#include <drm/drm_plane_helper.h>
16#include <drm/drm_atomic_helper.h>
17#include "armada_crtc.h"
18#include "armada_drm.h"
19#include "armada_fb.h"
20#include "armada_gem.h"
21#include "armada_hw.h"
22#include "armada_trace.h"
23
24enum csc_mode {
25 CSC_AUTO = 0,
26 CSC_YUV_CCIR601 = 1,
27 CSC_YUV_CCIR709 = 2,
28 CSC_RGB_COMPUTER = 1,
29 CSC_RGB_STUDIO = 2,
30};
31
32static const uint32_t armada_primary_formats[] = {
33 DRM_FORMAT_UYVY,
34 DRM_FORMAT_YUYV,
35 DRM_FORMAT_VYUY,
36 DRM_FORMAT_YVYU,
37 DRM_FORMAT_ARGB8888,
38 DRM_FORMAT_ABGR8888,
39 DRM_FORMAT_XRGB8888,
40 DRM_FORMAT_XBGR8888,
41 DRM_FORMAT_RGB888,
42 DRM_FORMAT_BGR888,
43 DRM_FORMAT_ARGB1555,
44 DRM_FORMAT_ABGR1555,
45 DRM_FORMAT_RGB565,
46 DRM_FORMAT_BGR565,
47};
48
49/*
50 * A note about interlacing. Let's consider HDMI 1920x1080i.
51 * The timing parameters we have from X are:
52 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
53 * 1920 2448 2492 2640 1080 1084 1094 1125
54 * Which get translated to:
55 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
56 * 1920 2448 2492 2640 540 542 547 562
57 *
58 * This is how it is defined by CEA-861-D - line and pixel numbers are
59 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
60 * line: 2640. The odd frame, the first active line is at line 21, and
61 * the even frame, the first active line is 584.
62 *
63 * LN: 560 561 562 563 567 568 569
64 * DE: ~~~|____________________________//__________________________
65 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
66 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
67 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
68 *
69 * LN: 1123 1124 1125 1 5 6 7
70 * DE: ~~~|____________________________//__________________________
71 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
72 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
73 * 23 blanking lines
74 *
75 * The Armada LCD Controller line and pixel numbers are, like X timings,
76 * referenced to the top left of the active frame.
77 *
78 * So, translating these to our LCD controller:
79 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
80 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
81 * Note: Vsync front porch remains constant!
82 *
83 * if (odd_frame) {
84 * vtotal = mode->crtc_vtotal + 1;
85 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
86 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
87 * } else {
88 * vtotal = mode->crtc_vtotal;
89 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
90 * vhorizpos = mode->crtc_hsync_start;
91 * }
92 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
93 *
94 * So, we need to reprogram these registers on each vsync event:
95 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
96 *
97 * Note: we do not use the frame done interrupts because these appear
98 * to happen too early, and lead to jitter on the display (presumably
99 * they occur at the end of the last active line, before the vsync back
100 * porch, which we're reprogramming.)
101 */
102
103void
104armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
105{
106 while (regs->offset != ~0) {
107 void __iomem *reg = dcrtc->base + regs->offset;
108 uint32_t val;
109
110 val = regs->mask;
111 if (val != 0)
112 val &= readl_relaxed(reg);
113 writel_relaxed(val | regs->val, reg);
114 ++regs;
115 }
116}
117
118#define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
119
120static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
121{
122 uint32_t dumb_ctrl;
123
124 dumb_ctrl = dcrtc->cfg_dumb_ctrl;
125
126 if (!dpms_blanked(dcrtc->dpms))
127 dumb_ctrl |= CFG_DUMB_ENA;
128
129 /*
130 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
131 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
132 * force LCD_D[23:0] to output blank color, overriding the GPIO or
133 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
134 */
135 if (dpms_blanked(dcrtc->dpms) &&
136 (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
137 dumb_ctrl &= ~DUMB_MASK;
138 dumb_ctrl |= DUMB_BLANK;
139 }
140
141 /*
142 * The documentation doesn't indicate what the normal state of
143 * the sync signals are. Sebastian Hesselbart kindly probed
144 * these signals on his board to determine their state.
145 *
146 * The non-inverted state of the sync signals is active high.
147 * Setting these bits makes the appropriate signal active low.
148 */
149 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
150 dumb_ctrl |= CFG_INV_CSYNC;
151 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
152 dumb_ctrl |= CFG_INV_HSYNC;
153 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
154 dumb_ctrl |= CFG_INV_VSYNC;
155
156 if (dcrtc->dumb_ctrl != dumb_ctrl) {
157 dcrtc->dumb_ctrl = dumb_ctrl;
158 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
159 }
160}
161
162void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb,
163 int x, int y)
164{
165 const struct drm_format_info *format = fb->format;
166 unsigned int num_planes = format->num_planes;
167 u32 addr = drm_fb_obj(fb)->dev_addr;
168 int i;
169
170 if (num_planes > 3)
171 num_planes = 3;
172
173 addrs[0] = addr + fb->offsets[0] + y * fb->pitches[0] +
174 x * format->cpp[0];
175
176 y /= format->vsub;
177 x /= format->hsub;
178
179 for (i = 1; i < num_planes; i++)
180 addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] +
181 x * format->cpp[i];
182 for (; i < 3; i++)
183 addrs[i] = 0;
184}
185
186static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
187 int x, int y, struct armada_regs *regs, bool interlaced)
188{
189 unsigned pitch = fb->pitches[0];
190 u32 addrs[3], addr_odd, addr_even;
191 unsigned i = 0;
192
193 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
194 pitch, x, y, fb->format->cpp[0] * 8);
195
196 armada_drm_plane_calc_addrs(addrs, fb, x, y);
197
198 addr_odd = addr_even = addrs[0];
199
200 if (interlaced) {
201 addr_even += pitch;
202 pitch *= 2;
203 }
204
205 /* write offset, base, and pitch */
206 armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
207 armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
208 armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
209
210 return i;
211}
212
213static void armada_drm_plane_work_call(struct armada_crtc *dcrtc,
214 struct armada_plane_work *work,
215 void (*fn)(struct armada_crtc *, struct armada_plane_work *))
216{
217 struct armada_plane *dplane = drm_to_armada_plane(work->plane);
218 struct drm_pending_vblank_event *event;
219 struct drm_framebuffer *fb;
220
221 if (fn)
222 fn(dcrtc, work);
223 drm_crtc_vblank_put(&dcrtc->crtc);
224
225 event = work->event;
226 fb = work->old_fb;
227 if (event || fb) {
228 struct drm_device *dev = dcrtc->crtc.dev;
229 unsigned long flags;
230
231 spin_lock_irqsave(&dev->event_lock, flags);
232 if (event)
233 drm_crtc_send_vblank_event(&dcrtc->crtc, event);
234 if (fb)
235 __armada_drm_queue_unref_work(dev, fb);
236 spin_unlock_irqrestore(&dev->event_lock, flags);
237 }
238
239 if (work->need_kfree)
240 kfree(work);
241
242 wake_up(&dplane->frame_wait);
243}
244
245static void armada_drm_plane_work_run(struct armada_crtc *dcrtc,
246 struct drm_plane *plane)
247{
248 struct armada_plane *dplane = drm_to_armada_plane(plane);
249 struct armada_plane_work *work = xchg(&dplane->work, NULL);
250
251 /* Handle any pending frame work. */
252 if (work)
253 armada_drm_plane_work_call(dcrtc, work, work->fn);
254}
255
256int armada_drm_plane_work_queue(struct armada_crtc *dcrtc,
257 struct armada_plane_work *work)
258{
259 struct armada_plane *plane = drm_to_armada_plane(work->plane);
260 int ret;
261
262 ret = drm_crtc_vblank_get(&dcrtc->crtc);
263 if (ret)
264 return ret;
265
266 ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0;
267 if (ret)
268 drm_crtc_vblank_put(&dcrtc->crtc);
269
270 return ret;
271}
272
273int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout)
274{
275 return wait_event_timeout(plane->frame_wait, !plane->work, timeout);
276}
277
278void armada_drm_plane_work_cancel(struct armada_crtc *dcrtc,
279 struct armada_plane *dplane)
280{
281 struct armada_plane_work *work = xchg(&dplane->work, NULL);
282
283 if (work)
284 armada_drm_plane_work_call(dcrtc, work, work->cancel);
285}
286
287static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc,
288 struct armada_plane_work *work)
289{
290 unsigned long flags;
291
292 spin_lock_irqsave(&dcrtc->irq_lock, flags);
293 armada_drm_crtc_update_regs(dcrtc, work->regs);
294 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
295}
296
297static void armada_drm_crtc_complete_disable_work(struct armada_crtc *dcrtc,
298 struct armada_plane_work *work)
299{
300 unsigned long flags;
301
302 if (dcrtc->plane == work->plane)
303 dcrtc->plane = NULL;
304
305 spin_lock_irqsave(&dcrtc->irq_lock, flags);
306 armada_drm_crtc_update_regs(dcrtc, work->regs);
307 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
308}
309
310static struct armada_plane_work *
311armada_drm_crtc_alloc_plane_work(struct drm_plane *plane)
312{
313 struct armada_plane_work *work;
314 int i = 0;
315
316 work = kzalloc(sizeof(*work), GFP_KERNEL);
317 if (!work)
318 return NULL;
319
320 work->plane = plane;
321 work->fn = armada_drm_crtc_complete_frame_work;
322 work->need_kfree = true;
323 armada_reg_queue_end(work->regs, i);
324
325 return work;
326}
327
328static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
329 struct drm_framebuffer *fb, bool force)
330{
331 struct armada_plane_work *work;
332
333 if (!fb)
334 return;
335
336 if (force) {
337 /* Display is disabled, so just drop the old fb */
338 drm_framebuffer_put(fb);
339 return;
340 }
341
342 work = armada_drm_crtc_alloc_plane_work(dcrtc->crtc.primary);
343 if (work) {
344 work->old_fb = fb;
345
346 if (armada_drm_plane_work_queue(dcrtc, work) == 0)
347 return;
348
349 kfree(work);
350 }
351
352 /*
353 * Oops - just drop the reference immediately and hope for
354 * the best. The worst that will happen is the buffer gets
355 * reused before it has finished being displayed.
356 */
357 drm_framebuffer_put(fb);
358}
359
360static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
361{
362 /*
363 * Tell the DRM core that vblank IRQs aren't going to happen for
364 * a while. This cleans up any pending vblank events for us.
365 */
366 drm_crtc_vblank_off(&dcrtc->crtc);
367 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
368}
369
370/* The mode_config.mutex will be held for this call */
371static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
372{
373 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
374
375 if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) {
376 if (dpms_blanked(dpms))
377 armada_drm_vblank_off(dcrtc);
378 else if (!IS_ERR(dcrtc->clk))
379 WARN_ON(clk_prepare_enable(dcrtc->clk));
380 dcrtc->dpms = dpms;
381 armada_drm_crtc_update(dcrtc);
382 if (!dpms_blanked(dpms))
383 drm_crtc_vblank_on(&dcrtc->crtc);
384 else if (!IS_ERR(dcrtc->clk))
385 clk_disable_unprepare(dcrtc->clk);
386 } else if (dcrtc->dpms != dpms) {
387 dcrtc->dpms = dpms;
388 }
389}
390
391/*
392 * Prepare for a mode set. Turn off overlay to ensure that we don't end
393 * up with the overlay size being bigger than the active screen size.
394 * We rely upon X refreshing this state after the mode set has completed.
395 *
396 * The mode_config.mutex will be held for this call
397 */
398static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
399{
400 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
401 struct drm_plane *plane;
402
403 /*
404 * If we have an overlay plane associated with this CRTC, disable
405 * it before the modeset to avoid its coordinates being outside
406 * the new mode parameters.
407 */
408 plane = dcrtc->plane;
409 if (plane) {
410 drm_plane_force_disable(plane);
411 WARN_ON(!armada_drm_plane_work_wait(drm_to_armada_plane(plane),
412 HZ));
413 }
414}
415
416/* The mode_config.mutex will be held for this call */
417static void armada_drm_crtc_commit(struct drm_crtc *crtc)
418{
419 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
420
421 if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
422 dcrtc->dpms = DRM_MODE_DPMS_ON;
423 armada_drm_crtc_update(dcrtc);
424 }
425}
426
427/* The mode_config.mutex will be held for this call */
428static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
429 const struct drm_display_mode *mode, struct drm_display_mode *adj)
430{
431 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
432 int ret;
433
434 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
435 if (!dcrtc->variant->has_spu_adv_reg &&
436 adj->flags & DRM_MODE_FLAG_INTERLACE)
437 return false;
438
439 /* Check whether the display mode is possible */
440 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
441 if (ret)
442 return false;
443
444 return true;
445}
446
447/* These are locked by dev->vbl_lock */
448static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
449{
450 if (dcrtc->irq_ena & mask) {
451 dcrtc->irq_ena &= ~mask;
452 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
453 }
454}
455
456static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
457{
458 if ((dcrtc->irq_ena & mask) != mask) {
459 dcrtc->irq_ena |= mask;
460 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
461 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
462 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
463 }
464}
465
466static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
467{
468 void __iomem *base = dcrtc->base;
469 struct drm_plane *ovl_plane;
470
471 if (stat & DMA_FF_UNDERFLOW)
472 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
473 if (stat & GRA_FF_UNDERFLOW)
474 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
475
476 if (stat & VSYNC_IRQ)
477 drm_crtc_handle_vblank(&dcrtc->crtc);
478
479 ovl_plane = dcrtc->plane;
480 if (ovl_plane)
481 armada_drm_plane_work_run(dcrtc, ovl_plane);
482
483 spin_lock(&dcrtc->irq_lock);
484 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
485 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
486 uint32_t val;
487
488 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
489 writel_relaxed(dcrtc->v[i].spu_v_h_total,
490 base + LCD_SPUT_V_H_TOTAL);
491
492 val = readl_relaxed(base + LCD_SPU_ADV_REG);
493 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
494 val |= dcrtc->v[i].spu_adv_reg;
495 writel_relaxed(val, base + LCD_SPU_ADV_REG);
496 }
497
498 if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
499 writel_relaxed(dcrtc->cursor_hw_pos,
500 base + LCD_SPU_HWC_OVSA_HPXL_VLN);
501 writel_relaxed(dcrtc->cursor_hw_sz,
502 base + LCD_SPU_HWC_HPXL_VLN);
503 armada_updatel(CFG_HWC_ENA,
504 CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
505 base + LCD_SPU_DMA_CTRL0);
506 dcrtc->cursor_update = false;
507 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
508 }
509
510 spin_unlock(&dcrtc->irq_lock);
511
512 if (stat & GRA_FRAME_IRQ)
513 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
514}
515
516static irqreturn_t armada_drm_irq(int irq, void *arg)
517{
518 struct armada_crtc *dcrtc = arg;
519 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
520
521 /*
522 * This is rediculous - rather than writing bits to clear, we
523 * have to set the actual status register value. This is racy.
524 */
525 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
526
527 trace_armada_drm_irq(&dcrtc->crtc, stat);
528
529 /* Mask out those interrupts we haven't enabled */
530 v = stat & dcrtc->irq_ena;
531
532 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
533 armada_drm_crtc_irq(dcrtc, stat);
534 return IRQ_HANDLED;
535 }
536 return IRQ_NONE;
537}
538
539static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
540{
541 struct drm_display_mode *adj = &dcrtc->crtc.mode;
542 uint32_t val = 0;
543
544 if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
545 val |= CFG_CSC_YUV_CCIR709;
546 if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
547 val |= CFG_CSC_RGB_STUDIO;
548
549 /*
550 * In auto mode, set the colorimetry, based upon the HDMI spec.
551 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
552 * ITU601. It may be more appropriate to set this depending on
553 * the source - but what if the graphic frame is YUV and the
554 * video frame is RGB?
555 */
556 if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
557 !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
558 (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
559 if (dcrtc->csc_yuv_mode == CSC_AUTO)
560 val |= CFG_CSC_YUV_CCIR709;
561 }
562
563 /*
564 * We assume we're connected to a TV-like device, so the YUV->RGB
565 * conversion should produce a limited range. We should set this
566 * depending on the connectors attached to this CRTC, and what
567 * kind of device they report being connected.
568 */
569 if (dcrtc->csc_rgb_mode == CSC_AUTO)
570 val |= CFG_CSC_RGB_STUDIO;
571
572 return val;
573}
574
575static void armada_drm_gra_plane_regs(struct armada_regs *regs,
576 struct drm_framebuffer *fb, struct armada_plane_state *state,
577 int x, int y, bool interlaced)
578{
579 unsigned int i;
580 u32 ctrl0;
581
582 i = armada_drm_crtc_calc_fb(fb, x, y, regs, interlaced);
583 armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN);
584 armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN);
585 armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN);
586
587 ctrl0 = state->ctrl0;
588 if (interlaced)
589 ctrl0 |= CFG_GRA_FTOGGLE;
590
591 armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT |
592 CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
593 CFG_SWAPYU | CFG_YUV2RGB) |
594 CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
595 CFG_GRA_HSMOOTH | CFG_GRA_ENA,
596 LCD_SPU_DMA_CTRL0);
597 armada_reg_queue_end(regs, i);
598}
599
600static void armada_drm_primary_set(struct drm_crtc *crtc,
601 struct drm_plane *plane, int x, int y)
602{
603 struct armada_plane_state *state = &drm_to_armada_plane(plane)->state;
604 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
605 struct armada_regs regs[8];
606 bool interlaced = dcrtc->interlaced;
607
608 armada_drm_gra_plane_regs(regs, plane->fb, state, x, y, interlaced);
609 armada_drm_crtc_update_regs(dcrtc, regs);
610}
611
612/* The mode_config.mutex will be held for this call */
613static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
614 struct drm_display_mode *mode, struct drm_display_mode *adj,
615 int x, int y, struct drm_framebuffer *old_fb)
616{
617 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
618 struct armada_regs regs[17];
619 uint32_t lm, rm, tm, bm, val, sclk;
620 unsigned long flags;
621 unsigned i;
622 bool interlaced;
623
624 drm_framebuffer_get(crtc->primary->fb);
625
626 interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
627
628 val = CFG_GRA_ENA;
629 val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
630 val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
631
632 if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
633 val |= CFG_PALETTE_ENA;
634
635 drm_to_armada_plane(crtc->primary)->state.ctrl0 = val;
636 drm_to_armada_plane(crtc->primary)->state.src_hw =
637 drm_to_armada_plane(crtc->primary)->state.dst_hw =
638 adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
639 drm_to_armada_plane(crtc->primary)->state.dst_yx = 0;
640
641 i = 0;
642 rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
643 lm = adj->crtc_htotal - adj->crtc_hsync_end;
644 bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
645 tm = adj->crtc_vtotal - adj->crtc_vsync_end;
646
647 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
648 adj->crtc_hdisplay,
649 adj->crtc_hsync_start,
650 adj->crtc_hsync_end,
651 adj->crtc_htotal, lm, rm);
652 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
653 adj->crtc_vdisplay,
654 adj->crtc_vsync_start,
655 adj->crtc_vsync_end,
656 adj->crtc_vtotal, tm, bm);
657
658 /* Wait for pending flips to complete */
659 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
660 MAX_SCHEDULE_TIMEOUT);
661
662 drm_crtc_vblank_off(crtc);
663
664 val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
665 if (val != dcrtc->dumb_ctrl) {
666 dcrtc->dumb_ctrl = val;
667 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
668 }
669
670 /*
671 * If we are blanked, we would have disabled the clock. Re-enable
672 * it so that compute_clock() does the right thing.
673 */
674 if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms))
675 WARN_ON(clk_prepare_enable(dcrtc->clk));
676
677 /* Now compute the divider for real */
678 dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
679
680 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
681
682 if (interlaced ^ dcrtc->interlaced) {
683 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
684 drm_crtc_vblank_get(&dcrtc->crtc);
685 else
686 drm_crtc_vblank_put(&dcrtc->crtc);
687 dcrtc->interlaced = interlaced;
688 }
689
690 spin_lock_irqsave(&dcrtc->irq_lock, flags);
691
692 /* Ensure graphic fifo is enabled */
693 armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
694
695 /* Even interlaced/progressive frame */
696 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
697 adj->crtc_htotal;
698 dcrtc->v[1].spu_v_porch = tm << 16 | bm;
699 val = adj->crtc_hsync_start;
700 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
701 dcrtc->variant->spu_adv_reg;
702
703 if (interlaced) {
704 /* Odd interlaced frame */
705 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
706 (1 << 16);
707 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
708 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
709 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
710 dcrtc->variant->spu_adv_reg;
711 } else {
712 dcrtc->v[0] = dcrtc->v[1];
713 }
714
715 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
716
717 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
718 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
719 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
720 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
721 LCD_SPUT_V_H_TOTAL);
722
723 if (dcrtc->variant->has_spu_adv_reg) {
724 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
725 ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
726 ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
727 }
728
729 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
730 armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
731
732 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
733 armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
734 armada_reg_queue_end(regs, i);
735
736 armada_drm_crtc_update_regs(dcrtc, regs);
737
738 armada_drm_primary_set(crtc, crtc->primary, x, y);
739 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
740
741 armada_drm_crtc_update(dcrtc);
742
743 drm_crtc_vblank_on(crtc);
744 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
745
746 return 0;
747}
748
749/* The mode_config.mutex will be held for this call */
750static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
751 struct drm_framebuffer *old_fb)
752{
753 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
754 struct armada_regs regs[4];
755 unsigned i;
756
757 i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
758 dcrtc->interlaced);
759 armada_reg_queue_end(regs, i);
760
761 /* Wait for pending flips to complete */
762 armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary),
763 MAX_SCHEDULE_TIMEOUT);
764
765 /* Take a reference to the new fb as we're using it */
766 drm_framebuffer_get(crtc->primary->fb);
767
768 /* Update the base in the CRTC */
769 armada_drm_crtc_update_regs(dcrtc, regs);
770
771 /* Drop our previously held reference */
772 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
773
774 return 0;
775}
776
777/* The mode_config.mutex will be held for this call */
778static void armada_drm_crtc_disable(struct drm_crtc *crtc)
779{
780 armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
781
782 /* Disable our primary plane when we disable the CRTC. */
783 crtc->primary->funcs->disable_plane(crtc->primary, NULL);
784}
785
786static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
787 .dpms = armada_drm_crtc_dpms,
788 .prepare = armada_drm_crtc_prepare,
789 .commit = armada_drm_crtc_commit,
790 .mode_fixup = armada_drm_crtc_mode_fixup,
791 .mode_set = armada_drm_crtc_mode_set,
792 .mode_set_base = armada_drm_crtc_mode_set_base,
793 .disable = armada_drm_crtc_disable,
794};
795
796static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
797 unsigned stride, unsigned width, unsigned height)
798{
799 uint32_t addr;
800 unsigned y;
801
802 addr = SRAM_HWC32_RAM1;
803 for (y = 0; y < height; y++) {
804 uint32_t *p = &pix[y * stride];
805 unsigned x;
806
807 for (x = 0; x < width; x++, p++) {
808 uint32_t val = *p;
809
810 val = (val & 0xff00ff00) |
811 (val & 0x000000ff) << 16 |
812 (val & 0x00ff0000) >> 16;
813
814 writel_relaxed(val,
815 base + LCD_SPU_SRAM_WRDAT);
816 writel_relaxed(addr | SRAM_WRITE,
817 base + LCD_SPU_SRAM_CTRL);
818 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
819 addr += 1;
820 if ((addr & 0x00ff) == 0)
821 addr += 0xf00;
822 if ((addr & 0x30ff) == 0)
823 addr = SRAM_HWC32_RAM2;
824 }
825 }
826}
827
828static void armada_drm_crtc_cursor_tran(void __iomem *base)
829{
830 unsigned addr;
831
832 for (addr = 0; addr < 256; addr++) {
833 /* write the default value */
834 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
835 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
836 base + LCD_SPU_SRAM_CTRL);
837 }
838}
839
840static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
841{
842 uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
843 uint32_t yoff, yscr, h = dcrtc->cursor_h;
844 uint32_t para1;
845
846 /*
847 * Calculate the visible width and height of the cursor,
848 * screen position, and the position in the cursor bitmap.
849 */
850 if (dcrtc->cursor_x < 0) {
851 xoff = -dcrtc->cursor_x;
852 xscr = 0;
853 w -= min(xoff, w);
854 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
855 xoff = 0;
856 xscr = dcrtc->cursor_x;
857 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
858 } else {
859 xoff = 0;
860 xscr = dcrtc->cursor_x;
861 }
862
863 if (dcrtc->cursor_y < 0) {
864 yoff = -dcrtc->cursor_y;
865 yscr = 0;
866 h -= min(yoff, h);
867 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
868 yoff = 0;
869 yscr = dcrtc->cursor_y;
870 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
871 } else {
872 yoff = 0;
873 yscr = dcrtc->cursor_y;
874 }
875
876 /* On interlaced modes, the vertical cursor size must be halved */
877 s = dcrtc->cursor_w;
878 if (dcrtc->interlaced) {
879 s *= 2;
880 yscr /= 2;
881 h /= 2;
882 }
883
884 if (!dcrtc->cursor_obj || !h || !w) {
885 spin_lock_irq(&dcrtc->irq_lock);
886 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
887 dcrtc->cursor_update = false;
888 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
889 spin_unlock_irq(&dcrtc->irq_lock);
890 return 0;
891 }
892
893 spin_lock_irq(&dcrtc->irq_lock);
894 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
895 armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
896 dcrtc->base + LCD_SPU_SRAM_PARA1);
897 spin_unlock_irq(&dcrtc->irq_lock);
898
899 /*
900 * Initialize the transparency if the SRAM was powered down.
901 * We must also reload the cursor data as well.
902 */
903 if (!(para1 & CFG_CSB_256x32)) {
904 armada_drm_crtc_cursor_tran(dcrtc->base);
905 reload = true;
906 }
907
908 if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
909 spin_lock_irq(&dcrtc->irq_lock);
910 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
911 dcrtc->cursor_update = false;
912 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
913 spin_unlock_irq(&dcrtc->irq_lock);
914 reload = true;
915 }
916 if (reload) {
917 struct armada_gem_object *obj = dcrtc->cursor_obj;
918 uint32_t *pix;
919 /* Set the top-left corner of the cursor image */
920 pix = obj->addr;
921 pix += yoff * s + xoff;
922 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
923 }
924
925 /* Reload the cursor position, size and enable in the IRQ handler */
926 spin_lock_irq(&dcrtc->irq_lock);
927 dcrtc->cursor_hw_pos = yscr << 16 | xscr;
928 dcrtc->cursor_hw_sz = h << 16 | w;
929 dcrtc->cursor_update = true;
930 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
931 spin_unlock_irq(&dcrtc->irq_lock);
932
933 return 0;
934}
935
936static void cursor_update(void *data)
937{
938 armada_drm_crtc_cursor_update(data, true);
939}
940
941static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
942 struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
943{
944 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
945 struct armada_gem_object *obj = NULL;
946 int ret;
947
948 /* If no cursor support, replicate drm's return value */
949 if (!dcrtc->variant->has_spu_adv_reg)
950 return -ENXIO;
951
952 if (handle && w > 0 && h > 0) {
953 /* maximum size is 64x32 or 32x64 */
954 if (w > 64 || h > 64 || (w > 32 && h > 32))
955 return -ENOMEM;
956
957 obj = armada_gem_object_lookup(file, handle);
958 if (!obj)
959 return -ENOENT;
960
961 /* Must be a kernel-mapped object */
962 if (!obj->addr) {
963 drm_gem_object_put_unlocked(&obj->obj);
964 return -EINVAL;
965 }
966
967 if (obj->obj.size < w * h * 4) {
968 DRM_ERROR("buffer is too small\n");
969 drm_gem_object_put_unlocked(&obj->obj);
970 return -ENOMEM;
971 }
972 }
973
974 if (dcrtc->cursor_obj) {
975 dcrtc->cursor_obj->update = NULL;
976 dcrtc->cursor_obj->update_data = NULL;
977 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
978 }
979 dcrtc->cursor_obj = obj;
980 dcrtc->cursor_w = w;
981 dcrtc->cursor_h = h;
982 ret = armada_drm_crtc_cursor_update(dcrtc, true);
983 if (obj) {
984 obj->update_data = dcrtc;
985 obj->update = cursor_update;
986 }
987
988 return ret;
989}
990
991static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
992{
993 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
994 int ret;
995
996 /* If no cursor support, replicate drm's return value */
997 if (!dcrtc->variant->has_spu_adv_reg)
998 return -EFAULT;
999
1000 dcrtc->cursor_x = x;
1001 dcrtc->cursor_y = y;
1002 ret = armada_drm_crtc_cursor_update(dcrtc, false);
1003
1004 return ret;
1005}
1006
1007static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
1008{
1009 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1010 struct armada_private *priv = crtc->dev->dev_private;
1011
1012 if (dcrtc->cursor_obj)
1013 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
1014
1015 priv->dcrtc[dcrtc->num] = NULL;
1016 drm_crtc_cleanup(&dcrtc->crtc);
1017
1018 if (!IS_ERR(dcrtc->clk))
1019 clk_disable_unprepare(dcrtc->clk);
1020
1021 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
1022
1023 of_node_put(dcrtc->crtc.port);
1024
1025 kfree(dcrtc);
1026}
1027
1028/*
1029 * The mode_config lock is held here, to prevent races between this
1030 * and a mode_set.
1031 */
1032static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
1033 struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags,
1034 struct drm_modeset_acquire_ctx *ctx)
1035{
1036 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1037 struct armada_plane_work *work;
1038 unsigned i;
1039 int ret;
1040
1041 /* We don't support changing the pixel format */
1042 if (fb->format != crtc->primary->fb->format)
1043 return -EINVAL;
1044
1045 work = armada_drm_crtc_alloc_plane_work(dcrtc->crtc.primary);
1046 if (!work)
1047 return -ENOMEM;
1048
1049 work->event = event;
1050 work->old_fb = dcrtc->crtc.primary->fb;
1051
1052 i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
1053 dcrtc->interlaced);
1054 armada_reg_queue_end(work->regs, i);
1055
1056 /*
1057 * Ensure that we hold a reference on the new framebuffer.
1058 * This has to match the behaviour in mode_set.
1059 */
1060 drm_framebuffer_get(fb);
1061
1062 ret = armada_drm_plane_work_queue(dcrtc, work);
1063 if (ret) {
1064 /* Undo our reference above */
1065 drm_framebuffer_put(fb);
1066 kfree(work);
1067 return ret;
1068 }
1069
1070 /*
1071 * Don't take a reference on the new framebuffer;
1072 * drm_mode_page_flip_ioctl() has already grabbed a reference and
1073 * will _not_ drop that reference on successful return from this
1074 * function. Simply mark this new framebuffer as the current one.
1075 */
1076 dcrtc->crtc.primary->fb = fb;
1077
1078 /*
1079 * Finally, if the display is blanked, we won't receive an
1080 * interrupt, so complete it now.
1081 */
1082 if (dpms_blanked(dcrtc->dpms))
1083 armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary);
1084
1085 return 0;
1086}
1087
1088static int
1089armada_drm_crtc_set_property(struct drm_crtc *crtc,
1090 struct drm_property *property, uint64_t val)
1091{
1092 struct armada_private *priv = crtc->dev->dev_private;
1093 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1094 bool update_csc = false;
1095
1096 if (property == priv->csc_yuv_prop) {
1097 dcrtc->csc_yuv_mode = val;
1098 update_csc = true;
1099 } else if (property == priv->csc_rgb_prop) {
1100 dcrtc->csc_rgb_mode = val;
1101 update_csc = true;
1102 }
1103
1104 if (update_csc) {
1105 uint32_t val;
1106
1107 val = dcrtc->spu_iopad_ctrl |
1108 armada_drm_crtc_calculate_csc(dcrtc);
1109 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1110 }
1111
1112 return 0;
1113}
1114
1115/* These are called under the vbl_lock. */
1116static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc)
1117{
1118 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1119
1120 armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA);
1121 return 0;
1122}
1123
1124static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc)
1125{
1126 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1127
1128 armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA);
1129}
1130
1131static const struct drm_crtc_funcs armada_crtc_funcs = {
1132 .cursor_set = armada_drm_crtc_cursor_set,
1133 .cursor_move = armada_drm_crtc_cursor_move,
1134 .destroy = armada_drm_crtc_destroy,
1135 .set_config = drm_crtc_helper_set_config,
1136 .page_flip = armada_drm_crtc_page_flip,
1137 .set_property = armada_drm_crtc_set_property,
1138 .enable_vblank = armada_drm_crtc_enable_vblank,
1139 .disable_vblank = armada_drm_crtc_disable_vblank,
1140};
1141
1142static void armada_drm_primary_update_state(struct drm_plane_state *state,
1143 struct armada_regs *regs)
1144{
1145 struct armada_plane *dplane = drm_to_armada_plane(state->plane);
1146 struct armada_crtc *dcrtc = drm_to_armada_crtc(state->crtc);
1147 struct armada_framebuffer *dfb = drm_fb_to_armada_fb(state->fb);
1148 bool was_disabled;
1149 unsigned int idx = 0;
1150 u32 val;
1151
1152 val = CFG_GRA_FMT(dfb->fmt) | CFG_GRA_MOD(dfb->mod);
1153 if (dfb->fmt > CFG_420)
1154 val |= CFG_PALETTE_ENA;
1155 if (state->visible)
1156 val |= CFG_GRA_ENA;
1157 if (drm_rect_width(&state->src) >> 16 != drm_rect_width(&state->dst))
1158 val |= CFG_GRA_HSMOOTH;
1159
1160 was_disabled = !(dplane->state.ctrl0 & CFG_GRA_ENA);
1161 if (was_disabled)
1162 armada_reg_queue_mod(regs, idx,
1163 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
1164
1165 dplane->state.ctrl0 = val;
1166 dplane->state.src_hw = (drm_rect_height(&state->src) & 0xffff0000) |
1167 drm_rect_width(&state->src) >> 16;
1168 dplane->state.dst_hw = drm_rect_height(&state->dst) << 16 |
1169 drm_rect_width(&state->dst);
1170 dplane->state.dst_yx = state->dst.y1 << 16 | state->dst.x1;
1171
1172 armada_drm_gra_plane_regs(regs + idx, &dfb->fb, &dplane->state,
1173 state->src.x1 >> 16, state->src.y1 >> 16,
1174 dcrtc->interlaced);
1175
1176 dplane->state.vsync_update = !was_disabled;
1177 dplane->state.changed = true;
1178}
1179
1180static int armada_drm_primary_update(struct drm_plane *plane,
1181 struct drm_crtc *crtc, struct drm_framebuffer *fb,
1182 int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h,
1183 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h,
1184 struct drm_modeset_acquire_ctx *ctx)
1185{
1186 struct armada_plane *dplane = drm_to_armada_plane(plane);
1187 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
1188 struct armada_plane_work *work;
1189 struct drm_plane_state state = {
1190 .plane = plane,
1191 .crtc = crtc,
1192 .fb = fb,
1193 .src_x = src_x,
1194 .src_y = src_y,
1195 .src_w = src_w,
1196 .src_h = src_h,
1197 .crtc_x = crtc_x,
1198 .crtc_y = crtc_y,
1199 .crtc_w = crtc_w,
1200 .crtc_h = crtc_h,
1201 .rotation = DRM_MODE_ROTATE_0,
1202 };
1203 struct drm_crtc_state crtc_state = {
1204 .crtc = crtc,
1205 .enable = crtc->enabled,
1206 .mode = crtc->mode,
1207 };
1208 int ret;
1209
1210 ret = drm_atomic_helper_check_plane_state(&state, &crtc_state, 0,
1211 INT_MAX, true, false);
1212 if (ret)
1213 return ret;
1214
1215 work = &dplane->works[dplane->next_work];
1216 work->fn = armada_drm_crtc_complete_frame_work;
1217
1218 if (plane->fb != fb) {
1219 /*
1220 * Take a reference on the new framebuffer - we want to
1221 * hold on to it while the hardware is displaying it.
1222 */
1223 drm_framebuffer_reference(fb);
1224
1225 work->old_fb = plane->fb;
1226 } else {
1227 work->old_fb = NULL;
1228 }
1229
1230 armada_drm_primary_update_state(&state, work->regs);
1231
1232 if (!dplane->state.changed)
1233 return 0;
1234
1235 /* Wait for pending work to complete */
1236 if (armada_drm_plane_work_wait(dplane, HZ / 10) == 0)
1237 armada_drm_plane_work_cancel(dcrtc, dplane);
1238
1239 if (!dplane->state.vsync_update) {
1240 work->fn(dcrtc, work);
1241 if (work->old_fb)
1242 drm_framebuffer_unreference(work->old_fb);
1243 return 0;
1244 }
1245
1246 /* Queue it for update on the next interrupt if we are enabled */
1247 ret = armada_drm_plane_work_queue(dcrtc, work);
1248 if (ret) {
1249 work->fn(dcrtc, work);
1250 if (work->old_fb)
1251 drm_framebuffer_unreference(work->old_fb);
1252 }
1253
1254 dplane->next_work = !dplane->next_work;
1255
1256 return 0;
1257}
1258
1259int armada_drm_plane_disable(struct drm_plane *plane,
1260 struct drm_modeset_acquire_ctx *ctx)
1261{
1262 struct armada_plane *dplane = drm_to_armada_plane(plane);
1263 struct armada_crtc *dcrtc;
1264 struct armada_plane_work *work;
1265 unsigned int idx = 0;
1266 u32 sram_para1, enable_mask;
1267
1268 if (!plane->crtc)
1269 return 0;
1270
1271 /*
1272 * Arrange to power down most RAMs and FIFOs if this is the primary
1273 * plane, otherwise just the YUV FIFOs for the overlay plane.
1274 */
1275 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
1276 sram_para1 = CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1277 CFG_PDWN32x32 | CFG_PDWN64x66;
1278 enable_mask = CFG_GRA_ENA;
1279 } else {
1280 sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
1281 enable_mask = CFG_DMA_ENA;
1282 }
1283
1284 dplane->state.ctrl0 &= ~enable_mask;
1285
1286 dcrtc = drm_to_armada_crtc(plane->crtc);
1287
1288 /*
1289 * Try to disable the plane and drop our ref on the framebuffer
1290 * at the next frame update. If we fail for any reason, disable
1291 * the plane immediately.
1292 */
1293 work = &dplane->works[dplane->next_work];
1294 work->fn = armada_drm_crtc_complete_disable_work;
1295 work->cancel = armada_drm_crtc_complete_disable_work;
1296 work->old_fb = plane->fb;
1297
1298 armada_reg_queue_mod(work->regs, idx,
1299 0, enable_mask, LCD_SPU_DMA_CTRL0);
1300 armada_reg_queue_mod(work->regs, idx,
1301 sram_para1, 0, LCD_SPU_SRAM_PARA1);
1302 armada_reg_queue_end(work->regs, idx);
1303
1304 /* Wait for any preceding work to complete, but don't wedge */
1305 if (WARN_ON(!armada_drm_plane_work_wait(dplane, HZ)))
1306 armada_drm_plane_work_cancel(dcrtc, dplane);
1307
1308 if (armada_drm_plane_work_queue(dcrtc, work)) {
1309 work->fn(dcrtc, work);
1310 if (work->old_fb)
1311 drm_framebuffer_unreference(work->old_fb);
1312 }
1313
1314 dplane->next_work = !dplane->next_work;
1315
1316 return 0;
1317}
1318
1319static const struct drm_plane_funcs armada_primary_plane_funcs = {
1320 .update_plane = armada_drm_primary_update,
1321 .disable_plane = armada_drm_plane_disable,
1322 .destroy = drm_primary_helper_destroy,
1323};
1324
1325int armada_drm_plane_init(struct armada_plane *plane)
1326{
1327 unsigned int i;
1328
1329 for (i = 0; i < ARRAY_SIZE(plane->works); i++)
1330 plane->works[i].plane = &plane->base;
1331
1332 init_waitqueue_head(&plane->frame_wait);
1333
1334 return 0;
1335}
1336
1337static const struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1338 { CSC_AUTO, "Auto" },
1339 { CSC_YUV_CCIR601, "CCIR601" },
1340 { CSC_YUV_CCIR709, "CCIR709" },
1341};
1342
1343static const struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1344 { CSC_AUTO, "Auto" },
1345 { CSC_RGB_COMPUTER, "Computer system" },
1346 { CSC_RGB_STUDIO, "Studio" },
1347};
1348
1349static int armada_drm_crtc_create_properties(struct drm_device *dev)
1350{
1351 struct armada_private *priv = dev->dev_private;
1352
1353 if (priv->csc_yuv_prop)
1354 return 0;
1355
1356 priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1357 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1358 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1359 priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1360 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1361 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1362
1363 if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1364 return -ENOMEM;
1365
1366 return 0;
1367}
1368
1369static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1370 struct resource *res, int irq, const struct armada_variant *variant,
1371 struct device_node *port)
1372{
1373 struct armada_private *priv = drm->dev_private;
1374 struct armada_crtc *dcrtc;
1375 struct armada_plane *primary;
1376 void __iomem *base;
1377 int ret;
1378
1379 ret = armada_drm_crtc_create_properties(drm);
1380 if (ret)
1381 return ret;
1382
1383 base = devm_ioremap_resource(dev, res);
1384 if (IS_ERR(base))
1385 return PTR_ERR(base);
1386
1387 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1388 if (!dcrtc) {
1389 DRM_ERROR("failed to allocate Armada crtc\n");
1390 return -ENOMEM;
1391 }
1392
1393 if (dev != drm->dev)
1394 dev_set_drvdata(dev, dcrtc);
1395
1396 dcrtc->variant = variant;
1397 dcrtc->base = base;
1398 dcrtc->num = drm->mode_config.num_crtc;
1399 dcrtc->clk = ERR_PTR(-EINVAL);
1400 dcrtc->csc_yuv_mode = CSC_AUTO;
1401 dcrtc->csc_rgb_mode = CSC_AUTO;
1402 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1403 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1404 spin_lock_init(&dcrtc->irq_lock);
1405 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1406
1407 /* Initialize some registers which we don't otherwise set */
1408 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1409 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1410 writel_relaxed(dcrtc->spu_iopad_ctrl,
1411 dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1412 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1413 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1414 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1415 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1416 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1417 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1418 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1419
1420 ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1421 dcrtc);
1422 if (ret < 0)
1423 goto err_crtc;
1424
1425 if (dcrtc->variant->init) {
1426 ret = dcrtc->variant->init(dcrtc, dev);
1427 if (ret)
1428 goto err_crtc;
1429 }
1430
1431 /* Ensure AXI pipeline is enabled */
1432 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1433
1434 priv->dcrtc[dcrtc->num] = dcrtc;
1435
1436 dcrtc->crtc.port = port;
1437
1438 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
1439 if (!primary) {
1440 ret = -ENOMEM;
1441 goto err_crtc;
1442 }
1443
1444 ret = armada_drm_plane_init(primary);
1445 if (ret) {
1446 kfree(primary);
1447 goto err_crtc;
1448 }
1449
1450 ret = drm_universal_plane_init(drm, &primary->base, 0,
1451 &armada_primary_plane_funcs,
1452 armada_primary_formats,
1453 ARRAY_SIZE(armada_primary_formats),
1454 NULL,
1455 DRM_PLANE_TYPE_PRIMARY, NULL);
1456 if (ret) {
1457 kfree(primary);
1458 goto err_crtc;
1459 }
1460
1461 ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL,
1462 &armada_crtc_funcs, NULL);
1463 if (ret)
1464 goto err_crtc_init;
1465
1466 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1467
1468 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1469 dcrtc->csc_yuv_mode);
1470 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1471 dcrtc->csc_rgb_mode);
1472
1473 return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1474
1475err_crtc_init:
1476 primary->base.funcs->destroy(&primary->base);
1477err_crtc:
1478 kfree(dcrtc);
1479
1480 return ret;
1481}
1482
1483static int
1484armada_lcd_bind(struct device *dev, struct device *master, void *data)
1485{
1486 struct platform_device *pdev = to_platform_device(dev);
1487 struct drm_device *drm = data;
1488 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1489 int irq = platform_get_irq(pdev, 0);
1490 const struct armada_variant *variant;
1491 struct device_node *port = NULL;
1492
1493 if (irq < 0)
1494 return irq;
1495
1496 if (!dev->of_node) {
1497 const struct platform_device_id *id;
1498
1499 id = platform_get_device_id(pdev);
1500 if (!id)
1501 return -ENXIO;
1502
1503 variant = (const struct armada_variant *)id->driver_data;
1504 } else {
1505 const struct of_device_id *match;
1506 struct device_node *np, *parent = dev->of_node;
1507
1508 match = of_match_device(dev->driver->of_match_table, dev);
1509 if (!match)
1510 return -ENXIO;
1511
1512 np = of_get_child_by_name(parent, "ports");
1513 if (np)
1514 parent = np;
1515 port = of_get_child_by_name(parent, "port");
1516 of_node_put(np);
1517 if (!port) {
1518 dev_err(dev, "no port node found in %pOF\n", parent);
1519 return -ENXIO;
1520 }
1521
1522 variant = match->data;
1523 }
1524
1525 return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1526}
1527
1528static void
1529armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1530{
1531 struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1532
1533 armada_drm_crtc_destroy(&dcrtc->crtc);
1534}
1535
1536static const struct component_ops armada_lcd_ops = {
1537 .bind = armada_lcd_bind,
1538 .unbind = armada_lcd_unbind,
1539};
1540
1541static int armada_lcd_probe(struct platform_device *pdev)
1542{
1543 return component_add(&pdev->dev, &armada_lcd_ops);
1544}
1545
1546static int armada_lcd_remove(struct platform_device *pdev)
1547{
1548 component_del(&pdev->dev, &armada_lcd_ops);
1549 return 0;
1550}
1551
1552static const struct of_device_id armada_lcd_of_match[] = {
1553 {
1554 .compatible = "marvell,dove-lcd",
1555 .data = &armada510_ops,
1556 },
1557 {}
1558};
1559MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1560
1561static const struct platform_device_id armada_lcd_platform_ids[] = {
1562 {
1563 .name = "armada-lcd",
1564 .driver_data = (unsigned long)&armada510_ops,
1565 }, {
1566 .name = "armada-510-lcd",
1567 .driver_data = (unsigned long)&armada510_ops,
1568 },
1569 { },
1570};
1571MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1572
1573struct platform_driver armada_lcd_platform_driver = {
1574 .probe = armada_lcd_probe,
1575 .remove = armada_lcd_remove,
1576 .driver = {
1577 .name = "armada-lcd",
1578 .owner = THIS_MODULE,
1579 .of_match_table = armada_lcd_of_match,
1580 },
1581 .id_table = armada_lcd_platform_ids,
1582};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Russell King
4 * Rewritten from the dovefb driver, and Armada510 manuals.
5 */
6
7#include <linux/clk.h>
8#include <linux/component.h>
9#include <linux/module.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12
13#include <drm/drm_atomic.h>
14#include <drm/drm_atomic_helper.h>
15#include <drm/drm_plane_helper.h>
16#include <drm/drm_probe_helper.h>
17#include <drm/drm_vblank.h>
18
19#include "armada_crtc.h"
20#include "armada_drm.h"
21#include "armada_fb.h"
22#include "armada_gem.h"
23#include "armada_hw.h"
24#include "armada_plane.h"
25#include "armada_trace.h"
26
27/*
28 * A note about interlacing. Let's consider HDMI 1920x1080i.
29 * The timing parameters we have from X are:
30 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
31 * 1920 2448 2492 2640 1080 1084 1094 1125
32 * Which get translated to:
33 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
34 * 1920 2448 2492 2640 540 542 547 562
35 *
36 * This is how it is defined by CEA-861-D - line and pixel numbers are
37 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
38 * line: 2640. The odd frame, the first active line is at line 21, and
39 * the even frame, the first active line is 584.
40 *
41 * LN: 560 561 562 563 567 568 569
42 * DE: ~~~|____________________________//__________________________
43 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
44 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
45 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
46 *
47 * LN: 1123 1124 1125 1 5 6 7
48 * DE: ~~~|____________________________//__________________________
49 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
50 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
51 * 23 blanking lines
52 *
53 * The Armada LCD Controller line and pixel numbers are, like X timings,
54 * referenced to the top left of the active frame.
55 *
56 * So, translating these to our LCD controller:
57 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
58 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
59 * Note: Vsync front porch remains constant!
60 *
61 * if (odd_frame) {
62 * vtotal = mode->crtc_vtotal + 1;
63 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
64 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
65 * } else {
66 * vtotal = mode->crtc_vtotal;
67 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
68 * vhorizpos = mode->crtc_hsync_start;
69 * }
70 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
71 *
72 * So, we need to reprogram these registers on each vsync event:
73 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
74 *
75 * Note: we do not use the frame done interrupts because these appear
76 * to happen too early, and lead to jitter on the display (presumably
77 * they occur at the end of the last active line, before the vsync back
78 * porch, which we're reprogramming.)
79 */
80
81void
82armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
83{
84 while (regs->offset != ~0) {
85 void __iomem *reg = dcrtc->base + regs->offset;
86 uint32_t val;
87
88 val = regs->mask;
89 if (val != 0)
90 val &= readl_relaxed(reg);
91 writel_relaxed(val | regs->val, reg);
92 ++regs;
93 }
94}
95
96static void armada_drm_crtc_update(struct armada_crtc *dcrtc, bool enable)
97{
98 uint32_t dumb_ctrl;
99
100 dumb_ctrl = dcrtc->cfg_dumb_ctrl;
101
102 if (enable)
103 dumb_ctrl |= CFG_DUMB_ENA;
104
105 /*
106 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
107 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
108 * force LCD_D[23:0] to output blank color, overriding the GPIO or
109 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
110 */
111 if (!enable && (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
112 dumb_ctrl &= ~DUMB_MASK;
113 dumb_ctrl |= DUMB_BLANK;
114 }
115
116 armada_updatel(dumb_ctrl,
117 ~(CFG_INV_CSYNC | CFG_INV_HSYNC | CFG_INV_VSYNC),
118 dcrtc->base + LCD_SPU_DUMB_CTRL);
119}
120
121static void armada_drm_crtc_queue_state_event(struct drm_crtc *crtc)
122{
123 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
124 struct drm_pending_vblank_event *event;
125
126 /* If we have an event, we need vblank events enabled */
127 event = xchg(&crtc->state->event, NULL);
128 if (event) {
129 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
130 dcrtc->event = event;
131 }
132}
133
134static void armada_drm_update_gamma(struct drm_crtc *crtc)
135{
136 struct drm_property_blob *blob = crtc->state->gamma_lut;
137 void __iomem *base = drm_to_armada_crtc(crtc)->base;
138 int i;
139
140 if (blob) {
141 struct drm_color_lut *lut = blob->data;
142
143 armada_updatel(CFG_CSB_256x8, CFG_CSB_256x8 | CFG_PDWN256x8,
144 base + LCD_SPU_SRAM_PARA1);
145
146 for (i = 0; i < 256; i++) {
147 writel_relaxed(drm_color_lut_extract(lut[i].red, 8),
148 base + LCD_SPU_SRAM_WRDAT);
149 writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_YR,
150 base + LCD_SPU_SRAM_CTRL);
151 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
152 writel_relaxed(drm_color_lut_extract(lut[i].green, 8),
153 base + LCD_SPU_SRAM_WRDAT);
154 writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_UG,
155 base + LCD_SPU_SRAM_CTRL);
156 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
157 writel_relaxed(drm_color_lut_extract(lut[i].blue, 8),
158 base + LCD_SPU_SRAM_WRDAT);
159 writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_VB,
160 base + LCD_SPU_SRAM_CTRL);
161 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
162 }
163 armada_updatel(CFG_GAMMA_ENA, CFG_GAMMA_ENA,
164 base + LCD_SPU_DMA_CTRL0);
165 } else {
166 armada_updatel(0, CFG_GAMMA_ENA, base + LCD_SPU_DMA_CTRL0);
167 armada_updatel(CFG_PDWN256x8, CFG_CSB_256x8 | CFG_PDWN256x8,
168 base + LCD_SPU_SRAM_PARA1);
169 }
170}
171
172static enum drm_mode_status armada_drm_crtc_mode_valid(struct drm_crtc *crtc,
173 const struct drm_display_mode *mode)
174{
175 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
176
177 if (mode->vscan > 1)
178 return MODE_NO_VSCAN;
179
180 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
181 return MODE_NO_DBLESCAN;
182
183 if (mode->flags & DRM_MODE_FLAG_HSKEW)
184 return MODE_H_ILLEGAL;
185
186 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
187 if (!dcrtc->variant->has_spu_adv_reg &&
188 mode->flags & DRM_MODE_FLAG_INTERLACE)
189 return MODE_NO_INTERLACE;
190
191 if (mode->flags & (DRM_MODE_FLAG_BCAST | DRM_MODE_FLAG_PIXMUX |
192 DRM_MODE_FLAG_CLKDIV2))
193 return MODE_BAD;
194
195 return MODE_OK;
196}
197
198/* The mode_config.mutex will be held for this call */
199static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
200 const struct drm_display_mode *mode, struct drm_display_mode *adj)
201{
202 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
203 int ret;
204
205 /*
206 * Set CRTC modesetting parameters for the adjusted mode. This is
207 * applied after the connectors, bridges, and encoders have fixed up
208 * this mode, as described above drm_atomic_helper_check_modeset().
209 */
210 drm_mode_set_crtcinfo(adj, CRTC_INTERLACE_HALVE_V);
211
212 /*
213 * Validate the adjusted mode in case an encoder/bridge has set
214 * something we don't support.
215 */
216 if (armada_drm_crtc_mode_valid(crtc, adj) != MODE_OK)
217 return false;
218
219 /* Check whether the display mode is possible */
220 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
221 if (ret)
222 return false;
223
224 return true;
225}
226
227/* These are locked by dev->vbl_lock */
228static void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
229{
230 if (dcrtc->irq_ena & mask) {
231 dcrtc->irq_ena &= ~mask;
232 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
233 }
234}
235
236static void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
237{
238 if ((dcrtc->irq_ena & mask) != mask) {
239 dcrtc->irq_ena |= mask;
240 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
241 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
242 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
243 }
244}
245
246static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
247{
248 struct drm_pending_vblank_event *event;
249 void __iomem *base = dcrtc->base;
250
251 if (stat & DMA_FF_UNDERFLOW)
252 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
253 if (stat & GRA_FF_UNDERFLOW)
254 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
255
256 if (stat & VSYNC_IRQ)
257 drm_crtc_handle_vblank(&dcrtc->crtc);
258
259 spin_lock(&dcrtc->irq_lock);
260 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
261 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
262 uint32_t val;
263
264 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
265 writel_relaxed(dcrtc->v[i].spu_v_h_total,
266 base + LCD_SPUT_V_H_TOTAL);
267
268 val = readl_relaxed(base + LCD_SPU_ADV_REG);
269 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
270 val |= dcrtc->v[i].spu_adv_reg;
271 writel_relaxed(val, base + LCD_SPU_ADV_REG);
272 }
273
274 if (stat & dcrtc->irq_ena & DUMB_FRAMEDONE) {
275 if (dcrtc->update_pending) {
276 armada_drm_crtc_update_regs(dcrtc, dcrtc->regs);
277 dcrtc->update_pending = false;
278 }
279 if (dcrtc->cursor_update) {
280 writel_relaxed(dcrtc->cursor_hw_pos,
281 base + LCD_SPU_HWC_OVSA_HPXL_VLN);
282 writel_relaxed(dcrtc->cursor_hw_sz,
283 base + LCD_SPU_HWC_HPXL_VLN);
284 armada_updatel(CFG_HWC_ENA,
285 CFG_HWC_ENA | CFG_HWC_1BITMOD |
286 CFG_HWC_1BITENA,
287 base + LCD_SPU_DMA_CTRL0);
288 dcrtc->cursor_update = false;
289 }
290 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
291 }
292 spin_unlock(&dcrtc->irq_lock);
293
294 if (stat & VSYNC_IRQ && !dcrtc->update_pending) {
295 event = xchg(&dcrtc->event, NULL);
296 if (event) {
297 spin_lock(&dcrtc->crtc.dev->event_lock);
298 drm_crtc_send_vblank_event(&dcrtc->crtc, event);
299 spin_unlock(&dcrtc->crtc.dev->event_lock);
300 drm_crtc_vblank_put(&dcrtc->crtc);
301 }
302 }
303}
304
305static irqreturn_t armada_drm_irq(int irq, void *arg)
306{
307 struct armada_crtc *dcrtc = arg;
308 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
309
310 /*
311 * Reading the ISR appears to clear bits provided CLEAN_SPU_IRQ_ISR
312 * is set. Writing has some other effect to acknowledge the IRQ -
313 * without this, we only get a single IRQ.
314 */
315 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
316
317 trace_armada_drm_irq(&dcrtc->crtc, stat);
318
319 /* Mask out those interrupts we haven't enabled */
320 v = stat & dcrtc->irq_ena;
321
322 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
323 armada_drm_crtc_irq(dcrtc, stat);
324 return IRQ_HANDLED;
325 }
326 return IRQ_NONE;
327}
328
329/* The mode_config.mutex will be held for this call */
330static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
331{
332 struct drm_display_mode *adj = &crtc->state->adjusted_mode;
333 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
334 struct armada_regs regs[17];
335 uint32_t lm, rm, tm, bm, val, sclk;
336 unsigned long flags;
337 unsigned i;
338 bool interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
339
340 i = 0;
341 rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
342 lm = adj->crtc_htotal - adj->crtc_hsync_end;
343 bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
344 tm = adj->crtc_vtotal - adj->crtc_vsync_end;
345
346 DRM_DEBUG_KMS("[CRTC:%d:%s] mode " DRM_MODE_FMT "\n",
347 crtc->base.id, crtc->name, DRM_MODE_ARG(adj));
348 DRM_DEBUG_KMS("lm %d rm %d tm %d bm %d\n", lm, rm, tm, bm);
349
350 /* Now compute the divider for real */
351 dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
352
353 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
354
355 spin_lock_irqsave(&dcrtc->irq_lock, flags);
356
357 dcrtc->interlaced = interlaced;
358 /* Even interlaced/progressive frame */
359 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
360 adj->crtc_htotal;
361 dcrtc->v[1].spu_v_porch = tm << 16 | bm;
362 val = adj->crtc_hsync_start;
363 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
364
365 if (interlaced) {
366 /* Odd interlaced frame */
367 val -= adj->crtc_htotal / 2;
368 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN;
369 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
370 (1 << 16);
371 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
372 } else {
373 dcrtc->v[0] = dcrtc->v[1];
374 }
375
376 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
377
378 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
379 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
380 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
381 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
382 LCD_SPUT_V_H_TOTAL);
383
384 if (dcrtc->variant->has_spu_adv_reg)
385 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
386 ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
387 ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
388
389 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
390 armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
391
392 /*
393 * The documentation doesn't indicate what the normal state of
394 * the sync signals are. Sebastian Hesselbart kindly probed
395 * these signals on his board to determine their state.
396 *
397 * The non-inverted state of the sync signals is active high.
398 * Setting these bits makes the appropriate signal active low.
399 */
400 val = 0;
401 if (adj->flags & DRM_MODE_FLAG_NCSYNC)
402 val |= CFG_INV_CSYNC;
403 if (adj->flags & DRM_MODE_FLAG_NHSYNC)
404 val |= CFG_INV_HSYNC;
405 if (adj->flags & DRM_MODE_FLAG_NVSYNC)
406 val |= CFG_INV_VSYNC;
407 armada_reg_queue_mod(regs, i, val, CFG_INV_CSYNC | CFG_INV_HSYNC |
408 CFG_INV_VSYNC, LCD_SPU_DUMB_CTRL);
409 armada_reg_queue_end(regs, i);
410
411 armada_drm_crtc_update_regs(dcrtc, regs);
412 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
413}
414
415static int armada_drm_crtc_atomic_check(struct drm_crtc *crtc,
416 struct drm_crtc_state *state)
417{
418 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
419
420 if (state->gamma_lut && drm_color_lut_size(state->gamma_lut) != 256)
421 return -EINVAL;
422
423 if (state->color_mgmt_changed)
424 state->planes_changed = true;
425
426 return 0;
427}
428
429static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc,
430 struct drm_crtc_state *old_crtc_state)
431{
432 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
433
434 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
435
436 if (crtc->state->color_mgmt_changed)
437 armada_drm_update_gamma(crtc);
438
439 dcrtc->regs_idx = 0;
440 dcrtc->regs = dcrtc->atomic_regs;
441}
442
443static void armada_drm_crtc_atomic_flush(struct drm_crtc *crtc,
444 struct drm_crtc_state *old_crtc_state)
445{
446 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
447
448 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
449
450 armada_reg_queue_end(dcrtc->regs, dcrtc->regs_idx);
451
452 /*
453 * If we aren't doing a full modeset, then we need to queue
454 * the event here.
455 */
456 if (!drm_atomic_crtc_needs_modeset(crtc->state)) {
457 dcrtc->update_pending = true;
458 armada_drm_crtc_queue_state_event(crtc);
459 spin_lock_irq(&dcrtc->irq_lock);
460 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
461 spin_unlock_irq(&dcrtc->irq_lock);
462 } else {
463 spin_lock_irq(&dcrtc->irq_lock);
464 armada_drm_crtc_update_regs(dcrtc, dcrtc->regs);
465 spin_unlock_irq(&dcrtc->irq_lock);
466 }
467}
468
469static void armada_drm_crtc_atomic_disable(struct drm_crtc *crtc,
470 struct drm_crtc_state *old_state)
471{
472 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
473 struct drm_pending_vblank_event *event;
474
475 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
476
477 if (old_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
478 drm_crtc_vblank_put(crtc);
479
480 drm_crtc_vblank_off(crtc);
481 armada_drm_crtc_update(dcrtc, false);
482
483 if (!crtc->state->active) {
484 /*
485 * This modeset will be leaving the CRTC disabled, so
486 * call the backend to disable upstream clocks etc.
487 */
488 if (dcrtc->variant->disable)
489 dcrtc->variant->disable(dcrtc);
490
491 /*
492 * We will not receive any further vblank events.
493 * Send the flip_done event manually.
494 */
495 event = crtc->state->event;
496 crtc->state->event = NULL;
497 if (event) {
498 spin_lock_irq(&crtc->dev->event_lock);
499 drm_crtc_send_vblank_event(crtc, event);
500 spin_unlock_irq(&crtc->dev->event_lock);
501 }
502 }
503}
504
505static void armada_drm_crtc_atomic_enable(struct drm_crtc *crtc,
506 struct drm_crtc_state *old_state)
507{
508 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
509
510 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
511
512 if (!old_state->active) {
513 /*
514 * This modeset is enabling the CRTC after it having
515 * been disabled. Reverse the call to ->disable in
516 * the atomic_disable().
517 */
518 if (dcrtc->variant->enable)
519 dcrtc->variant->enable(dcrtc, &crtc->state->adjusted_mode);
520 }
521 armada_drm_crtc_update(dcrtc, true);
522 drm_crtc_vblank_on(crtc);
523
524 if (crtc->state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
525 WARN_ON(drm_crtc_vblank_get(crtc));
526
527 armada_drm_crtc_queue_state_event(crtc);
528}
529
530static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
531 .mode_valid = armada_drm_crtc_mode_valid,
532 .mode_fixup = armada_drm_crtc_mode_fixup,
533 .mode_set_nofb = armada_drm_crtc_mode_set_nofb,
534 .atomic_check = armada_drm_crtc_atomic_check,
535 .atomic_begin = armada_drm_crtc_atomic_begin,
536 .atomic_flush = armada_drm_crtc_atomic_flush,
537 .atomic_disable = armada_drm_crtc_atomic_disable,
538 .atomic_enable = armada_drm_crtc_atomic_enable,
539};
540
541static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
542 unsigned stride, unsigned width, unsigned height)
543{
544 uint32_t addr;
545 unsigned y;
546
547 addr = SRAM_HWC32_RAM1;
548 for (y = 0; y < height; y++) {
549 uint32_t *p = &pix[y * stride];
550 unsigned x;
551
552 for (x = 0; x < width; x++, p++) {
553 uint32_t val = *p;
554
555 /*
556 * In "ARGB888" (HWC32) mode, writing to the SRAM
557 * requires these bits to contain:
558 * 31:24 = alpha 23:16 = blue 15:8 = green 7:0 = red
559 * So, it's actually ABGR8888. This is independent
560 * of the SWAPRB bits in DMA control register 0.
561 */
562 val = (val & 0xff00ff00) |
563 (val & 0x000000ff) << 16 |
564 (val & 0x00ff0000) >> 16;
565
566 writel_relaxed(val,
567 base + LCD_SPU_SRAM_WRDAT);
568 writel_relaxed(addr | SRAM_WRITE,
569 base + LCD_SPU_SRAM_CTRL);
570 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
571 addr += 1;
572 if ((addr & 0x00ff) == 0)
573 addr += 0xf00;
574 if ((addr & 0x30ff) == 0)
575 addr = SRAM_HWC32_RAM2;
576 }
577 }
578}
579
580static void armada_drm_crtc_cursor_tran(void __iomem *base)
581{
582 unsigned addr;
583
584 for (addr = 0; addr < 256; addr++) {
585 /* write the default value */
586 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
587 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
588 base + LCD_SPU_SRAM_CTRL);
589 }
590}
591
592static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
593{
594 uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
595 uint32_t yoff, yscr, h = dcrtc->cursor_h;
596 uint32_t para1;
597
598 /*
599 * Calculate the visible width and height of the cursor,
600 * screen position, and the position in the cursor bitmap.
601 */
602 if (dcrtc->cursor_x < 0) {
603 xoff = -dcrtc->cursor_x;
604 xscr = 0;
605 w -= min(xoff, w);
606 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
607 xoff = 0;
608 xscr = dcrtc->cursor_x;
609 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
610 } else {
611 xoff = 0;
612 xscr = dcrtc->cursor_x;
613 }
614
615 if (dcrtc->cursor_y < 0) {
616 yoff = -dcrtc->cursor_y;
617 yscr = 0;
618 h -= min(yoff, h);
619 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
620 yoff = 0;
621 yscr = dcrtc->cursor_y;
622 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
623 } else {
624 yoff = 0;
625 yscr = dcrtc->cursor_y;
626 }
627
628 /* On interlaced modes, the vertical cursor size must be halved */
629 s = dcrtc->cursor_w;
630 if (dcrtc->interlaced) {
631 s *= 2;
632 yscr /= 2;
633 h /= 2;
634 }
635
636 if (!dcrtc->cursor_obj || !h || !w) {
637 spin_lock_irq(&dcrtc->irq_lock);
638 dcrtc->cursor_update = false;
639 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
640 spin_unlock_irq(&dcrtc->irq_lock);
641 return 0;
642 }
643
644 spin_lock_irq(&dcrtc->irq_lock);
645 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
646 armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
647 dcrtc->base + LCD_SPU_SRAM_PARA1);
648 spin_unlock_irq(&dcrtc->irq_lock);
649
650 /*
651 * Initialize the transparency if the SRAM was powered down.
652 * We must also reload the cursor data as well.
653 */
654 if (!(para1 & CFG_CSB_256x32)) {
655 armada_drm_crtc_cursor_tran(dcrtc->base);
656 reload = true;
657 }
658
659 if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
660 spin_lock_irq(&dcrtc->irq_lock);
661 dcrtc->cursor_update = false;
662 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
663 spin_unlock_irq(&dcrtc->irq_lock);
664 reload = true;
665 }
666 if (reload) {
667 struct armada_gem_object *obj = dcrtc->cursor_obj;
668 uint32_t *pix;
669 /* Set the top-left corner of the cursor image */
670 pix = obj->addr;
671 pix += yoff * s + xoff;
672 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
673 }
674
675 /* Reload the cursor position, size and enable in the IRQ handler */
676 spin_lock_irq(&dcrtc->irq_lock);
677 dcrtc->cursor_hw_pos = yscr << 16 | xscr;
678 dcrtc->cursor_hw_sz = h << 16 | w;
679 dcrtc->cursor_update = true;
680 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
681 spin_unlock_irq(&dcrtc->irq_lock);
682
683 return 0;
684}
685
686static void cursor_update(void *data)
687{
688 armada_drm_crtc_cursor_update(data, true);
689}
690
691static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
692 struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
693{
694 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
695 struct armada_gem_object *obj = NULL;
696 int ret;
697
698 /* If no cursor support, replicate drm's return value */
699 if (!dcrtc->variant->has_spu_adv_reg)
700 return -ENXIO;
701
702 if (handle && w > 0 && h > 0) {
703 /* maximum size is 64x32 or 32x64 */
704 if (w > 64 || h > 64 || (w > 32 && h > 32))
705 return -ENOMEM;
706
707 obj = armada_gem_object_lookup(file, handle);
708 if (!obj)
709 return -ENOENT;
710
711 /* Must be a kernel-mapped object */
712 if (!obj->addr) {
713 drm_gem_object_put_unlocked(&obj->obj);
714 return -EINVAL;
715 }
716
717 if (obj->obj.size < w * h * 4) {
718 DRM_ERROR("buffer is too small\n");
719 drm_gem_object_put_unlocked(&obj->obj);
720 return -ENOMEM;
721 }
722 }
723
724 if (dcrtc->cursor_obj) {
725 dcrtc->cursor_obj->update = NULL;
726 dcrtc->cursor_obj->update_data = NULL;
727 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
728 }
729 dcrtc->cursor_obj = obj;
730 dcrtc->cursor_w = w;
731 dcrtc->cursor_h = h;
732 ret = armada_drm_crtc_cursor_update(dcrtc, true);
733 if (obj) {
734 obj->update_data = dcrtc;
735 obj->update = cursor_update;
736 }
737
738 return ret;
739}
740
741static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
742{
743 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
744 int ret;
745
746 /* If no cursor support, replicate drm's return value */
747 if (!dcrtc->variant->has_spu_adv_reg)
748 return -EFAULT;
749
750 dcrtc->cursor_x = x;
751 dcrtc->cursor_y = y;
752 ret = armada_drm_crtc_cursor_update(dcrtc, false);
753
754 return ret;
755}
756
757static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
758{
759 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
760 struct armada_private *priv = crtc->dev->dev_private;
761
762 if (dcrtc->cursor_obj)
763 drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
764
765 priv->dcrtc[dcrtc->num] = NULL;
766 drm_crtc_cleanup(&dcrtc->crtc);
767
768 if (dcrtc->variant->disable)
769 dcrtc->variant->disable(dcrtc);
770
771 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
772
773 of_node_put(dcrtc->crtc.port);
774
775 kfree(dcrtc);
776}
777
778static int armada_drm_crtc_late_register(struct drm_crtc *crtc)
779{
780 if (IS_ENABLED(CONFIG_DEBUG_FS))
781 armada_drm_crtc_debugfs_init(drm_to_armada_crtc(crtc));
782
783 return 0;
784}
785
786/* These are called under the vbl_lock. */
787static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc)
788{
789 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
790 unsigned long flags;
791
792 spin_lock_irqsave(&dcrtc->irq_lock, flags);
793 armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA);
794 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
795 return 0;
796}
797
798static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc)
799{
800 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
801 unsigned long flags;
802
803 spin_lock_irqsave(&dcrtc->irq_lock, flags);
804 armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA);
805 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
806}
807
808static const struct drm_crtc_funcs armada_crtc_funcs = {
809 .reset = drm_atomic_helper_crtc_reset,
810 .cursor_set = armada_drm_crtc_cursor_set,
811 .cursor_move = armada_drm_crtc_cursor_move,
812 .destroy = armada_drm_crtc_destroy,
813 .gamma_set = drm_atomic_helper_legacy_gamma_set,
814 .set_config = drm_atomic_helper_set_config,
815 .page_flip = drm_atomic_helper_page_flip,
816 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
817 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
818 .late_register = armada_drm_crtc_late_register,
819 .enable_vblank = armada_drm_crtc_enable_vblank,
820 .disable_vblank = armada_drm_crtc_disable_vblank,
821};
822
823int armada_crtc_select_clock(struct armada_crtc *dcrtc,
824 struct armada_clk_result *res,
825 const struct armada_clocking_params *params,
826 struct clk *clks[], size_t num_clks,
827 unsigned long desired_khz)
828{
829 unsigned long desired_hz = desired_khz * 1000;
830 unsigned long desired_clk_hz; // requested clk input
831 unsigned long real_clk_hz; // actual clk input
832 unsigned long real_hz; // actual pixel clk
833 unsigned long permillage;
834 struct clk *clk;
835 u32 div;
836 int i;
837
838 DRM_DEBUG_KMS("[CRTC:%u:%s] desired clock=%luHz\n",
839 dcrtc->crtc.base.id, dcrtc->crtc.name, desired_hz);
840
841 for (i = 0; i < num_clks; i++) {
842 clk = clks[i];
843 if (!clk)
844 continue;
845
846 if (params->settable & BIT(i)) {
847 real_clk_hz = clk_round_rate(clk, desired_hz);
848 desired_clk_hz = desired_hz;
849 } else {
850 real_clk_hz = clk_get_rate(clk);
851 desired_clk_hz = real_clk_hz;
852 }
853
854 /* If the clock can do exactly the desired rate, we're done */
855 if (real_clk_hz == desired_hz) {
856 real_hz = real_clk_hz;
857 div = 1;
858 goto found;
859 }
860
861 /* Calculate the divider - if invalid, we can't do this rate */
862 div = DIV_ROUND_CLOSEST(real_clk_hz, desired_hz);
863 if (div == 0 || div > params->div_max)
864 continue;
865
866 /* Calculate the actual rate - HDMI requires -0.6%..+0.5% */
867 real_hz = DIV_ROUND_CLOSEST(real_clk_hz, div);
868
869 DRM_DEBUG_KMS("[CRTC:%u:%s] clk=%u %luHz div=%u real=%luHz\n",
870 dcrtc->crtc.base.id, dcrtc->crtc.name,
871 i, real_clk_hz, div, real_hz);
872
873 /* Avoid repeated division */
874 if (real_hz < desired_hz) {
875 permillage = real_hz / desired_khz;
876 if (permillage < params->permillage_min)
877 continue;
878 } else {
879 permillage = DIV_ROUND_UP(real_hz, desired_khz);
880 if (permillage > params->permillage_max)
881 continue;
882 }
883 goto found;
884 }
885
886 return -ERANGE;
887
888found:
889 DRM_DEBUG_KMS("[CRTC:%u:%s] selected clk=%u %luHz div=%u real=%luHz\n",
890 dcrtc->crtc.base.id, dcrtc->crtc.name,
891 i, real_clk_hz, div, real_hz);
892
893 res->desired_clk_hz = desired_clk_hz;
894 res->clk = clk;
895 res->div = div;
896
897 return i;
898}
899
900static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
901 struct resource *res, int irq, const struct armada_variant *variant,
902 struct device_node *port)
903{
904 struct armada_private *priv = drm->dev_private;
905 struct armada_crtc *dcrtc;
906 struct drm_plane *primary;
907 void __iomem *base;
908 int ret;
909
910 base = devm_ioremap_resource(dev, res);
911 if (IS_ERR(base))
912 return PTR_ERR(base);
913
914 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
915 if (!dcrtc) {
916 DRM_ERROR("failed to allocate Armada crtc\n");
917 return -ENOMEM;
918 }
919
920 if (dev != drm->dev)
921 dev_set_drvdata(dev, dcrtc);
922
923 dcrtc->variant = variant;
924 dcrtc->base = base;
925 dcrtc->num = drm->mode_config.num_crtc;
926 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
927 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
928 spin_lock_init(&dcrtc->irq_lock);
929 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
930
931 /* Initialize some registers which we don't otherwise set */
932 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
933 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
934 writel_relaxed(dcrtc->spu_iopad_ctrl,
935 dcrtc->base + LCD_SPU_IOPAD_CONTROL);
936 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
937 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
938 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
939 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
940 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
941 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
942 readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
943 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
944
945 ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
946 dcrtc);
947 if (ret < 0)
948 goto err_crtc;
949
950 if (dcrtc->variant->init) {
951 ret = dcrtc->variant->init(dcrtc, dev);
952 if (ret)
953 goto err_crtc;
954 }
955
956 /* Ensure AXI pipeline is enabled */
957 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
958
959 priv->dcrtc[dcrtc->num] = dcrtc;
960
961 dcrtc->crtc.port = port;
962
963 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
964 if (!primary) {
965 ret = -ENOMEM;
966 goto err_crtc;
967 }
968
969 ret = armada_drm_primary_plane_init(drm, primary);
970 if (ret) {
971 kfree(primary);
972 goto err_crtc;
973 }
974
975 ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, primary, NULL,
976 &armada_crtc_funcs, NULL);
977 if (ret)
978 goto err_crtc_init;
979
980 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
981
982 ret = drm_mode_crtc_set_gamma_size(&dcrtc->crtc, 256);
983 if (ret)
984 return ret;
985
986 drm_crtc_enable_color_mgmt(&dcrtc->crtc, 0, false, 256);
987
988 return armada_overlay_plane_create(drm, 1 << dcrtc->num);
989
990err_crtc_init:
991 primary->funcs->destroy(primary);
992err_crtc:
993 kfree(dcrtc);
994
995 return ret;
996}
997
998static int
999armada_lcd_bind(struct device *dev, struct device *master, void *data)
1000{
1001 struct platform_device *pdev = to_platform_device(dev);
1002 struct drm_device *drm = data;
1003 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1004 int irq = platform_get_irq(pdev, 0);
1005 const struct armada_variant *variant;
1006 struct device_node *port = NULL;
1007
1008 if (irq < 0)
1009 return irq;
1010
1011 if (!dev->of_node) {
1012 const struct platform_device_id *id;
1013
1014 id = platform_get_device_id(pdev);
1015 if (!id)
1016 return -ENXIO;
1017
1018 variant = (const struct armada_variant *)id->driver_data;
1019 } else {
1020 const struct of_device_id *match;
1021 struct device_node *np, *parent = dev->of_node;
1022
1023 match = of_match_device(dev->driver->of_match_table, dev);
1024 if (!match)
1025 return -ENXIO;
1026
1027 np = of_get_child_by_name(parent, "ports");
1028 if (np)
1029 parent = np;
1030 port = of_get_child_by_name(parent, "port");
1031 of_node_put(np);
1032 if (!port) {
1033 dev_err(dev, "no port node found in %pOF\n", parent);
1034 return -ENXIO;
1035 }
1036
1037 variant = match->data;
1038 }
1039
1040 return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1041}
1042
1043static void
1044armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1045{
1046 struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1047
1048 armada_drm_crtc_destroy(&dcrtc->crtc);
1049}
1050
1051static const struct component_ops armada_lcd_ops = {
1052 .bind = armada_lcd_bind,
1053 .unbind = armada_lcd_unbind,
1054};
1055
1056static int armada_lcd_probe(struct platform_device *pdev)
1057{
1058 return component_add(&pdev->dev, &armada_lcd_ops);
1059}
1060
1061static int armada_lcd_remove(struct platform_device *pdev)
1062{
1063 component_del(&pdev->dev, &armada_lcd_ops);
1064 return 0;
1065}
1066
1067static const struct of_device_id armada_lcd_of_match[] = {
1068 {
1069 .compatible = "marvell,dove-lcd",
1070 .data = &armada510_ops,
1071 },
1072 {}
1073};
1074MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1075
1076static const struct platform_device_id armada_lcd_platform_ids[] = {
1077 {
1078 .name = "armada-lcd",
1079 .driver_data = (unsigned long)&armada510_ops,
1080 }, {
1081 .name = "armada-510-lcd",
1082 .driver_data = (unsigned long)&armada510_ops,
1083 },
1084 { },
1085};
1086MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1087
1088struct platform_driver armada_lcd_platform_driver = {
1089 .probe = armada_lcd_probe,
1090 .remove = armada_lcd_remove,
1091 .driver = {
1092 .name = "armada-lcd",
1093 .owner = THIS_MODULE,
1094 .of_match_table = armada_lcd_of_match,
1095 },
1096 .id_table = armada_lcd_platform_ids,
1097};