1/*
 2 * apb_timer.h: Driver for Langwell APB timer based on Synopsis DesignWare
 3 *
 4 * (C) Copyright 2009 Intel Corporation
 5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
 6 *
 7 * This program is free software; you can redistribute it and/or
 8 * modify it under the terms of the GNU General Public License
 9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 *
12 * Note:
13 */
14
15#ifndef ASM_X86_APBT_H
16#define ASM_X86_APBT_H
17#include <linux/sfi.h>
18
19#ifdef CONFIG_APB_TIMER
20
21/* default memory mapped register base */
22#define LNW_SCU_ADDR           0xFF100000
23#define LNW_EXT_TIMER_OFFSET   0x1B800
24#define APBT_DEFAULT_BASE      (LNW_SCU_ADDR+LNW_EXT_TIMER_OFFSET)
25#define LNW_EXT_TIMER_PGOFFSET         0x800
26
27/* APBT clock speed range from PCLK to fabric base, 25-100MHz */
28#define APBT_MAX_FREQ          50000000
29#define APBT_MIN_FREQ          1000000
30#define APBT_MMAP_SIZE         1024
31
32#define APBT_DEV_USED  1
33
34extern void apbt_time_init(void);
35extern unsigned long apbt_quick_calibrate(void);
36extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);
37extern void apbt_setup_secondary_clock(void);
38
39extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);
40extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);
41extern int sfi_mtimer_num;
42
43#else /* CONFIG_APB_TIMER */
44
45static inline unsigned long apbt_quick_calibrate(void) {return 0; }
46static inline void apbt_time_init(void) { }
47
48#endif
49#endif /* ASM_X86_APBT_H */

 1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * apb_timer.h: Driver for Langwell APB timer based on Synopsis DesignWare
 4 *
 5 * (C) Copyright 2009 Intel Corporation
 6 * Author: Jacob Pan (jacob.jun.pan@intel.com)
 
 
 
 
 
 7 *
 8 * Note:
 9 */
10
11#ifndef ASM_X86_APBT_H
12#define ASM_X86_APBT_H
13#include <linux/sfi.h>
14
15#ifdef CONFIG_APB_TIMER
16
17/* default memory mapped register base */
18#define LNW_SCU_ADDR           0xFF100000
19#define LNW_EXT_TIMER_OFFSET   0x1B800
20#define APBT_DEFAULT_BASE      (LNW_SCU_ADDR+LNW_EXT_TIMER_OFFSET)
21#define LNW_EXT_TIMER_PGOFFSET         0x800
22
23/* APBT clock speed range from PCLK to fabric base, 25-100MHz */
24#define APBT_MAX_FREQ          50000000
25#define APBT_MIN_FREQ          1000000
26#define APBT_MMAP_SIZE         1024
27
28#define APBT_DEV_USED  1
29
30extern void apbt_time_init(void);
31extern unsigned long apbt_quick_calibrate(void);
32extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);
33extern void apbt_setup_secondary_clock(void);
34
35extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);
36extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);
37extern int sfi_mtimer_num;
38
39#else /* CONFIG_APB_TIMER */
40
41static inline unsigned long apbt_quick_calibrate(void) {return 0; }
42static inline void apbt_time_init(void) { }
43
44#endif
45#endif /* ASM_X86_APBT_H */