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1/*
2 * SBC8548 Device Tree Source
3 *
4 * Configured for booting off the alternate (64MB SODIMM) flash.
5 * Requires switching JP12 jumpers and changing SW2.8 setting.
6 *
7 * Copyright 2013 Wind River Systems Inc.
8 *
9 * Paul Gortmaker (see MAINTAINERS for contact information)
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17
18/dts-v1/;
19
20/include/ "sbc8548-pre.dtsi"
21
22/{
23 localbus@e0000000 {
24 #address-cells = <2>;
25 #size-cells = <1>;
26 compatible = "simple-bus";
27 reg = <0xe0000000 0x5000>;
28 interrupt-parent = <&mpic>;
29
30 ranges = <0x0 0x0 0xfc000000 0x04000000 /*64MB Flash*/
31 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
32 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
33 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
34 0x6 0x0 0xef800000 0x00800000>; /*8MB Flash*/
35
36 flash@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 reg = <0x0 0x0 0x04000000>;
40 compatible = "intel,JS28F128", "cfi-flash";
41 bank-width = <4>;
42 device-width = <1>;
43 partition@0 {
44 label = "space";
45 /* FC000000 -> FFEFFFFF */
46 reg = <0x00000000 0x03f00000>;
47 };
48 partition@3f00000 {
49 label = "bootloader";
50 /* FFF00000 -> FFFFFFFF */
51 reg = <0x03f00000 0x00100000>;
52 read-only;
53 };
54 };
55
56
57 epld@5,0 {
58 compatible = "wrs,epld-localbus";
59 #address-cells = <2>;
60 #size-cells = <1>;
61 reg = <0x5 0x0 0x00b10000>;
62 ranges = <
63 0x0 0x0 0x5 0x000000 0x1fff /* LED */
64 0x1 0x0 0x5 0x100000 0x1fff /* Switches */
65 0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */
66 0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */
67 >;
68
69 led@0,0 {
70 compatible = "led";
71 reg = <0x0 0x0 0x1fff>;
72 };
73
74 switches@1,0 {
75 compatible = "switches";
76 reg = <0x1 0x0 0x1fff>;
77 };
78
79 hw-rev@3,0 {
80 compatible = "hw-rev";
81 reg = <0x3 0x0 0x1fff>;
82 };
83
84 eeprom@b,0 {
85 compatible = "eeprom";
86 reg = <0xb 0 0x1fff>;
87 };
88
89 };
90
91 alt-flash@6,0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "intel,JS28F640", "cfi-flash";
95 reg = <0x6 0x0 0x800000>;
96 bank-width = <1>;
97 device-width = <1>;
98 partition@0 {
99 label = "space";
100 /* EF800000 -> EFF9FFFF */
101 reg = <0x00000000 0x007a0000>;
102 };
103 partition@7a0000 {
104 label = "bootloader";
105 /* EFFA0000 -> EFFFFFFF */
106 reg = <0x007a0000 0x00060000>;
107 read-only;
108 };
109 };
110
111
112 };
113};
114
115/include/ "sbc8548-post.dtsi"
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * SBC8548 Device Tree Source
4 *
5 * Configured for booting off the alternate (64MB SODIMM) flash.
6 * Requires switching JP12 jumpers and changing SW2.8 setting.
7 *
8 * Copyright 2013 Wind River Systems Inc.
9 *
10 * Paul Gortmaker (see MAINTAINERS for contact information)
11 */
12
13
14/dts-v1/;
15
16/include/ "sbc8548-pre.dtsi"
17
18/{
19 localbus@e0000000 {
20 #address-cells = <2>;
21 #size-cells = <1>;
22 compatible = "simple-bus";
23 reg = <0xe0000000 0x5000>;
24 interrupt-parent = <&mpic>;
25
26 ranges = <0x0 0x0 0xfc000000 0x04000000 /*64MB Flash*/
27 0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
28 0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
29 0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
30 0x6 0x0 0xef800000 0x00800000>; /*8MB Flash*/
31
32 flash@0,0 {
33 #address-cells = <1>;
34 #size-cells = <1>;
35 reg = <0x0 0x0 0x04000000>;
36 compatible = "intel,JS28F128", "cfi-flash";
37 bank-width = <4>;
38 device-width = <1>;
39 partition@0 {
40 label = "space";
41 /* FC000000 -> FFEFFFFF */
42 reg = <0x00000000 0x03f00000>;
43 };
44 partition@3f00000 {
45 label = "bootloader";
46 /* FFF00000 -> FFFFFFFF */
47 reg = <0x03f00000 0x00100000>;
48 read-only;
49 };
50 };
51
52
53 epld@5,0 {
54 compatible = "wrs,epld-localbus";
55 #address-cells = <2>;
56 #size-cells = <1>;
57 reg = <0x5 0x0 0x00b10000>;
58 ranges = <
59 0x0 0x0 0x5 0x000000 0x1fff /* LED */
60 0x1 0x0 0x5 0x100000 0x1fff /* Switches */
61 0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */
62 0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */
63 >;
64
65 led@0,0 {
66 compatible = "led";
67 reg = <0x0 0x0 0x1fff>;
68 };
69
70 switches@1,0 {
71 compatible = "switches";
72 reg = <0x1 0x0 0x1fff>;
73 };
74
75 hw-rev@3,0 {
76 compatible = "hw-rev";
77 reg = <0x3 0x0 0x1fff>;
78 };
79
80 eeprom@b,0 {
81 compatible = "eeprom";
82 reg = <0xb 0 0x1fff>;
83 };
84
85 };
86
87 alt-flash@6,0 {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "intel,JS28F640", "cfi-flash";
91 reg = <0x6 0x0 0x800000>;
92 bank-width = <1>;
93 device-width = <1>;
94 partition@0 {
95 label = "space";
96 /* EF800000 -> EFF9FFFF */
97 reg = <0x00000000 0x007a0000>;
98 };
99 partition@7a0000 {
100 label = "bootloader";
101 /* EFFA0000 -> EFFFFFFF */
102 reg = <0x007a0000 0x00060000>;
103 read-only;
104 };
105 };
106
107
108 };
109};
110
111/include/ "sbc8548-post.dtsi"