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1/*
2 * Device Tree Source for the Marzen board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/dts-v1/;
13#include "r8a7779.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
17/ {
18 model = "marzen";
19 compatible = "renesas,marzen", "renesas,r8a7779";
20
21 aliases {
22 serial0 = &scif2;
23 serial1 = &scif4;
24 };
25
26 chosen {
27 bootargs = "ignore_loglevel root=/dev/nfs ip=on";
28 stdout-path = "serial0:115200n8";
29 };
30
31 memory@60000000 {
32 device_type = "memory";
33 reg = <0x60000000 0x40000000>;
34 };
35
36 fixedregulator3v3: regulator-3v3 {
37 compatible = "regulator-fixed";
38 regulator-name = "fixed-3.3V";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 regulator-boot-on;
42 regulator-always-on;
43 };
44
45 vccq_sdhi0: regulator-vccq-sdhi0 {
46 compatible = "regulator-gpio";
47
48 regulator-name = "SDHI0 VccQ";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <3300000>;
51
52 gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
53 gpios-states = <1>;
54 states = <3300000 1
55 1800000 0>;
56 };
57
58 ethernet@18000000 {
59 compatible = "smsc,lan9220", "smsc,lan9115";
60 reg = <0x18000000 0x100>;
61 pinctrl-0 = <ðernet_pins>;
62 pinctrl-names = "default";
63
64 phy-mode = "mii";
65 interrupt-parent = <&irqpin0>;
66 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
67 smsc,irq-push-pull;
68 reg-io-width = <4>;
69 vddvario-supply = <&fixedregulator3v3>;
70 vdd33a-supply = <&fixedregulator3v3>;
71 };
72
73 leds {
74 compatible = "gpio-leds";
75 led2 {
76 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
77 };
78 led3 {
79 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
80 };
81 led4 {
82 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
83 };
84 };
85
86 vga-encoder {
87 compatible = "adi,adv7123";
88
89 ports {
90 #address-cells = <1>;
91 #size-cells = <0>;
92
93 port@0 {
94 reg = <0>;
95 vga_enc_in: endpoint {
96 remote-endpoint = <&du_out_rgb0>;
97 };
98 };
99 port@1 {
100 reg = <1>;
101 vga_enc_out: endpoint {
102 remote-endpoint = <&vga_in>;
103 };
104 };
105 };
106 };
107
108 vga {
109 compatible = "vga-connector";
110
111 port {
112 vga_in: endpoint {
113 remote-endpoint = <&vga_enc_out>;
114 };
115 };
116 };
117
118 lvds-encoder {
119 compatible = "thine,thc63lvdm83d";
120
121 ports {
122 #address-cells = <1>;
123 #size-cells = <0>;
124
125 port@0 {
126 reg = <0>;
127 lvds_enc_in: endpoint {
128 remote-endpoint = <&du_out_rgb1>;
129 };
130 };
131 port@1 {
132 reg = <1>;
133 lvds_connector: endpoint {
134 };
135 };
136 };
137 };
138
139 x3_clk: x3-clock {
140 compatible = "fixed-clock";
141 #clock-cells = <0>;
142 clock-frequency = <65000000>;
143 };
144};
145
146&du {
147 pinctrl-0 = <&du_pins>;
148 pinctrl-names = "default";
149 status = "okay";
150
151 clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
152 clock-names = "du", "dclkin.0";
153
154 ports {
155 port@0 {
156 endpoint {
157 remote-endpoint = <&vga_enc_in>;
158 };
159 };
160 port@1 {
161 endpoint {
162 remote-endpoint = <&lvds_enc_in>;
163 };
164 };
165 };
166};
167
168&irqpin0 {
169 status = "okay";
170};
171
172&extal_clk {
173 clock-frequency = <31250000>;
174};
175
176&tmu0 {
177 status = "okay";
178};
179
180&pfc {
181 pinctrl-0 = <&scif_clk_pins>;
182 pinctrl-names = "default";
183
184 du_pins: du {
185 du0 {
186 groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in";
187 function = "du0";
188 };
189 du1 {
190 groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
191 function = "du1";
192 };
193 };
194
195 scif_clk_pins: scif_clk {
196 groups = "scif_clk_b";
197 function = "scif_clk";
198 };
199
200 ethernet_pins: ethernet {
201 intc {
202 groups = "intc_irq1_b";
203 function = "intc";
204 };
205 lbsc {
206 groups = "lbsc_ex_cs0";
207 function = "lbsc";
208 };
209 };
210
211 scif2_pins: scif2 {
212 groups = "scif2_data_c";
213 function = "scif2";
214 };
215
216 scif4_pins: scif4 {
217 groups = "scif4_data";
218 function = "scif4";
219 };
220
221 sdhi0_pins: sd0 {
222 groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
223 function = "sdhi0";
224 };
225
226 hspi0_pins: hspi0 {
227 groups = "hspi0";
228 function = "hspi0";
229 };
230};
231
232&sata {
233 status = "okay";
234};
235
236&scif2 {
237 pinctrl-0 = <&scif2_pins>;
238 pinctrl-names = "default";
239
240 status = "okay";
241};
242
243&scif4 {
244 pinctrl-0 = <&scif4_pins>;
245 pinctrl-names = "default";
246
247 status = "okay";
248};
249
250&scif_clk {
251 clock-frequency = <14745600>;
252};
253
254&sdhi0 {
255 pinctrl-0 = <&sdhi0_pins>;
256 pinctrl-names = "default";
257
258 vmmc-supply = <&fixedregulator3v3>;
259 vqmmc-supply = <&vccq_sdhi0>;
260 bus-width = <4>;
261 status = "okay";
262};
263
264&hspi0 {
265 pinctrl-0 = <&hspi0_pins>;
266 pinctrl-names = "default";
267 status = "okay";
268};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car H1 (R8A77790) Marzen board
4 *
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Simon Horman
7 */
8
9/dts-v1/;
10#include "r8a7779.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13
14/ {
15 model = "marzen";
16 compatible = "renesas,marzen", "renesas,r8a7779";
17
18 aliases {
19 serial0 = &scif2;
20 serial1 = &scif4;
21 };
22
23 chosen {
24 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
25 stdout-path = "serial0:115200n8";
26 };
27
28 memory@60000000 {
29 device_type = "memory";
30 reg = <0x60000000 0x40000000>;
31 };
32
33 fixedregulator3v3: regulator-3v3 {
34 compatible = "regulator-fixed";
35 regulator-name = "fixed-3.3V";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 regulator-boot-on;
39 regulator-always-on;
40 };
41
42 vccq_sdhi0: regulator-vccq-sdhi0 {
43 compatible = "regulator-gpio";
44
45 regulator-name = "SDHI0 VccQ";
46 regulator-min-microvolt = <1800000>;
47 regulator-max-microvolt = <3300000>;
48
49 gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
50 gpios-states = <1>;
51 states = <3300000 1
52 1800000 0>;
53 };
54
55 ethernet@18000000 {
56 compatible = "smsc,lan9220", "smsc,lan9115";
57 reg = <0x18000000 0x100>;
58 pinctrl-0 = <ðernet_pins>;
59 pinctrl-names = "default";
60
61 phy-mode = "mii";
62 interrupt-parent = <&irqpin0>;
63 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
64 smsc,irq-push-pull;
65 reg-io-width = <4>;
66 vddvario-supply = <&fixedregulator3v3>;
67 vdd33a-supply = <&fixedregulator3v3>;
68 };
69
70 leds {
71 compatible = "gpio-leds";
72 led2 {
73 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
74 };
75 led3 {
76 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
77 };
78 led4 {
79 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
80 };
81 };
82
83 vga-encoder {
84 compatible = "adi,adv7123";
85
86 ports {
87 #address-cells = <1>;
88 #size-cells = <0>;
89
90 port@0 {
91 reg = <0>;
92 vga_enc_in: endpoint {
93 remote-endpoint = <&du_out_rgb0>;
94 };
95 };
96 port@1 {
97 reg = <1>;
98 vga_enc_out: endpoint {
99 remote-endpoint = <&vga_in>;
100 };
101 };
102 };
103 };
104
105 vga {
106 compatible = "vga-connector";
107
108 port {
109 vga_in: endpoint {
110 remote-endpoint = <&vga_enc_out>;
111 };
112 };
113 };
114
115 lvds-encoder {
116 compatible = "thine,thc63lvdm83d";
117
118 ports {
119 #address-cells = <1>;
120 #size-cells = <0>;
121
122 port@0 {
123 reg = <0>;
124 lvds_enc_in: endpoint {
125 remote-endpoint = <&du_out_rgb1>;
126 };
127 };
128 port@1 {
129 reg = <1>;
130 lvds_connector: endpoint {
131 };
132 };
133 };
134 };
135
136 x3_clk: x3-clock {
137 compatible = "fixed-clock";
138 #clock-cells = <0>;
139 clock-frequency = <65000000>;
140 };
141};
142
143&du {
144 pinctrl-0 = <&du_pins>;
145 pinctrl-names = "default";
146 status = "okay";
147
148 clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
149 clock-names = "du", "dclkin.0";
150
151 ports {
152 port@0 {
153 endpoint {
154 remote-endpoint = <&vga_enc_in>;
155 };
156 };
157 port@1 {
158 endpoint {
159 remote-endpoint = <&lvds_enc_in>;
160 };
161 };
162 };
163};
164
165&irqpin0 {
166 status = "okay";
167};
168
169&extal_clk {
170 clock-frequency = <31250000>;
171};
172
173&tmu0 {
174 status = "okay";
175};
176
177&pfc {
178 pinctrl-0 = <&scif_clk_pins>;
179 pinctrl-names = "default";
180
181 du_pins: du {
182 du0 {
183 groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in";
184 function = "du0";
185 };
186 du1 {
187 groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
188 function = "du1";
189 };
190 };
191
192 scif_clk_pins: scif_clk {
193 groups = "scif_clk_b";
194 function = "scif_clk";
195 };
196
197 ethernet_pins: ethernet {
198 intc {
199 groups = "intc_irq1_b";
200 function = "intc";
201 };
202 lbsc {
203 groups = "lbsc_ex_cs0";
204 function = "lbsc";
205 };
206 };
207
208 scif2_pins: scif2 {
209 groups = "scif2_data_c";
210 function = "scif2";
211 };
212
213 scif4_pins: scif4 {
214 groups = "scif4_data";
215 function = "scif4";
216 };
217
218 sdhi0_pins: sd0 {
219 groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
220 function = "sdhi0";
221 };
222
223 hspi0_pins: hspi0 {
224 groups = "hspi0";
225 function = "hspi0";
226 };
227};
228
229&sata {
230 status = "okay";
231};
232
233&scif2 {
234 pinctrl-0 = <&scif2_pins>;
235 pinctrl-names = "default";
236
237 status = "okay";
238};
239
240&scif4 {
241 pinctrl-0 = <&scif4_pins>;
242 pinctrl-names = "default";
243
244 status = "okay";
245};
246
247&scif_clk {
248 clock-frequency = <14745600>;
249};
250
251&sdhi0 {
252 pinctrl-0 = <&sdhi0_pins>;
253 pinctrl-names = "default";
254
255 vmmc-supply = <&fixedregulator3v3>;
256 vqmmc-supply = <&vccq_sdhi0>;
257 bus-width = <4>;
258 status = "okay";
259};
260
261&hspi0 {
262 pinctrl-0 = <&hspi0_pins>;
263 pinctrl-names = "default";
264 status = "okay";
265};