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1/*
2 * Copyright 2017 NXP
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44
45#include "imx7d.dtsi"
46
47/ {
48 model = "Technexion Pico i.MX7D Board";
49 compatible = "technexion,imx7d-pico", "fsl,imx7d";
50
51 memory@80000000 {
52 reg = <0x80000000 0x80000000>;
53 };
54
55 reg_ap6212: regulator-ap6212 {
56 compatible = "regulator-fixed";
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_reg_ap6212>;
59 regulator-name = "AP6212";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
62 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
63 enable-active-high;
64 };
65
66 reg_2p5v: regulator-2p5v {
67 compatible = "regulator-fixed";
68 regulator-name = "2P5V";
69 regulator-min-microvolt = <2500000>;
70 regulator-max-microvolt = <2500000>;
71 regulator-always-on;
72 };
73
74 reg_3p3v: regulator-3p3v {
75 compatible = "regulator-fixed";
76 regulator-name = "3P3V";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 regulator-always-on;
80 };
81
82 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
83 compatible = "regulator-fixed";
84 regulator-name = "usb_otg1_vbus";
85 regulator-min-microvolt = <5000000>;
86 regulator-max-microvolt = <5000000>;
87 gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
88 };
89
90 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
91 compatible = "regulator-fixed";
92 regulator-name = "usb_otg2_vbus";
93 regulator-min-microvolt = <5000000>;
94 regulator-max-microvolt = <5000000>;
95 };
96
97 reg_vref_1v8: regulator-vref-1v8 {
98 compatible = "regulator-fixed";
99 regulator-name = "vref-1v8";
100 regulator-min-microvolt = <1800000>;
101 regulator-max-microvolt = <1800000>;
102 };
103};
104
105&i2c4 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_i2c4>;
108 status = "okay";
109
110 pmic: pfuze3000@8 {
111 compatible = "fsl,pfuze3000";
112 reg = <0x08>;
113
114 regulators {
115 sw1a_reg: sw1a {
116 regulator-min-microvolt = <700000>;
117 regulator-max-microvolt = <3300000>;
118 regulator-boot-on;
119 regulator-always-on;
120 regulator-ramp-delay = <6250>;
121 };
122 /* use sw1c_reg to align with pfuze100/pfuze200 */
123 sw1c_reg: sw1b {
124 regulator-min-microvolt = <700000>;
125 regulator-max-microvolt = <1475000>;
126 regulator-boot-on;
127 regulator-always-on;
128 regulator-ramp-delay = <6250>;
129 };
130
131 sw2_reg: sw2 {
132 regulator-min-microvolt = <1800000>;
133 regulator-max-microvolt = <1850000>;
134 regulator-boot-on;
135 regulator-always-on;
136 };
137
138 sw3a_reg: sw3 {
139 regulator-min-microvolt = <900000>;
140 regulator-max-microvolt = <1650000>;
141 regulator-boot-on;
142 regulator-always-on;
143 };
144
145 swbst_reg: swbst {
146 regulator-min-microvolt = <5000000>;
147 regulator-max-microvolt = <5150000>;
148 };
149
150 snvs_reg: vsnvs {
151 regulator-min-microvolt = <1000000>;
152 regulator-max-microvolt = <3000000>;
153 regulator-boot-on;
154 regulator-always-on;
155 };
156
157 vref_reg: vrefddr {
158 regulator-boot-on;
159 regulator-always-on;
160 };
161
162 vgen1_reg: vldo1 {
163 regulator-min-microvolt = <1800000>;
164 regulator-max-microvolt = <3300000>;
165 regulator-always-on;
166 };
167
168 vgen2_reg: vldo2 {
169 regulator-min-microvolt = <800000>;
170 regulator-max-microvolt = <1550000>;
171 };
172
173 vgen3_reg: vccsd {
174 regulator-min-microvolt = <2850000>;
175 regulator-max-microvolt = <3300000>;
176 regulator-always-on;
177 };
178
179 vgen4_reg: v33 {
180 regulator-min-microvolt = <2850000>;
181 regulator-max-microvolt = <3300000>;
182 regulator-always-on;
183 };
184
185 vgen5_reg: vldo3 {
186 regulator-min-microvolt = <1800000>;
187 regulator-max-microvolt = <3300000>;
188 regulator-always-on;
189 };
190
191 vgen6_reg: vldo4 {
192 regulator-min-microvolt = <1800000>;
193 regulator-max-microvolt = <3300000>;
194 regulator-always-on;
195 };
196 };
197 };
198};
199
200&usdhc2 { /* Wifi SDIO */
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_usdhc2>;
203 no-1-8-v;
204 non-removable;
205 keep-power-in-suspend;
206 wakeup-source;
207 vmmc-supply = <®_ap6212>;
208 status = "okay";
209};
210
211&usdhc3 {
212 pinctrl-names = "default", "state_100mhz", "state_200mhz";
213 pinctrl-0 = <&pinctrl_usdhc3>;
214 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
215 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
216 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
217 assigned-clock-rates = <400000000>;
218 bus-width = <8>;
219 no-1-8-v;
220 fsl,tuning-step = <2>;
221 non-removable;
222 status = "okay";
223};
224
225&wdog1 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_wdog>;
228 fsl,ext-reset-output;
229 status = "okay";
230};
231
232&iomuxc {
233 pinctrl_i2c4: i2c4grp {
234 fsl,pins = <
235 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
236 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
237 >;
238 };
239
240 pinctrl_reg_ap6212: regap6212grp {
241 fsl,pins = <
242 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
243 >;
244 };
245
246 pinctrl_usdhc2: usdhc2grp {
247 fsl,pins = <
248 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
249 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
250 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
251 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
252 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
253 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
254 >;
255 };
256
257 pinctrl_usdhc3: usdhc3grp {
258 fsl,pins = <
259 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
260 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
261 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
262 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
263 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
264 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
265 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
266 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
267 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
268 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
269 >;
270 };
271
272 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
273 fsl,pins = <
274 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
275 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
276 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
277 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
278 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
279 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
280 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
281 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
282 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
283 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
284 >;
285 };
286
287 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
288 fsl,pins = <
289 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
290 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
291 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
292 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
293 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
294 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
295 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
296 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
297 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
298 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
299 >;
300 };
301};
302
303&iomuxc_lpsr {
304 pinctrl_wdog: wdoggrp {
305 fsl,pins = <
306 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
307 >;
308 };
309};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2//
3// Copyright 2017 NXP
4
5/dts-v1/;
6
7#include "imx7d.dtsi"
8
9/ {
10 /* Will be filled by the bootloader */
11 memory@80000000 {
12 device_type = "memory";
13 reg = <0x80000000 0>;
14 };
15
16 reg_wlreg_on: regulator-wlreg_on {
17 compatible = "regulator-fixed";
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_reg_wlreg_on>;
20 regulator-name = "wlreg_on";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
23 gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
24 enable-active-high;
25 };
26
27 reg_2p5v: regulator-2p5v {
28 compatible = "regulator-fixed";
29 regulator-name = "2P5V";
30 regulator-min-microvolt = <2500000>;
31 regulator-max-microvolt = <2500000>;
32 regulator-always-on;
33 };
34
35 reg_3p3v: regulator-3p3v {
36 compatible = "regulator-fixed";
37 regulator-name = "3P3V";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-always-on;
41 };
42
43 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_usbotg1_pwr>;
46 compatible = "regulator-fixed";
47 regulator-name = "usb_otg1_vbus";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
51 };
52
53 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
54 compatible = "regulator-fixed";
55 regulator-name = "usb_otg2_vbus";
56 regulator-min-microvolt = <5000000>;
57 regulator-max-microvolt = <5000000>;
58 };
59
60 reg_vref_1v8: regulator-vref-1v8 {
61 compatible = "regulator-fixed";
62 regulator-name = "vref-1v8";
63 regulator-min-microvolt = <1800000>;
64 regulator-max-microvolt = <1800000>;
65 };
66
67 usdhc2_pwrseq: usdhc2_pwrseq {
68 compatible = "mmc-pwrseq-simple";
69 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
70 clock-names = "ext_clock";
71 };
72};
73
74&clks {
75 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
76 <&clks IMX7D_CLKO2_ROOT_DIV>;
77 assigned-clock-parents = <&clks IMX7D_CKIL>;
78 assigned-clock-rates = <0>, <32768>;
79};
80
81&ecspi3 {
82 cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_ecspi3>;
85 status = "okay";
86};
87
88&fec1 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_enet1>;
91 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
92 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
93 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
94 assigned-clock-rates = <0>, <100000000>;
95 phy-mode = "rgmii-id";
96 phy-handle = <ðphy0>;
97 fsl,magic-packet;
98 phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
99 status = "okay";
100
101 mdio {
102 #address-cells = <1>;
103 #size-cells = <0>;
104
105 ethphy0: ethernet-phy@1 {
106 compatible = "ethernet-phy-ieee802.3-c22";
107 reg = <1>;
108 status = "okay";
109 };
110 };
111};
112
113&flexcan1 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_can1>;
116 status = "okay";
117};
118
119&flexcan2 {
120 pinctrl-names = "default";
121 pinctrl-0 = <&pinctrl_can2>;
122 status = "okay";
123};
124
125&i2c1 {
126 clock-frequency = <100000>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c1>;
129 status = "okay";
130};
131
132&i2c2 {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_i2c2>;
135 status = "okay";
136};
137
138&i2c4 {
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c4>;
141 status = "okay";
142
143 pmic: pfuze3000@8 {
144 compatible = "fsl,pfuze3000";
145 reg = <0x08>;
146
147 regulators {
148 sw1a_reg: sw1a {
149 regulator-min-microvolt = <700000>;
150 regulator-max-microvolt = <3300000>;
151 regulator-boot-on;
152 regulator-always-on;
153 regulator-ramp-delay = <6250>;
154 };
155 /* use sw1c_reg to align with pfuze100/pfuze200 */
156 sw1c_reg: sw1b {
157 regulator-min-microvolt = <700000>;
158 regulator-max-microvolt = <1475000>;
159 regulator-boot-on;
160 regulator-always-on;
161 regulator-ramp-delay = <6250>;
162 };
163
164 sw2_reg: sw2 {
165 regulator-min-microvolt = <1800000>;
166 regulator-max-microvolt = <1850000>;
167 regulator-boot-on;
168 regulator-always-on;
169 };
170
171 sw3a_reg: sw3 {
172 regulator-min-microvolt = <900000>;
173 regulator-max-microvolt = <1650000>;
174 regulator-boot-on;
175 regulator-always-on;
176 };
177
178 swbst_reg: swbst {
179 regulator-min-microvolt = <5000000>;
180 regulator-max-microvolt = <5150000>;
181 };
182
183 snvs_reg: vsnvs {
184 regulator-min-microvolt = <1000000>;
185 regulator-max-microvolt = <3000000>;
186 regulator-boot-on;
187 regulator-always-on;
188 };
189
190 vref_reg: vrefddr {
191 regulator-boot-on;
192 regulator-always-on;
193 };
194
195 vgen1_reg: vldo1 {
196 regulator-min-microvolt = <1800000>;
197 regulator-max-microvolt = <3300000>;
198 regulator-always-on;
199 };
200
201 vgen2_reg: vldo2 {
202 regulator-min-microvolt = <800000>;
203 regulator-max-microvolt = <1550000>;
204 };
205
206 vgen3_reg: vccsd {
207 regulator-min-microvolt = <2850000>;
208 regulator-max-microvolt = <3300000>;
209 regulator-always-on;
210 };
211
212 vgen4_reg: v33 {
213 regulator-min-microvolt = <2850000>;
214 regulator-max-microvolt = <3300000>;
215 regulator-always-on;
216 };
217
218 vgen5_reg: vldo3 {
219 regulator-min-microvolt = <1800000>;
220 regulator-max-microvolt = <3300000>;
221 regulator-always-on;
222 };
223
224 vgen6_reg: vldo4 {
225 regulator-min-microvolt = <1800000>;
226 regulator-max-microvolt = <3300000>;
227 regulator-always-on;
228 };
229 };
230 };
231};
232
233&sai1 {
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_sai1>;
236 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
237 <&clks IMX7D_SAI1_ROOT_CLK>;
238 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
239 assigned-clock-rates = <0>, <24576000>;
240 status = "okay";
241};
242
243
244&pwm1 {
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_pwm1>;
247 status = "okay";
248};
249
250&pwm2 {
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_pwm2>;
253 status = "okay";
254};
255
256&pwm3 {
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_pwm3>;
259 status = "okay";
260};
261
262&pwm4 { /* Backlight */
263 status = "okay";
264};
265
266&uart5 {
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_uart5>;
269 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
270 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
271 status = "okay";
272};
273
274&uart6 {
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_uart6>;
277 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
278 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
279 uart-has-rtscts;
280 status = "okay";
281};
282
283&uart7 { /* Bluetooth */
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_uart7>;
286 assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
288 uart-has-rtscts;
289 status = "okay";
290};
291
292&usbotg1 {
293 vbus-supply = <®_usb_otg1_vbus>;
294 status = "okay";
295};
296
297&usbotg2 {
298 vbus-supply = <®_usb_otg2_vbus>;
299 dr_mode = "host";
300 status = "okay";
301};
302
303&usdhc1 {
304 pinctrl-names = "default", "state_100mhz", "state_200mhz";
305 pinctrl-0 = <&pinctrl_usdhc1>;
306 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
307 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
308 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
309 bus-width = <4>;
310 tuning-step = <2>;
311 vmmc-supply = <®_3p3v>;
312 wakeup-source;
313 no-1-8-v;
314 keep-power-in-suspend;
315 status = "okay";
316};
317
318&usdhc2 { /* Wifi SDIO */
319 pinctrl-names = "default";
320 pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
321 no-1-8-v;
322 non-removable;
323 keep-power-in-suspend;
324 wakeup-source;
325 vmmc-supply = <®_wlreg_on>;
326 mmc-pwrseq = <&usdhc2_pwrseq>;
327 status = "okay";
328};
329
330&usdhc3 {
331 pinctrl-names = "default", "state_100mhz", "state_200mhz";
332 pinctrl-0 = <&pinctrl_usdhc3>;
333 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
334 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
335 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
336 assigned-clock-rates = <400000000>;
337 bus-width = <8>;
338 no-1-8-v;
339 fsl,tuning-step = <2>;
340 non-removable;
341 status = "okay";
342};
343
344&wdog1 {
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_wdog>;
347 fsl,ext-reset-output;
348 status = "okay";
349};
350
351&iomuxc {
352 pinctrl_ecspi3: ecspi3grp {
353 fsl,pins = <
354 MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
355 MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
356 MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
357 MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
358 >;
359 };
360
361 pinctrl_i2c1: i2c1grp {
362 fsl,pins = <
363 MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
364 MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
365 >;
366 };
367
368 pinctrl_i2c2: i2c2grp {
369 fsl,pins = <
370 MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f
371 MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f
372 >;
373 };
374
375 pinctrl_enet1: enet1grp {
376 fsl,pins = <
377 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
378 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
379 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
380 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
381 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
382 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
383 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
384 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
385 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
386 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
387 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
388 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
389 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
390 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
391 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
392 >;
393 };
394
395 pinctrl_can1: can1frp {
396 fsl,pins = <
397 MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59
398 MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59
399 >;
400 };
401
402 pinctrl_can2: can2frp {
403 fsl,pins = <
404 MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59
405 MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59
406 >;
407 };
408
409 pinctrl_i2c4: i2c4grp {
410 fsl,pins = <
411 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
412 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
413 >;
414 };
415
416 pinctrl_pwm1: pwm1 {
417 fsl,pins = <
418 MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
419 >;
420 };
421
422 pinctrl_pwm2: pwm2 {
423 fsl,pins = <
424 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
425 >;
426 };
427
428 pinctrl_pwm3: pwm3 {
429 fsl,pins = <
430 MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
431 >;
432 };
433
434 pinctrl_reg_wlreg_on: regregongrp {
435 fsl,pins = <
436 MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
437 >;
438 };
439
440 pinctrl_sai1: sai1grp {
441 fsl,pins = <
442 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
443 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
444 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
445 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
446 >;
447 };
448
449 pinctrl_uart5: uart5grp {
450 fsl,pins = <
451 MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
452 MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
453 >;
454 };
455
456 pinctrl_uart6: uart6grp {
457 fsl,pins = <
458 MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79
459 MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79
460 MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79
461 MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79
462 >;
463 };
464
465 pinctrl_uart7: uart7grp {
466 fsl,pins = <
467 MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79
468 MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79
469 MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79
470 MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79
471 >;
472 };
473
474 pinctrl_usbotg1_pwr: usbotg_pwr {
475 fsl,pins = <
476 MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
477 >;
478 };
479
480 pinctrl_usdhc1: usdhc1grp {
481 fsl,pins = <
482 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
483 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
484 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
485 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
486 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
487 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
488 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
489 >;
490 };
491
492 pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
493 fsl,pins = <
494 MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
495 MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
496 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
497 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
498 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
499 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
500 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
501 >;
502 };
503
504 pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
505 fsl,pins = <
506 MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
507 MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
508 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
509 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
510 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
511 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
512 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
513 >;
514 };
515
516 pinctrl_usdhc2: usdhc2grp {
517 fsl,pins = <
518 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
519 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
520 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
521 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
522 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
523 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
524 >;
525 };
526
527 pinctrl_usdhc3: usdhc3grp {
528 fsl,pins = <
529 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
530 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
531 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
532 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
533 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
534 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
535 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
536 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
537 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
538 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
539 >;
540 };
541
542 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
543 fsl,pins = <
544 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
545 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
546 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
547 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
548 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
549 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
550 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
551 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
552 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
553 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
554 >;
555 };
556
557 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
558 fsl,pins = <
559 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
560 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
561 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
562 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
563 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
564 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
565 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
566 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
567 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
568 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
569 >;
570 };
571};
572
573&iomuxc_lpsr {
574 pinctrl_wifi_clk: wificlkgrp {
575 fsl,pins = <
576 MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d
577 >;
578 };
579
580 pinctrl_wdog: wdoggrp {
581 fsl,pins = <
582 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
583 >;
584 };
585};