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1#undef DEBUG
2
3/*
4 * ARM performance counter support.
5 *
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
8 *
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code.
11 */
12#define pr_fmt(fmt) "hw perfevents: " fmt
13
14#include <linux/bitmap.h>
15#include <linux/cpumask.h>
16#include <linux/cpu_pm.h>
17#include <linux/export.h>
18#include <linux/kernel.h>
19#include <linux/perf/arm_pmu.h>
20#include <linux/slab.h>
21#include <linux/sched/clock.h>
22#include <linux/spinlock.h>
23#include <linux/irq.h>
24#include <linux/irqdesc.h>
25
26#include <asm/irq_regs.h>
27
28static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
29static DEFINE_PER_CPU(int, cpu_irq);
30
31static int
32armpmu_map_cache_event(const unsigned (*cache_map)
33 [PERF_COUNT_HW_CACHE_MAX]
34 [PERF_COUNT_HW_CACHE_OP_MAX]
35 [PERF_COUNT_HW_CACHE_RESULT_MAX],
36 u64 config)
37{
38 unsigned int cache_type, cache_op, cache_result, ret;
39
40 cache_type = (config >> 0) & 0xff;
41 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
42 return -EINVAL;
43
44 cache_op = (config >> 8) & 0xff;
45 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
46 return -EINVAL;
47
48 cache_result = (config >> 16) & 0xff;
49 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
50 return -EINVAL;
51
52 if (!cache_map)
53 return -ENOENT;
54
55 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
56
57 if (ret == CACHE_OP_UNSUPPORTED)
58 return -ENOENT;
59
60 return ret;
61}
62
63static int
64armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
65{
66 int mapping;
67
68 if (config >= PERF_COUNT_HW_MAX)
69 return -EINVAL;
70
71 if (!event_map)
72 return -ENOENT;
73
74 mapping = (*event_map)[config];
75 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
76}
77
78static int
79armpmu_map_raw_event(u32 raw_event_mask, u64 config)
80{
81 return (int)(config & raw_event_mask);
82}
83
84int
85armpmu_map_event(struct perf_event *event,
86 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
87 const unsigned (*cache_map)
88 [PERF_COUNT_HW_CACHE_MAX]
89 [PERF_COUNT_HW_CACHE_OP_MAX]
90 [PERF_COUNT_HW_CACHE_RESULT_MAX],
91 u32 raw_event_mask)
92{
93 u64 config = event->attr.config;
94 int type = event->attr.type;
95
96 if (type == event->pmu->type)
97 return armpmu_map_raw_event(raw_event_mask, config);
98
99 switch (type) {
100 case PERF_TYPE_HARDWARE:
101 return armpmu_map_hw_event(event_map, config);
102 case PERF_TYPE_HW_CACHE:
103 return armpmu_map_cache_event(cache_map, config);
104 case PERF_TYPE_RAW:
105 return armpmu_map_raw_event(raw_event_mask, config);
106 }
107
108 return -ENOENT;
109}
110
111int armpmu_event_set_period(struct perf_event *event)
112{
113 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
114 struct hw_perf_event *hwc = &event->hw;
115 s64 left = local64_read(&hwc->period_left);
116 s64 period = hwc->sample_period;
117 int ret = 0;
118
119 if (unlikely(left <= -period)) {
120 left = period;
121 local64_set(&hwc->period_left, left);
122 hwc->last_period = period;
123 ret = 1;
124 }
125
126 if (unlikely(left <= 0)) {
127 left += period;
128 local64_set(&hwc->period_left, left);
129 hwc->last_period = period;
130 ret = 1;
131 }
132
133 /*
134 * Limit the maximum period to prevent the counter value
135 * from overtaking the one we are about to program. In
136 * effect we are reducing max_period to account for
137 * interrupt latency (and we are being very conservative).
138 */
139 if (left > (armpmu->max_period >> 1))
140 left = armpmu->max_period >> 1;
141
142 local64_set(&hwc->prev_count, (u64)-left);
143
144 armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
145
146 perf_event_update_userpage(event);
147
148 return ret;
149}
150
151u64 armpmu_event_update(struct perf_event *event)
152{
153 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
154 struct hw_perf_event *hwc = &event->hw;
155 u64 delta, prev_raw_count, new_raw_count;
156
157again:
158 prev_raw_count = local64_read(&hwc->prev_count);
159 new_raw_count = armpmu->read_counter(event);
160
161 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
162 new_raw_count) != prev_raw_count)
163 goto again;
164
165 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
166
167 local64_add(delta, &event->count);
168 local64_sub(delta, &hwc->period_left);
169
170 return new_raw_count;
171}
172
173static void
174armpmu_read(struct perf_event *event)
175{
176 armpmu_event_update(event);
177}
178
179static void
180armpmu_stop(struct perf_event *event, int flags)
181{
182 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
183 struct hw_perf_event *hwc = &event->hw;
184
185 /*
186 * ARM pmu always has to update the counter, so ignore
187 * PERF_EF_UPDATE, see comments in armpmu_start().
188 */
189 if (!(hwc->state & PERF_HES_STOPPED)) {
190 armpmu->disable(event);
191 armpmu_event_update(event);
192 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
193 }
194}
195
196static void armpmu_start(struct perf_event *event, int flags)
197{
198 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
199 struct hw_perf_event *hwc = &event->hw;
200
201 /*
202 * ARM pmu always has to reprogram the period, so ignore
203 * PERF_EF_RELOAD, see the comment below.
204 */
205 if (flags & PERF_EF_RELOAD)
206 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
207
208 hwc->state = 0;
209 /*
210 * Set the period again. Some counters can't be stopped, so when we
211 * were stopped we simply disabled the IRQ source and the counter
212 * may have been left counting. If we don't do this step then we may
213 * get an interrupt too soon or *way* too late if the overflow has
214 * happened since disabling.
215 */
216 armpmu_event_set_period(event);
217 armpmu->enable(event);
218}
219
220static void
221armpmu_del(struct perf_event *event, int flags)
222{
223 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
224 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
225 struct hw_perf_event *hwc = &event->hw;
226 int idx = hwc->idx;
227
228 armpmu_stop(event, PERF_EF_UPDATE);
229 hw_events->events[idx] = NULL;
230 clear_bit(idx, hw_events->used_mask);
231 if (armpmu->clear_event_idx)
232 armpmu->clear_event_idx(hw_events, event);
233
234 perf_event_update_userpage(event);
235}
236
237static int
238armpmu_add(struct perf_event *event, int flags)
239{
240 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
241 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
242 struct hw_perf_event *hwc = &event->hw;
243 int idx;
244
245 /* An event following a process won't be stopped earlier */
246 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
247 return -ENOENT;
248
249 /* If we don't have a space for the counter then finish early. */
250 idx = armpmu->get_event_idx(hw_events, event);
251 if (idx < 0)
252 return idx;
253
254 /*
255 * If there is an event in the counter we are going to use then make
256 * sure it is disabled.
257 */
258 event->hw.idx = idx;
259 armpmu->disable(event);
260 hw_events->events[idx] = event;
261
262 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
263 if (flags & PERF_EF_START)
264 armpmu_start(event, PERF_EF_RELOAD);
265
266 /* Propagate our changes to the userspace mapping. */
267 perf_event_update_userpage(event);
268
269 return 0;
270}
271
272static int
273validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
274 struct perf_event *event)
275{
276 struct arm_pmu *armpmu;
277
278 if (is_software_event(event))
279 return 1;
280
281 /*
282 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
283 * core perf code won't check that the pmu->ctx == leader->ctx
284 * until after pmu->event_init(event).
285 */
286 if (event->pmu != pmu)
287 return 0;
288
289 if (event->state < PERF_EVENT_STATE_OFF)
290 return 1;
291
292 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
293 return 1;
294
295 armpmu = to_arm_pmu(event->pmu);
296 return armpmu->get_event_idx(hw_events, event) >= 0;
297}
298
299static int
300validate_group(struct perf_event *event)
301{
302 struct perf_event *sibling, *leader = event->group_leader;
303 struct pmu_hw_events fake_pmu;
304
305 /*
306 * Initialise the fake PMU. We only need to populate the
307 * used_mask for the purposes of validation.
308 */
309 memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
310
311 if (!validate_event(event->pmu, &fake_pmu, leader))
312 return -EINVAL;
313
314 for_each_sibling_event(sibling, leader) {
315 if (!validate_event(event->pmu, &fake_pmu, sibling))
316 return -EINVAL;
317 }
318
319 if (!validate_event(event->pmu, &fake_pmu, event))
320 return -EINVAL;
321
322 return 0;
323}
324
325static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
326{
327 struct arm_pmu *armpmu;
328 int ret;
329 u64 start_clock, finish_clock;
330
331 /*
332 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
333 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
334 * do any necessary shifting, we just need to perform the first
335 * dereference.
336 */
337 armpmu = *(void **)dev;
338 if (WARN_ON_ONCE(!armpmu))
339 return IRQ_NONE;
340
341 start_clock = sched_clock();
342 ret = armpmu->handle_irq(irq, armpmu);
343 finish_clock = sched_clock();
344
345 perf_sample_event_took(finish_clock - start_clock);
346 return ret;
347}
348
349static int
350event_requires_mode_exclusion(struct perf_event_attr *attr)
351{
352 return attr->exclude_idle || attr->exclude_user ||
353 attr->exclude_kernel || attr->exclude_hv;
354}
355
356static int
357__hw_perf_event_init(struct perf_event *event)
358{
359 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
360 struct hw_perf_event *hwc = &event->hw;
361 int mapping;
362
363 mapping = armpmu->map_event(event);
364
365 if (mapping < 0) {
366 pr_debug("event %x:%llx not supported\n", event->attr.type,
367 event->attr.config);
368 return mapping;
369 }
370
371 /*
372 * We don't assign an index until we actually place the event onto
373 * hardware. Use -1 to signify that we haven't decided where to put it
374 * yet. For SMP systems, each core has it's own PMU so we can't do any
375 * clever allocation or constraints checking at this point.
376 */
377 hwc->idx = -1;
378 hwc->config_base = 0;
379 hwc->config = 0;
380 hwc->event_base = 0;
381
382 /*
383 * Check whether we need to exclude the counter from certain modes.
384 */
385 if ((!armpmu->set_event_filter ||
386 armpmu->set_event_filter(hwc, &event->attr)) &&
387 event_requires_mode_exclusion(&event->attr)) {
388 pr_debug("ARM performance counters do not support "
389 "mode exclusion\n");
390 return -EOPNOTSUPP;
391 }
392
393 /*
394 * Store the event encoding into the config_base field.
395 */
396 hwc->config_base |= (unsigned long)mapping;
397
398 if (!is_sampling_event(event)) {
399 /*
400 * For non-sampling runs, limit the sample_period to half
401 * of the counter width. That way, the new counter value
402 * is far less likely to overtake the previous one unless
403 * you have some serious IRQ latency issues.
404 */
405 hwc->sample_period = armpmu->max_period >> 1;
406 hwc->last_period = hwc->sample_period;
407 local64_set(&hwc->period_left, hwc->sample_period);
408 }
409
410 if (event->group_leader != event) {
411 if (validate_group(event) != 0)
412 return -EINVAL;
413 }
414
415 return 0;
416}
417
418static int armpmu_event_init(struct perf_event *event)
419{
420 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
421
422 /*
423 * Reject CPU-affine events for CPUs that are of a different class to
424 * that which this PMU handles. Process-following events (where
425 * event->cpu == -1) can be migrated between CPUs, and thus we have to
426 * reject them later (in armpmu_add) if they're scheduled on a
427 * different class of CPU.
428 */
429 if (event->cpu != -1 &&
430 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
431 return -ENOENT;
432
433 /* does not support taken branch sampling */
434 if (has_branch_stack(event))
435 return -EOPNOTSUPP;
436
437 if (armpmu->map_event(event) == -ENOENT)
438 return -ENOENT;
439
440 return __hw_perf_event_init(event);
441}
442
443static void armpmu_enable(struct pmu *pmu)
444{
445 struct arm_pmu *armpmu = to_arm_pmu(pmu);
446 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
447 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
448
449 /* For task-bound events we may be called on other CPUs */
450 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
451 return;
452
453 if (enabled)
454 armpmu->start(armpmu);
455}
456
457static void armpmu_disable(struct pmu *pmu)
458{
459 struct arm_pmu *armpmu = to_arm_pmu(pmu);
460
461 /* For task-bound events we may be called on other CPUs */
462 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
463 return;
464
465 armpmu->stop(armpmu);
466}
467
468/*
469 * In heterogeneous systems, events are specific to a particular
470 * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
471 * the same microarchitecture.
472 */
473static int armpmu_filter_match(struct perf_event *event)
474{
475 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
476 unsigned int cpu = smp_processor_id();
477 return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
478}
479
480static ssize_t armpmu_cpumask_show(struct device *dev,
481 struct device_attribute *attr, char *buf)
482{
483 struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
484 return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
485}
486
487static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
488
489static struct attribute *armpmu_common_attrs[] = {
490 &dev_attr_cpus.attr,
491 NULL,
492};
493
494static struct attribute_group armpmu_common_attr_group = {
495 .attrs = armpmu_common_attrs,
496};
497
498/* Set at runtime when we know what CPU type we are. */
499static struct arm_pmu *__oprofile_cpu_pmu;
500
501/*
502 * Despite the names, these two functions are CPU-specific and are used
503 * by the OProfile/perf code.
504 */
505const char *perf_pmu_name(void)
506{
507 if (!__oprofile_cpu_pmu)
508 return NULL;
509
510 return __oprofile_cpu_pmu->name;
511}
512EXPORT_SYMBOL_GPL(perf_pmu_name);
513
514int perf_num_counters(void)
515{
516 int max_events = 0;
517
518 if (__oprofile_cpu_pmu != NULL)
519 max_events = __oprofile_cpu_pmu->num_events;
520
521 return max_events;
522}
523EXPORT_SYMBOL_GPL(perf_num_counters);
524
525static int armpmu_count_irq_users(const int irq)
526{
527 int cpu, count = 0;
528
529 for_each_possible_cpu(cpu) {
530 if (per_cpu(cpu_irq, cpu) == irq)
531 count++;
532 }
533
534 return count;
535}
536
537void armpmu_free_irq(int irq, int cpu)
538{
539 if (per_cpu(cpu_irq, cpu) == 0)
540 return;
541 if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
542 return;
543
544 if (!irq_is_percpu_devid(irq))
545 free_irq(irq, per_cpu_ptr(&cpu_armpmu, cpu));
546 else if (armpmu_count_irq_users(irq) == 1)
547 free_percpu_irq(irq, &cpu_armpmu);
548
549 per_cpu(cpu_irq, cpu) = 0;
550}
551
552int armpmu_request_irq(int irq, int cpu)
553{
554 int err = 0;
555 const irq_handler_t handler = armpmu_dispatch_irq;
556 if (!irq)
557 return 0;
558
559 if (!irq_is_percpu_devid(irq)) {
560 unsigned long irq_flags;
561
562 err = irq_force_affinity(irq, cpumask_of(cpu));
563
564 if (err && num_possible_cpus() > 1) {
565 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
566 irq, cpu);
567 goto err_out;
568 }
569
570 irq_flags = IRQF_PERCPU |
571 IRQF_NOBALANCING |
572 IRQF_NO_THREAD;
573
574 irq_set_status_flags(irq, IRQ_NOAUTOEN);
575 err = request_irq(irq, handler, irq_flags, "arm-pmu",
576 per_cpu_ptr(&cpu_armpmu, cpu));
577 } else if (armpmu_count_irq_users(irq) == 0) {
578 err = request_percpu_irq(irq, handler, "arm-pmu",
579 &cpu_armpmu);
580 }
581
582 if (err)
583 goto err_out;
584
585 per_cpu(cpu_irq, cpu) = irq;
586 return 0;
587
588err_out:
589 pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
590 return err;
591}
592
593static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
594{
595 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
596 return per_cpu(hw_events->irq, cpu);
597}
598
599/*
600 * PMU hardware loses all context when a CPU goes offline.
601 * When a CPU is hotplugged back in, since some hardware registers are
602 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
603 * junk values out of them.
604 */
605static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
606{
607 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
608 int irq;
609
610 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
611 return 0;
612 if (pmu->reset)
613 pmu->reset(pmu);
614
615 per_cpu(cpu_armpmu, cpu) = pmu;
616
617 irq = armpmu_get_cpu_irq(pmu, cpu);
618 if (irq) {
619 if (irq_is_percpu_devid(irq))
620 enable_percpu_irq(irq, IRQ_TYPE_NONE);
621 else
622 enable_irq(irq);
623 }
624
625 return 0;
626}
627
628static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
629{
630 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
631 int irq;
632
633 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
634 return 0;
635
636 irq = armpmu_get_cpu_irq(pmu, cpu);
637 if (irq) {
638 if (irq_is_percpu_devid(irq))
639 disable_percpu_irq(irq);
640 else
641 disable_irq_nosync(irq);
642 }
643
644 per_cpu(cpu_armpmu, cpu) = NULL;
645
646 return 0;
647}
648
649#ifdef CONFIG_CPU_PM
650static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
651{
652 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
653 struct perf_event *event;
654 int idx;
655
656 for (idx = 0; idx < armpmu->num_events; idx++) {
657 /*
658 * If the counter is not used skip it, there is no
659 * need of stopping/restarting it.
660 */
661 if (!test_bit(idx, hw_events->used_mask))
662 continue;
663
664 event = hw_events->events[idx];
665
666 switch (cmd) {
667 case CPU_PM_ENTER:
668 /*
669 * Stop and update the counter
670 */
671 armpmu_stop(event, PERF_EF_UPDATE);
672 break;
673 case CPU_PM_EXIT:
674 case CPU_PM_ENTER_FAILED:
675 /*
676 * Restore and enable the counter.
677 * armpmu_start() indirectly calls
678 *
679 * perf_event_update_userpage()
680 *
681 * that requires RCU read locking to be functional,
682 * wrap the call within RCU_NONIDLE to make the
683 * RCU subsystem aware this cpu is not idle from
684 * an RCU perspective for the armpmu_start() call
685 * duration.
686 */
687 RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
688 break;
689 default:
690 break;
691 }
692 }
693}
694
695static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
696 void *v)
697{
698 struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
699 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
700 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
701
702 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
703 return NOTIFY_DONE;
704
705 /*
706 * Always reset the PMU registers on power-up even if
707 * there are no events running.
708 */
709 if (cmd == CPU_PM_EXIT && armpmu->reset)
710 armpmu->reset(armpmu);
711
712 if (!enabled)
713 return NOTIFY_OK;
714
715 switch (cmd) {
716 case CPU_PM_ENTER:
717 armpmu->stop(armpmu);
718 cpu_pm_pmu_setup(armpmu, cmd);
719 break;
720 case CPU_PM_EXIT:
721 cpu_pm_pmu_setup(armpmu, cmd);
722 case CPU_PM_ENTER_FAILED:
723 armpmu->start(armpmu);
724 break;
725 default:
726 return NOTIFY_DONE;
727 }
728
729 return NOTIFY_OK;
730}
731
732static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
733{
734 cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
735 return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
736}
737
738static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
739{
740 cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
741}
742#else
743static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
744static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
745#endif
746
747static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
748{
749 int err;
750
751 err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
752 &cpu_pmu->node);
753 if (err)
754 goto out;
755
756 err = cpu_pm_pmu_register(cpu_pmu);
757 if (err)
758 goto out_unregister;
759
760 return 0;
761
762out_unregister:
763 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
764 &cpu_pmu->node);
765out:
766 return err;
767}
768
769static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
770{
771 cpu_pm_pmu_unregister(cpu_pmu);
772 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
773 &cpu_pmu->node);
774}
775
776static struct arm_pmu *__armpmu_alloc(gfp_t flags)
777{
778 struct arm_pmu *pmu;
779 int cpu;
780
781 pmu = kzalloc(sizeof(*pmu), flags);
782 if (!pmu) {
783 pr_info("failed to allocate PMU device!\n");
784 goto out;
785 }
786
787 pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags);
788 if (!pmu->hw_events) {
789 pr_info("failed to allocate per-cpu PMU data.\n");
790 goto out_free_pmu;
791 }
792
793 pmu->pmu = (struct pmu) {
794 .pmu_enable = armpmu_enable,
795 .pmu_disable = armpmu_disable,
796 .event_init = armpmu_event_init,
797 .add = armpmu_add,
798 .del = armpmu_del,
799 .start = armpmu_start,
800 .stop = armpmu_stop,
801 .read = armpmu_read,
802 .filter_match = armpmu_filter_match,
803 .attr_groups = pmu->attr_groups,
804 /*
805 * This is a CPU PMU potentially in a heterogeneous
806 * configuration (e.g. big.LITTLE). This is not an uncore PMU,
807 * and we have taken ctx sharing into account (e.g. with our
808 * pmu::filter_match callback and pmu::event_init group
809 * validation).
810 */
811 .capabilities = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
812 };
813
814 pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
815 &armpmu_common_attr_group;
816
817 for_each_possible_cpu(cpu) {
818 struct pmu_hw_events *events;
819
820 events = per_cpu_ptr(pmu->hw_events, cpu);
821 raw_spin_lock_init(&events->pmu_lock);
822 events->percpu_pmu = pmu;
823 }
824
825 return pmu;
826
827out_free_pmu:
828 kfree(pmu);
829out:
830 return NULL;
831}
832
833struct arm_pmu *armpmu_alloc(void)
834{
835 return __armpmu_alloc(GFP_KERNEL);
836}
837
838struct arm_pmu *armpmu_alloc_atomic(void)
839{
840 return __armpmu_alloc(GFP_ATOMIC);
841}
842
843
844void armpmu_free(struct arm_pmu *pmu)
845{
846 free_percpu(pmu->hw_events);
847 kfree(pmu);
848}
849
850int armpmu_register(struct arm_pmu *pmu)
851{
852 int ret;
853
854 ret = cpu_pmu_init(pmu);
855 if (ret)
856 return ret;
857
858 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
859 if (ret)
860 goto out_destroy;
861
862 if (!__oprofile_cpu_pmu)
863 __oprofile_cpu_pmu = pmu;
864
865 pr_info("enabled with %s PMU driver, %d counters available\n",
866 pmu->name, pmu->num_events);
867
868 return 0;
869
870out_destroy:
871 cpu_pmu_destroy(pmu);
872 return ret;
873}
874
875static int arm_pmu_hp_init(void)
876{
877 int ret;
878
879 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
880 "perf/arm/pmu:starting",
881 arm_perf_starting_cpu,
882 arm_perf_teardown_cpu);
883 if (ret)
884 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
885 ret);
886 return ret;
887}
888subsys_initcall(arm_pmu_hp_init);
1// SPDX-License-Identifier: GPL-2.0-only
2#undef DEBUG
3
4/*
5 * ARM performance counter support.
6 *
7 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
8 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 *
10 * This code is based on the sparc64 perf event code, which is in turn based
11 * on the x86 code.
12 */
13#define pr_fmt(fmt) "hw perfevents: " fmt
14
15#include <linux/bitmap.h>
16#include <linux/cpumask.h>
17#include <linux/cpu_pm.h>
18#include <linux/export.h>
19#include <linux/kernel.h>
20#include <linux/perf/arm_pmu.h>
21#include <linux/slab.h>
22#include <linux/sched/clock.h>
23#include <linux/spinlock.h>
24#include <linux/irq.h>
25#include <linux/irqdesc.h>
26
27#include <asm/irq_regs.h>
28
29static int armpmu_count_irq_users(const int irq);
30
31struct pmu_irq_ops {
32 void (*enable_pmuirq)(unsigned int irq);
33 void (*disable_pmuirq)(unsigned int irq);
34 void (*free_pmuirq)(unsigned int irq, int cpu, void __percpu *devid);
35};
36
37static void armpmu_free_pmuirq(unsigned int irq, int cpu, void __percpu *devid)
38{
39 free_irq(irq, per_cpu_ptr(devid, cpu));
40}
41
42static const struct pmu_irq_ops pmuirq_ops = {
43 .enable_pmuirq = enable_irq,
44 .disable_pmuirq = disable_irq_nosync,
45 .free_pmuirq = armpmu_free_pmuirq
46};
47
48static void armpmu_free_pmunmi(unsigned int irq, int cpu, void __percpu *devid)
49{
50 free_nmi(irq, per_cpu_ptr(devid, cpu));
51}
52
53static const struct pmu_irq_ops pmunmi_ops = {
54 .enable_pmuirq = enable_nmi,
55 .disable_pmuirq = disable_nmi_nosync,
56 .free_pmuirq = armpmu_free_pmunmi
57};
58
59static void armpmu_enable_percpu_pmuirq(unsigned int irq)
60{
61 enable_percpu_irq(irq, IRQ_TYPE_NONE);
62}
63
64static void armpmu_free_percpu_pmuirq(unsigned int irq, int cpu,
65 void __percpu *devid)
66{
67 if (armpmu_count_irq_users(irq) == 1)
68 free_percpu_irq(irq, devid);
69}
70
71static const struct pmu_irq_ops percpu_pmuirq_ops = {
72 .enable_pmuirq = armpmu_enable_percpu_pmuirq,
73 .disable_pmuirq = disable_percpu_irq,
74 .free_pmuirq = armpmu_free_percpu_pmuirq
75};
76
77static void armpmu_enable_percpu_pmunmi(unsigned int irq)
78{
79 if (!prepare_percpu_nmi(irq))
80 enable_percpu_nmi(irq, IRQ_TYPE_NONE);
81}
82
83static void armpmu_disable_percpu_pmunmi(unsigned int irq)
84{
85 disable_percpu_nmi(irq);
86 teardown_percpu_nmi(irq);
87}
88
89static void armpmu_free_percpu_pmunmi(unsigned int irq, int cpu,
90 void __percpu *devid)
91{
92 if (armpmu_count_irq_users(irq) == 1)
93 free_percpu_nmi(irq, devid);
94}
95
96static const struct pmu_irq_ops percpu_pmunmi_ops = {
97 .enable_pmuirq = armpmu_enable_percpu_pmunmi,
98 .disable_pmuirq = armpmu_disable_percpu_pmunmi,
99 .free_pmuirq = armpmu_free_percpu_pmunmi
100};
101
102static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
103static DEFINE_PER_CPU(int, cpu_irq);
104static DEFINE_PER_CPU(const struct pmu_irq_ops *, cpu_irq_ops);
105
106static bool has_nmi;
107
108static inline u64 arm_pmu_event_max_period(struct perf_event *event)
109{
110 if (event->hw.flags & ARMPMU_EVT_64BIT)
111 return GENMASK_ULL(63, 0);
112 else
113 return GENMASK_ULL(31, 0);
114}
115
116static int
117armpmu_map_cache_event(const unsigned (*cache_map)
118 [PERF_COUNT_HW_CACHE_MAX]
119 [PERF_COUNT_HW_CACHE_OP_MAX]
120 [PERF_COUNT_HW_CACHE_RESULT_MAX],
121 u64 config)
122{
123 unsigned int cache_type, cache_op, cache_result, ret;
124
125 cache_type = (config >> 0) & 0xff;
126 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
127 return -EINVAL;
128
129 cache_op = (config >> 8) & 0xff;
130 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
131 return -EINVAL;
132
133 cache_result = (config >> 16) & 0xff;
134 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
135 return -EINVAL;
136
137 if (!cache_map)
138 return -ENOENT;
139
140 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
141
142 if (ret == CACHE_OP_UNSUPPORTED)
143 return -ENOENT;
144
145 return ret;
146}
147
148static int
149armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
150{
151 int mapping;
152
153 if (config >= PERF_COUNT_HW_MAX)
154 return -EINVAL;
155
156 if (!event_map)
157 return -ENOENT;
158
159 mapping = (*event_map)[config];
160 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
161}
162
163static int
164armpmu_map_raw_event(u32 raw_event_mask, u64 config)
165{
166 return (int)(config & raw_event_mask);
167}
168
169int
170armpmu_map_event(struct perf_event *event,
171 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
172 const unsigned (*cache_map)
173 [PERF_COUNT_HW_CACHE_MAX]
174 [PERF_COUNT_HW_CACHE_OP_MAX]
175 [PERF_COUNT_HW_CACHE_RESULT_MAX],
176 u32 raw_event_mask)
177{
178 u64 config = event->attr.config;
179 int type = event->attr.type;
180
181 if (type == event->pmu->type)
182 return armpmu_map_raw_event(raw_event_mask, config);
183
184 switch (type) {
185 case PERF_TYPE_HARDWARE:
186 return armpmu_map_hw_event(event_map, config);
187 case PERF_TYPE_HW_CACHE:
188 return armpmu_map_cache_event(cache_map, config);
189 case PERF_TYPE_RAW:
190 return armpmu_map_raw_event(raw_event_mask, config);
191 }
192
193 return -ENOENT;
194}
195
196int armpmu_event_set_period(struct perf_event *event)
197{
198 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
199 struct hw_perf_event *hwc = &event->hw;
200 s64 left = local64_read(&hwc->period_left);
201 s64 period = hwc->sample_period;
202 u64 max_period;
203 int ret = 0;
204
205 max_period = arm_pmu_event_max_period(event);
206 if (unlikely(left <= -period)) {
207 left = period;
208 local64_set(&hwc->period_left, left);
209 hwc->last_period = period;
210 ret = 1;
211 }
212
213 if (unlikely(left <= 0)) {
214 left += period;
215 local64_set(&hwc->period_left, left);
216 hwc->last_period = period;
217 ret = 1;
218 }
219
220 /*
221 * Limit the maximum period to prevent the counter value
222 * from overtaking the one we are about to program. In
223 * effect we are reducing max_period to account for
224 * interrupt latency (and we are being very conservative).
225 */
226 if (left > (max_period >> 1))
227 left = (max_period >> 1);
228
229 local64_set(&hwc->prev_count, (u64)-left);
230
231 armpmu->write_counter(event, (u64)(-left) & max_period);
232
233 perf_event_update_userpage(event);
234
235 return ret;
236}
237
238u64 armpmu_event_update(struct perf_event *event)
239{
240 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
241 struct hw_perf_event *hwc = &event->hw;
242 u64 delta, prev_raw_count, new_raw_count;
243 u64 max_period = arm_pmu_event_max_period(event);
244
245again:
246 prev_raw_count = local64_read(&hwc->prev_count);
247 new_raw_count = armpmu->read_counter(event);
248
249 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
250 new_raw_count) != prev_raw_count)
251 goto again;
252
253 delta = (new_raw_count - prev_raw_count) & max_period;
254
255 local64_add(delta, &event->count);
256 local64_sub(delta, &hwc->period_left);
257
258 return new_raw_count;
259}
260
261static void
262armpmu_read(struct perf_event *event)
263{
264 armpmu_event_update(event);
265}
266
267static void
268armpmu_stop(struct perf_event *event, int flags)
269{
270 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
271 struct hw_perf_event *hwc = &event->hw;
272
273 /*
274 * ARM pmu always has to update the counter, so ignore
275 * PERF_EF_UPDATE, see comments in armpmu_start().
276 */
277 if (!(hwc->state & PERF_HES_STOPPED)) {
278 armpmu->disable(event);
279 armpmu_event_update(event);
280 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
281 }
282}
283
284static void armpmu_start(struct perf_event *event, int flags)
285{
286 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
287 struct hw_perf_event *hwc = &event->hw;
288
289 /*
290 * ARM pmu always has to reprogram the period, so ignore
291 * PERF_EF_RELOAD, see the comment below.
292 */
293 if (flags & PERF_EF_RELOAD)
294 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
295
296 hwc->state = 0;
297 /*
298 * Set the period again. Some counters can't be stopped, so when we
299 * were stopped we simply disabled the IRQ source and the counter
300 * may have been left counting. If we don't do this step then we may
301 * get an interrupt too soon or *way* too late if the overflow has
302 * happened since disabling.
303 */
304 armpmu_event_set_period(event);
305 armpmu->enable(event);
306}
307
308static void
309armpmu_del(struct perf_event *event, int flags)
310{
311 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
312 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
313 struct hw_perf_event *hwc = &event->hw;
314 int idx = hwc->idx;
315
316 armpmu_stop(event, PERF_EF_UPDATE);
317 hw_events->events[idx] = NULL;
318 armpmu->clear_event_idx(hw_events, event);
319 perf_event_update_userpage(event);
320 /* Clear the allocated counter */
321 hwc->idx = -1;
322}
323
324static int
325armpmu_add(struct perf_event *event, int flags)
326{
327 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
328 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
329 struct hw_perf_event *hwc = &event->hw;
330 int idx;
331
332 /* An event following a process won't be stopped earlier */
333 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
334 return -ENOENT;
335
336 /* If we don't have a space for the counter then finish early. */
337 idx = armpmu->get_event_idx(hw_events, event);
338 if (idx < 0)
339 return idx;
340
341 /*
342 * If there is an event in the counter we are going to use then make
343 * sure it is disabled.
344 */
345 event->hw.idx = idx;
346 armpmu->disable(event);
347 hw_events->events[idx] = event;
348
349 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
350 if (flags & PERF_EF_START)
351 armpmu_start(event, PERF_EF_RELOAD);
352
353 /* Propagate our changes to the userspace mapping. */
354 perf_event_update_userpage(event);
355
356 return 0;
357}
358
359static int
360validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
361 struct perf_event *event)
362{
363 struct arm_pmu *armpmu;
364
365 if (is_software_event(event))
366 return 1;
367
368 /*
369 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
370 * core perf code won't check that the pmu->ctx == leader->ctx
371 * until after pmu->event_init(event).
372 */
373 if (event->pmu != pmu)
374 return 0;
375
376 if (event->state < PERF_EVENT_STATE_OFF)
377 return 1;
378
379 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
380 return 1;
381
382 armpmu = to_arm_pmu(event->pmu);
383 return armpmu->get_event_idx(hw_events, event) >= 0;
384}
385
386static int
387validate_group(struct perf_event *event)
388{
389 struct perf_event *sibling, *leader = event->group_leader;
390 struct pmu_hw_events fake_pmu;
391
392 /*
393 * Initialise the fake PMU. We only need to populate the
394 * used_mask for the purposes of validation.
395 */
396 memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
397
398 if (!validate_event(event->pmu, &fake_pmu, leader))
399 return -EINVAL;
400
401 for_each_sibling_event(sibling, leader) {
402 if (!validate_event(event->pmu, &fake_pmu, sibling))
403 return -EINVAL;
404 }
405
406 if (!validate_event(event->pmu, &fake_pmu, event))
407 return -EINVAL;
408
409 return 0;
410}
411
412static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
413{
414 struct arm_pmu *armpmu;
415 int ret;
416 u64 start_clock, finish_clock;
417
418 /*
419 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
420 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
421 * do any necessary shifting, we just need to perform the first
422 * dereference.
423 */
424 armpmu = *(void **)dev;
425 if (WARN_ON_ONCE(!armpmu))
426 return IRQ_NONE;
427
428 start_clock = sched_clock();
429 ret = armpmu->handle_irq(armpmu);
430 finish_clock = sched_clock();
431
432 perf_sample_event_took(finish_clock - start_clock);
433 return ret;
434}
435
436static int
437__hw_perf_event_init(struct perf_event *event)
438{
439 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
440 struct hw_perf_event *hwc = &event->hw;
441 int mapping;
442
443 hwc->flags = 0;
444 mapping = armpmu->map_event(event);
445
446 if (mapping < 0) {
447 pr_debug("event %x:%llx not supported\n", event->attr.type,
448 event->attr.config);
449 return mapping;
450 }
451
452 /*
453 * We don't assign an index until we actually place the event onto
454 * hardware. Use -1 to signify that we haven't decided where to put it
455 * yet. For SMP systems, each core has it's own PMU so we can't do any
456 * clever allocation or constraints checking at this point.
457 */
458 hwc->idx = -1;
459 hwc->config_base = 0;
460 hwc->config = 0;
461 hwc->event_base = 0;
462
463 /*
464 * Check whether we need to exclude the counter from certain modes.
465 */
466 if (armpmu->set_event_filter &&
467 armpmu->set_event_filter(hwc, &event->attr)) {
468 pr_debug("ARM performance counters do not support "
469 "mode exclusion\n");
470 return -EOPNOTSUPP;
471 }
472
473 /*
474 * Store the event encoding into the config_base field.
475 */
476 hwc->config_base |= (unsigned long)mapping;
477
478 if (!is_sampling_event(event)) {
479 /*
480 * For non-sampling runs, limit the sample_period to half
481 * of the counter width. That way, the new counter value
482 * is far less likely to overtake the previous one unless
483 * you have some serious IRQ latency issues.
484 */
485 hwc->sample_period = arm_pmu_event_max_period(event) >> 1;
486 hwc->last_period = hwc->sample_period;
487 local64_set(&hwc->period_left, hwc->sample_period);
488 }
489
490 if (event->group_leader != event) {
491 if (validate_group(event) != 0)
492 return -EINVAL;
493 }
494
495 return 0;
496}
497
498static int armpmu_event_init(struct perf_event *event)
499{
500 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
501
502 /*
503 * Reject CPU-affine events for CPUs that are of a different class to
504 * that which this PMU handles. Process-following events (where
505 * event->cpu == -1) can be migrated between CPUs, and thus we have to
506 * reject them later (in armpmu_add) if they're scheduled on a
507 * different class of CPU.
508 */
509 if (event->cpu != -1 &&
510 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
511 return -ENOENT;
512
513 /* does not support taken branch sampling */
514 if (has_branch_stack(event))
515 return -EOPNOTSUPP;
516
517 if (armpmu->map_event(event) == -ENOENT)
518 return -ENOENT;
519
520 return __hw_perf_event_init(event);
521}
522
523static void armpmu_enable(struct pmu *pmu)
524{
525 struct arm_pmu *armpmu = to_arm_pmu(pmu);
526 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
527 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
528
529 /* For task-bound events we may be called on other CPUs */
530 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
531 return;
532
533 if (enabled)
534 armpmu->start(armpmu);
535}
536
537static void armpmu_disable(struct pmu *pmu)
538{
539 struct arm_pmu *armpmu = to_arm_pmu(pmu);
540
541 /* For task-bound events we may be called on other CPUs */
542 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
543 return;
544
545 armpmu->stop(armpmu);
546}
547
548/*
549 * In heterogeneous systems, events are specific to a particular
550 * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
551 * the same microarchitecture.
552 */
553static int armpmu_filter_match(struct perf_event *event)
554{
555 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
556 unsigned int cpu = smp_processor_id();
557 int ret;
558
559 ret = cpumask_test_cpu(cpu, &armpmu->supported_cpus);
560 if (ret && armpmu->filter_match)
561 return armpmu->filter_match(event);
562
563 return ret;
564}
565
566static ssize_t cpus_show(struct device *dev,
567 struct device_attribute *attr, char *buf)
568{
569 struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
570 return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
571}
572
573static DEVICE_ATTR_RO(cpus);
574
575static struct attribute *armpmu_common_attrs[] = {
576 &dev_attr_cpus.attr,
577 NULL,
578};
579
580static const struct attribute_group armpmu_common_attr_group = {
581 .attrs = armpmu_common_attrs,
582};
583
584static int armpmu_count_irq_users(const int irq)
585{
586 int cpu, count = 0;
587
588 for_each_possible_cpu(cpu) {
589 if (per_cpu(cpu_irq, cpu) == irq)
590 count++;
591 }
592
593 return count;
594}
595
596static const struct pmu_irq_ops *armpmu_find_irq_ops(int irq)
597{
598 const struct pmu_irq_ops *ops = NULL;
599 int cpu;
600
601 for_each_possible_cpu(cpu) {
602 if (per_cpu(cpu_irq, cpu) != irq)
603 continue;
604
605 ops = per_cpu(cpu_irq_ops, cpu);
606 if (ops)
607 break;
608 }
609
610 return ops;
611}
612
613void armpmu_free_irq(int irq, int cpu)
614{
615 if (per_cpu(cpu_irq, cpu) == 0)
616 return;
617 if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
618 return;
619
620 per_cpu(cpu_irq_ops, cpu)->free_pmuirq(irq, cpu, &cpu_armpmu);
621
622 per_cpu(cpu_irq, cpu) = 0;
623 per_cpu(cpu_irq_ops, cpu) = NULL;
624}
625
626int armpmu_request_irq(int irq, int cpu)
627{
628 int err = 0;
629 const irq_handler_t handler = armpmu_dispatch_irq;
630 const struct pmu_irq_ops *irq_ops;
631
632 if (!irq)
633 return 0;
634
635 if (!irq_is_percpu_devid(irq)) {
636 unsigned long irq_flags;
637
638 err = irq_force_affinity(irq, cpumask_of(cpu));
639
640 if (err && num_possible_cpus() > 1) {
641 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
642 irq, cpu);
643 goto err_out;
644 }
645
646 irq_flags = IRQF_PERCPU |
647 IRQF_NOBALANCING | IRQF_NO_AUTOEN |
648 IRQF_NO_THREAD;
649
650 err = request_nmi(irq, handler, irq_flags, "arm-pmu",
651 per_cpu_ptr(&cpu_armpmu, cpu));
652
653 /* If cannot get an NMI, get a normal interrupt */
654 if (err) {
655 err = request_irq(irq, handler, irq_flags, "arm-pmu",
656 per_cpu_ptr(&cpu_armpmu, cpu));
657 irq_ops = &pmuirq_ops;
658 } else {
659 has_nmi = true;
660 irq_ops = &pmunmi_ops;
661 }
662 } else if (armpmu_count_irq_users(irq) == 0) {
663 err = request_percpu_nmi(irq, handler, "arm-pmu", &cpu_armpmu);
664
665 /* If cannot get an NMI, get a normal interrupt */
666 if (err) {
667 err = request_percpu_irq(irq, handler, "arm-pmu",
668 &cpu_armpmu);
669 irq_ops = &percpu_pmuirq_ops;
670 } else {
671 has_nmi = true;
672 irq_ops = &percpu_pmunmi_ops;
673 }
674 } else {
675 /* Per cpudevid irq was already requested by another CPU */
676 irq_ops = armpmu_find_irq_ops(irq);
677
678 if (WARN_ON(!irq_ops))
679 err = -EINVAL;
680 }
681
682 if (err)
683 goto err_out;
684
685 per_cpu(cpu_irq, cpu) = irq;
686 per_cpu(cpu_irq_ops, cpu) = irq_ops;
687 return 0;
688
689err_out:
690 pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
691 return err;
692}
693
694static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
695{
696 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
697 return per_cpu(hw_events->irq, cpu);
698}
699
700/*
701 * PMU hardware loses all context when a CPU goes offline.
702 * When a CPU is hotplugged back in, since some hardware registers are
703 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
704 * junk values out of them.
705 */
706static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
707{
708 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
709 int irq;
710
711 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
712 return 0;
713 if (pmu->reset)
714 pmu->reset(pmu);
715
716 per_cpu(cpu_armpmu, cpu) = pmu;
717
718 irq = armpmu_get_cpu_irq(pmu, cpu);
719 if (irq)
720 per_cpu(cpu_irq_ops, cpu)->enable_pmuirq(irq);
721
722 return 0;
723}
724
725static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
726{
727 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
728 int irq;
729
730 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
731 return 0;
732
733 irq = armpmu_get_cpu_irq(pmu, cpu);
734 if (irq)
735 per_cpu(cpu_irq_ops, cpu)->disable_pmuirq(irq);
736
737 per_cpu(cpu_armpmu, cpu) = NULL;
738
739 return 0;
740}
741
742#ifdef CONFIG_CPU_PM
743static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
744{
745 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
746 struct perf_event *event;
747 int idx;
748
749 for (idx = 0; idx < armpmu->num_events; idx++) {
750 event = hw_events->events[idx];
751 if (!event)
752 continue;
753
754 switch (cmd) {
755 case CPU_PM_ENTER:
756 /*
757 * Stop and update the counter
758 */
759 armpmu_stop(event, PERF_EF_UPDATE);
760 break;
761 case CPU_PM_EXIT:
762 case CPU_PM_ENTER_FAILED:
763 /*
764 * Restore and enable the counter.
765 * armpmu_start() indirectly calls
766 *
767 * perf_event_update_userpage()
768 *
769 * that requires RCU read locking to be functional,
770 * wrap the call within RCU_NONIDLE to make the
771 * RCU subsystem aware this cpu is not idle from
772 * an RCU perspective for the armpmu_start() call
773 * duration.
774 */
775 RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
776 break;
777 default:
778 break;
779 }
780 }
781}
782
783static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
784 void *v)
785{
786 struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
787 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
788 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
789
790 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
791 return NOTIFY_DONE;
792
793 /*
794 * Always reset the PMU registers on power-up even if
795 * there are no events running.
796 */
797 if (cmd == CPU_PM_EXIT && armpmu->reset)
798 armpmu->reset(armpmu);
799
800 if (!enabled)
801 return NOTIFY_OK;
802
803 switch (cmd) {
804 case CPU_PM_ENTER:
805 armpmu->stop(armpmu);
806 cpu_pm_pmu_setup(armpmu, cmd);
807 break;
808 case CPU_PM_EXIT:
809 case CPU_PM_ENTER_FAILED:
810 cpu_pm_pmu_setup(armpmu, cmd);
811 armpmu->start(armpmu);
812 break;
813 default:
814 return NOTIFY_DONE;
815 }
816
817 return NOTIFY_OK;
818}
819
820static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
821{
822 cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
823 return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
824}
825
826static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
827{
828 cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
829}
830#else
831static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
832static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
833#endif
834
835static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
836{
837 int err;
838
839 err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
840 &cpu_pmu->node);
841 if (err)
842 goto out;
843
844 err = cpu_pm_pmu_register(cpu_pmu);
845 if (err)
846 goto out_unregister;
847
848 return 0;
849
850out_unregister:
851 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
852 &cpu_pmu->node);
853out:
854 return err;
855}
856
857static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
858{
859 cpu_pm_pmu_unregister(cpu_pmu);
860 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
861 &cpu_pmu->node);
862}
863
864static struct arm_pmu *__armpmu_alloc(gfp_t flags)
865{
866 struct arm_pmu *pmu;
867 int cpu;
868
869 pmu = kzalloc(sizeof(*pmu), flags);
870 if (!pmu)
871 goto out;
872
873 pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags);
874 if (!pmu->hw_events) {
875 pr_info("failed to allocate per-cpu PMU data.\n");
876 goto out_free_pmu;
877 }
878
879 pmu->pmu = (struct pmu) {
880 .pmu_enable = armpmu_enable,
881 .pmu_disable = armpmu_disable,
882 .event_init = armpmu_event_init,
883 .add = armpmu_add,
884 .del = armpmu_del,
885 .start = armpmu_start,
886 .stop = armpmu_stop,
887 .read = armpmu_read,
888 .filter_match = armpmu_filter_match,
889 .attr_groups = pmu->attr_groups,
890 /*
891 * This is a CPU PMU potentially in a heterogeneous
892 * configuration (e.g. big.LITTLE). This is not an uncore PMU,
893 * and we have taken ctx sharing into account (e.g. with our
894 * pmu::filter_match callback and pmu::event_init group
895 * validation).
896 */
897 .capabilities = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
898 };
899
900 pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
901 &armpmu_common_attr_group;
902
903 for_each_possible_cpu(cpu) {
904 struct pmu_hw_events *events;
905
906 events = per_cpu_ptr(pmu->hw_events, cpu);
907 raw_spin_lock_init(&events->pmu_lock);
908 events->percpu_pmu = pmu;
909 }
910
911 return pmu;
912
913out_free_pmu:
914 kfree(pmu);
915out:
916 return NULL;
917}
918
919struct arm_pmu *armpmu_alloc(void)
920{
921 return __armpmu_alloc(GFP_KERNEL);
922}
923
924struct arm_pmu *armpmu_alloc_atomic(void)
925{
926 return __armpmu_alloc(GFP_ATOMIC);
927}
928
929
930void armpmu_free(struct arm_pmu *pmu)
931{
932 free_percpu(pmu->hw_events);
933 kfree(pmu);
934}
935
936int armpmu_register(struct arm_pmu *pmu)
937{
938 int ret;
939
940 ret = cpu_pmu_init(pmu);
941 if (ret)
942 return ret;
943
944 if (!pmu->set_event_filter)
945 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
946
947 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
948 if (ret)
949 goto out_destroy;
950
951 pr_info("enabled with %s PMU driver, %d counters available%s\n",
952 pmu->name, pmu->num_events,
953 has_nmi ? ", using NMIs" : "");
954
955 return 0;
956
957out_destroy:
958 cpu_pmu_destroy(pmu);
959 return ret;
960}
961
962static int arm_pmu_hp_init(void)
963{
964 int ret;
965
966 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
967 "perf/arm/pmu:starting",
968 arm_perf_starting_cpu,
969 arm_perf_teardown_cpu);
970 if (ret)
971 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
972 ret);
973 return ret;
974}
975subsys_initcall(arm_pmu_hp_init);