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1/*
2 * Marvell 10G 88x3310 PHY driver
3 *
4 * Based upon the ID registers, this PHY appears to be a mixture of IPs
5 * from two different companies.
6 *
7 * There appears to be several different data paths through the PHY which
8 * are automatically managed by the PHY. The following has been determined
9 * via observation and experimentation for a setup using single-lane Serdes:
10 *
11 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
12 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
13 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
14 *
15 * With XAUI, observation shows:
16 *
17 * XAUI PHYXS -- <appropriate PCS as above>
18 *
19 * and no switching of the host interface mode occurs.
20 *
21 * If both the fiber and copper ports are connected, the first to gain
22 * link takes priority and the other port is completely locked out.
23 */
24#include <linux/ctype.h>
25#include <linux/hwmon.h>
26#include <linux/marvell_phy.h>
27#include <linux/phy.h>
28
29enum {
30 MV_PCS_BASE_T = 0x0000,
31 MV_PCS_BASE_R = 0x1000,
32 MV_PCS_1000BASEX = 0x2000,
33
34 MV_PCS_PAIRSWAP = 0x8182,
35 MV_PCS_PAIRSWAP_MASK = 0x0003,
36 MV_PCS_PAIRSWAP_AB = 0x0002,
37 MV_PCS_PAIRSWAP_NONE = 0x0003,
38
39 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
40 * registers appear to set themselves to the 0x800X when AN is
41 * restarted, but status registers appear readable from either.
42 */
43 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
44 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
45
46 /* Vendor2 MMD registers */
47 MV_V2_TEMP_CTRL = 0xf08a,
48 MV_V2_TEMP_CTRL_MASK = 0xc000,
49 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
50 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
51 MV_V2_TEMP = 0xf08c,
52 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
53};
54
55struct mv3310_priv {
56 struct device *hwmon_dev;
57 char *hwmon_name;
58};
59
60static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,
61 u16 mask, u16 bits)
62{
63 int old, val, ret;
64
65 old = phy_read_mmd(phydev, devad, reg);
66 if (old < 0)
67 return old;
68
69 val = (old & ~mask) | (bits & mask);
70 if (val == old)
71 return 0;
72
73 ret = phy_write_mmd(phydev, devad, reg, val);
74
75 return ret < 0 ? ret : 1;
76}
77
78#ifdef CONFIG_HWMON
79static umode_t mv3310_hwmon_is_visible(const void *data,
80 enum hwmon_sensor_types type,
81 u32 attr, int channel)
82{
83 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
84 return 0444;
85 if (type == hwmon_temp && attr == hwmon_temp_input)
86 return 0444;
87 return 0;
88}
89
90static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
91 u32 attr, int channel, long *value)
92{
93 struct phy_device *phydev = dev_get_drvdata(dev);
94 int temp;
95
96 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
97 *value = MSEC_PER_SEC;
98 return 0;
99 }
100
101 if (type == hwmon_temp && attr == hwmon_temp_input) {
102 temp = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
103 if (temp < 0)
104 return temp;
105
106 *value = ((temp & 0xff) - 75) * 1000;
107
108 return 0;
109 }
110
111 return -EOPNOTSUPP;
112}
113
114static const struct hwmon_ops mv3310_hwmon_ops = {
115 .is_visible = mv3310_hwmon_is_visible,
116 .read = mv3310_hwmon_read,
117};
118
119static u32 mv3310_hwmon_chip_config[] = {
120 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
121 0,
122};
123
124static const struct hwmon_channel_info mv3310_hwmon_chip = {
125 .type = hwmon_chip,
126 .config = mv3310_hwmon_chip_config,
127};
128
129static u32 mv3310_hwmon_temp_config[] = {
130 HWMON_T_INPUT,
131 0,
132};
133
134static const struct hwmon_channel_info mv3310_hwmon_temp = {
135 .type = hwmon_temp,
136 .config = mv3310_hwmon_temp_config,
137};
138
139static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
140 &mv3310_hwmon_chip,
141 &mv3310_hwmon_temp,
142 NULL,
143};
144
145static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
146 .ops = &mv3310_hwmon_ops,
147 .info = mv3310_hwmon_info,
148};
149
150static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
151{
152 u16 val;
153 int ret;
154
155 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
156 MV_V2_TEMP_UNKNOWN);
157 if (ret < 0)
158 return ret;
159
160 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
161 ret = mv3310_modify(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
162 MV_V2_TEMP_CTRL_MASK, val);
163
164 return ret < 0 ? ret : 0;
165}
166
167static void mv3310_hwmon_disable(void *data)
168{
169 struct phy_device *phydev = data;
170
171 mv3310_hwmon_config(phydev, false);
172}
173
174static int mv3310_hwmon_probe(struct phy_device *phydev)
175{
176 struct device *dev = &phydev->mdio.dev;
177 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
178 int i, j, ret;
179
180 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
181 if (!priv->hwmon_name)
182 return -ENODEV;
183
184 for (i = j = 0; priv->hwmon_name[i]; i++) {
185 if (isalnum(priv->hwmon_name[i])) {
186 if (i != j)
187 priv->hwmon_name[j] = priv->hwmon_name[i];
188 j++;
189 }
190 }
191 priv->hwmon_name[j] = '\0';
192
193 ret = mv3310_hwmon_config(phydev, true);
194 if (ret)
195 return ret;
196
197 ret = devm_add_action_or_reset(dev, mv3310_hwmon_disable, phydev);
198 if (ret)
199 return ret;
200
201 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
202 priv->hwmon_name, phydev,
203 &mv3310_hwmon_chip_info, NULL);
204
205 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
206}
207#else
208static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
209{
210 return 0;
211}
212
213static int mv3310_hwmon_probe(struct phy_device *phydev)
214{
215 return 0;
216}
217#endif
218
219static int mv3310_probe(struct phy_device *phydev)
220{
221 struct mv3310_priv *priv;
222 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
223 int ret;
224
225 if (!phydev->is_c45 ||
226 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
227 return -ENODEV;
228
229 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
230 if (!priv)
231 return -ENOMEM;
232
233 dev_set_drvdata(&phydev->mdio.dev, priv);
234
235 ret = mv3310_hwmon_probe(phydev);
236 if (ret)
237 return ret;
238
239 return 0;
240}
241
242static int mv3310_suspend(struct phy_device *phydev)
243{
244 return 0;
245}
246
247static int mv3310_resume(struct phy_device *phydev)
248{
249 return mv3310_hwmon_config(phydev, true);
250}
251
252static int mv3310_config_init(struct phy_device *phydev)
253{
254 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
255 u32 mask;
256 int val;
257
258 /* Check that the PHY interface type is compatible */
259 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
260 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
261 phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
262 phydev->interface != PHY_INTERFACE_MODE_10GKR)
263 return -ENODEV;
264
265 __set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
266 __set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, supported);
267
268 if (phydev->c45_ids.devices_in_package & MDIO_DEVS_AN) {
269 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
270 if (val < 0)
271 return val;
272
273 if (val & MDIO_AN_STAT1_ABLE)
274 __set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, supported);
275 }
276
277 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2);
278 if (val < 0)
279 return val;
280
281 /* Ethtool does not support the WAN mode bits */
282 if (val & (MDIO_PMA_STAT2_10GBSR | MDIO_PMA_STAT2_10GBLR |
283 MDIO_PMA_STAT2_10GBER | MDIO_PMA_STAT2_10GBLX4 |
284 MDIO_PMA_STAT2_10GBSW | MDIO_PMA_STAT2_10GBLW |
285 MDIO_PMA_STAT2_10GBEW))
286 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
287 if (val & MDIO_PMA_STAT2_10GBSR)
288 __set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, supported);
289 if (val & MDIO_PMA_STAT2_10GBLR)
290 __set_bit(ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, supported);
291 if (val & MDIO_PMA_STAT2_10GBER)
292 __set_bit(ETHTOOL_LINK_MODE_10000baseER_Full_BIT, supported);
293
294 if (val & MDIO_PMA_STAT2_EXTABLE) {
295 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
296 if (val < 0)
297 return val;
298
299 if (val & (MDIO_PMA_EXTABLE_10GBT | MDIO_PMA_EXTABLE_1000BT |
300 MDIO_PMA_EXTABLE_100BTX | MDIO_PMA_EXTABLE_10BT))
301 __set_bit(ETHTOOL_LINK_MODE_TP_BIT, supported);
302 if (val & MDIO_PMA_EXTABLE_10GBLRM)
303 __set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
304 if (val & (MDIO_PMA_EXTABLE_10GBKX4 | MDIO_PMA_EXTABLE_10GBKR |
305 MDIO_PMA_EXTABLE_1000BKX))
306 __set_bit(ETHTOOL_LINK_MODE_Backplane_BIT, supported);
307 if (val & MDIO_PMA_EXTABLE_10GBLRM)
308 __set_bit(ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
309 supported);
310 if (val & MDIO_PMA_EXTABLE_10GBT)
311 __set_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
312 supported);
313 if (val & MDIO_PMA_EXTABLE_10GBKX4)
314 __set_bit(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
315 supported);
316 if (val & MDIO_PMA_EXTABLE_10GBKR)
317 __set_bit(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
318 supported);
319 if (val & MDIO_PMA_EXTABLE_1000BT)
320 __set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
321 supported);
322 if (val & MDIO_PMA_EXTABLE_1000BKX)
323 __set_bit(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
324 supported);
325 if (val & MDIO_PMA_EXTABLE_100BTX) {
326 __set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
327 supported);
328 __set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
329 supported);
330 }
331 if (val & MDIO_PMA_EXTABLE_10BT) {
332 __set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
333 supported);
334 __set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
335 supported);
336 }
337 }
338
339 if (!ethtool_convert_link_mode_to_legacy_u32(&mask, supported))
340 dev_warn(&phydev->mdio.dev,
341 "PHY supports (%*pb) more modes than phylib supports, some modes not supported.\n",
342 __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
343
344 phydev->supported &= mask;
345 phydev->advertising &= phydev->supported;
346
347 return 0;
348}
349
350static int mv3310_config_aneg(struct phy_device *phydev)
351{
352 bool changed = false;
353 u32 advertising;
354 int ret;
355
356 /* We don't support manual MDI control */
357 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
358
359 if (phydev->autoneg == AUTONEG_DISABLE) {
360 ret = genphy_c45_pma_setup_forced(phydev);
361 if (ret < 0)
362 return ret;
363
364 return genphy_c45_an_disable_aneg(phydev);
365 }
366
367 phydev->advertising &= phydev->supported;
368 advertising = phydev->advertising;
369
370 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
371 ADVERTISE_ALL | ADVERTISE_100BASE4 |
372 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,
373 ethtool_adv_to_mii_adv_t(advertising));
374 if (ret < 0)
375 return ret;
376 if (ret > 0)
377 changed = true;
378
379 ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
380 ADVERTISE_1000FULL | ADVERTISE_1000HALF,
381 ethtool_adv_to_mii_ctrl1000_t(advertising));
382 if (ret < 0)
383 return ret;
384 if (ret > 0)
385 changed = true;
386
387 /* 10G control register */
388 ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
389 MDIO_AN_10GBT_CTRL_ADV10G,
390 advertising & ADVERTISED_10000baseT_Full ?
391 MDIO_AN_10GBT_CTRL_ADV10G : 0);
392 if (ret < 0)
393 return ret;
394 if (ret > 0)
395 changed = true;
396
397 if (changed)
398 ret = genphy_c45_restart_aneg(phydev);
399
400 return ret;
401}
402
403static int mv3310_aneg_done(struct phy_device *phydev)
404{
405 int val;
406
407 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
408 if (val < 0)
409 return val;
410
411 if (val & MDIO_STAT1_LSTATUS)
412 return 1;
413
414 return genphy_c45_aneg_done(phydev);
415}
416
417static void mv3310_update_interface(struct phy_device *phydev)
418{
419 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
420 phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
421 /* The PHY automatically switches its serdes interface (and
422 * active PHYXS instance) between Cisco SGMII and 10GBase-KR
423 * modes according to the speed. Florian suggests setting
424 * phydev->interface to communicate this to the MAC. Only do
425 * this if we are already in either SGMII or 10GBase-KR mode.
426 */
427 if (phydev->speed == SPEED_10000)
428 phydev->interface = PHY_INTERFACE_MODE_10GKR;
429 else if (phydev->speed >= SPEED_10 &&
430 phydev->speed < SPEED_10000)
431 phydev->interface = PHY_INTERFACE_MODE_SGMII;
432 }
433}
434
435/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
436static int mv3310_read_10gbr_status(struct phy_device *phydev)
437{
438 phydev->link = 1;
439 phydev->speed = SPEED_10000;
440 phydev->duplex = DUPLEX_FULL;
441
442 mv3310_update_interface(phydev);
443
444 return 0;
445}
446
447static int mv3310_read_status(struct phy_device *phydev)
448{
449 u32 mmd_mask = phydev->c45_ids.devices_in_package;
450 int val;
451
452 /* The vendor devads do not report link status. Avoid the PHYXS
453 * instance as there are three, and its status depends on the MAC
454 * being appropriately configured for the negotiated speed.
455 */
456 mmd_mask &= ~(BIT(MDIO_MMD_VEND1) | BIT(MDIO_MMD_VEND2) |
457 BIT(MDIO_MMD_PHYXS));
458
459 phydev->speed = SPEED_UNKNOWN;
460 phydev->duplex = DUPLEX_UNKNOWN;
461 phydev->lp_advertising = 0;
462 phydev->link = 0;
463 phydev->pause = 0;
464 phydev->asym_pause = 0;
465 phydev->mdix = 0;
466
467 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
468 if (val < 0)
469 return val;
470
471 if (val & MDIO_STAT1_LSTATUS)
472 return mv3310_read_10gbr_status(phydev);
473
474 val = genphy_c45_read_link(phydev, mmd_mask);
475 if (val < 0)
476 return val;
477
478 phydev->link = val > 0 ? 1 : 0;
479
480 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
481 if (val < 0)
482 return val;
483
484 if (val & MDIO_AN_STAT1_COMPLETE) {
485 val = genphy_c45_read_lpa(phydev);
486 if (val < 0)
487 return val;
488
489 /* Read the link partner's 1G advertisement */
490 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
491 if (val < 0)
492 return val;
493
494 phydev->lp_advertising |= mii_stat1000_to_ethtool_lpa_t(val);
495
496 if (phydev->autoneg == AUTONEG_ENABLE)
497 phy_resolve_aneg_linkmode(phydev);
498 }
499
500 if (phydev->autoneg != AUTONEG_ENABLE) {
501 val = genphy_c45_read_pma(phydev);
502 if (val < 0)
503 return val;
504 }
505
506 if (phydev->speed == SPEED_10000) {
507 val = genphy_c45_read_mdix(phydev);
508 if (val < 0)
509 return val;
510 } else {
511 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PAIRSWAP);
512 if (val < 0)
513 return val;
514
515 switch (val & MV_PCS_PAIRSWAP_MASK) {
516 case MV_PCS_PAIRSWAP_AB:
517 phydev->mdix = ETH_TP_MDI_X;
518 break;
519 case MV_PCS_PAIRSWAP_NONE:
520 phydev->mdix = ETH_TP_MDI;
521 break;
522 default:
523 phydev->mdix = ETH_TP_MDI_INVALID;
524 break;
525 }
526 }
527
528 mv3310_update_interface(phydev);
529
530 return 0;
531}
532
533static struct phy_driver mv3310_drivers[] = {
534 {
535 .phy_id = 0x002b09aa,
536 .phy_id_mask = MARVELL_PHY_ID_MASK,
537 .name = "mv88x3310",
538 .features = SUPPORTED_10baseT_Full |
539 SUPPORTED_10baseT_Half |
540 SUPPORTED_100baseT_Full |
541 SUPPORTED_100baseT_Half |
542 SUPPORTED_1000baseT_Full |
543 SUPPORTED_Autoneg |
544 SUPPORTED_TP |
545 SUPPORTED_FIBRE |
546 SUPPORTED_10000baseT_Full |
547 SUPPORTED_Backplane,
548 .soft_reset = gen10g_no_soft_reset,
549 .config_init = mv3310_config_init,
550 .probe = mv3310_probe,
551 .suspend = mv3310_suspend,
552 .resume = mv3310_resume,
553 .config_aneg = mv3310_config_aneg,
554 .aneg_done = mv3310_aneg_done,
555 .read_status = mv3310_read_status,
556 },
557};
558
559module_phy_driver(mv3310_drivers);
560
561static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
562 { 0x002b09aa, MARVELL_PHY_ID_MASK },
563 { },
564};
565MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
566MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
567MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell 10G 88x3310 PHY driver
4 *
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
6 * from two different companies.
7 *
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
11 *
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
15 *
16 * With XAUI, observation shows:
17 *
18 * XAUI PHYXS -- <appropriate PCS as above>
19 *
20 * and no switching of the host interface mode occurs.
21 *
22 * If both the fiber and copper ports are connected, the first to gain
23 * link takes priority and the other port is completely locked out.
24 */
25#include <linux/ctype.h>
26#include <linux/delay.h>
27#include <linux/hwmon.h>
28#include <linux/marvell_phy.h>
29#include <linux/phy.h>
30#include <linux/sfp.h>
31
32#define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
33#define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
34
35enum {
36 MV_PMA_FW_VER0 = 0xc011,
37 MV_PMA_FW_VER1 = 0xc012,
38 MV_PMA_21X0_PORT_CTRL = 0xc04a,
39 MV_PMA_21X0_PORT_CTRL_SWRST = BIT(15),
40 MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK = 0x7,
41 MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII = 0x0,
42 MV_PMA_2180_PORT_CTRL_MACTYPE_DXGMII = 0x1,
43 MV_PMA_2180_PORT_CTRL_MACTYPE_QXGMII = 0x2,
44 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER = 0x4,
45 MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN = 0x5,
46 MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
47 MV_PMA_BOOT = 0xc050,
48 MV_PMA_BOOT_FATAL = BIT(0),
49
50 MV_PCS_BASE_T = 0x0000,
51 MV_PCS_BASE_R = 0x1000,
52 MV_PCS_1000BASEX = 0x2000,
53
54 MV_PCS_CSCR1 = 0x8000,
55 MV_PCS_CSCR1_ED_MASK = 0x0300,
56 MV_PCS_CSCR1_ED_OFF = 0x0000,
57 MV_PCS_CSCR1_ED_RX = 0x0200,
58 MV_PCS_CSCR1_ED_NLP = 0x0300,
59 MV_PCS_CSCR1_MDIX_MASK = 0x0060,
60 MV_PCS_CSCR1_MDIX_MDI = 0x0000,
61 MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
62 MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
63
64 MV_PCS_CSSR1 = 0x8008,
65 MV_PCS_CSSR1_SPD1_MASK = 0xc000,
66 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
67 MV_PCS_CSSR1_SPD1_1000 = 0x8000,
68 MV_PCS_CSSR1_SPD1_100 = 0x4000,
69 MV_PCS_CSSR1_SPD1_10 = 0x0000,
70 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
71 MV_PCS_CSSR1_RESOLVED = BIT(11),
72 MV_PCS_CSSR1_MDIX = BIT(6),
73 MV_PCS_CSSR1_SPD2_MASK = 0x000c,
74 MV_PCS_CSSR1_SPD2_5000 = 0x0008,
75 MV_PCS_CSSR1_SPD2_2500 = 0x0004,
76 MV_PCS_CSSR1_SPD2_10000 = 0x0000,
77
78 /* Temperature read register (88E2110 only) */
79 MV_PCS_TEMP = 0x8042,
80
81 /* Number of ports on the device */
82 MV_PCS_PORT_INFO = 0xd00d,
83 MV_PCS_PORT_INFO_NPORTS_MASK = 0x0380,
84 MV_PCS_PORT_INFO_NPORTS_SHIFT = 7,
85
86 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
87 * registers appear to set themselves to the 0x800X when AN is
88 * restarted, but status registers appear readable from either.
89 */
90 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
91 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
92
93 /* Vendor2 MMD registers */
94 MV_V2_PORT_CTRL = 0xf001,
95 MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
96 MV_V2_33X0_PORT_CTRL_SWRST = BIT(15),
97 MV_V2_33X0_PORT_CTRL_MACTYPE_MASK = 0x7,
98 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI = 0x0,
99 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH = 0x1,
100 MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN = 0x1,
101 MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH = 0x2,
102 MV_V2_3310_PORT_CTRL_MACTYPE_XAUI = 0x3,
103 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER = 0x4,
104 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN = 0x5,
105 MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH = 0x6,
106 MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII = 0x7,
107 /* Temperature control/read registers (88X3310 only) */
108 MV_V2_TEMP_CTRL = 0xf08a,
109 MV_V2_TEMP_CTRL_MASK = 0xc000,
110 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
111 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
112 MV_V2_TEMP = 0xf08c,
113 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
114};
115
116struct mv3310_chip {
117 void (*init_supported_interfaces)(unsigned long *mask);
118 int (*get_mactype)(struct phy_device *phydev);
119 int (*init_interface)(struct phy_device *phydev, int mactype);
120
121#ifdef CONFIG_HWMON
122 int (*hwmon_read_temp_reg)(struct phy_device *phydev);
123#endif
124};
125
126struct mv3310_priv {
127 DECLARE_BITMAP(supported_interfaces, PHY_INTERFACE_MODE_MAX);
128
129 u32 firmware_ver;
130 bool rate_match;
131 phy_interface_t const_interface;
132
133 struct device *hwmon_dev;
134 char *hwmon_name;
135};
136
137static const struct mv3310_chip *to_mv3310_chip(struct phy_device *phydev)
138{
139 return phydev->drv->driver_data;
140}
141
142#ifdef CONFIG_HWMON
143static umode_t mv3310_hwmon_is_visible(const void *data,
144 enum hwmon_sensor_types type,
145 u32 attr, int channel)
146{
147 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
148 return 0444;
149 if (type == hwmon_temp && attr == hwmon_temp_input)
150 return 0444;
151 return 0;
152}
153
154static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
155{
156 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
157}
158
159static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
160{
161 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
162}
163
164static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
165 u32 attr, int channel, long *value)
166{
167 struct phy_device *phydev = dev_get_drvdata(dev);
168 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
169 int temp;
170
171 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
172 *value = MSEC_PER_SEC;
173 return 0;
174 }
175
176 if (type == hwmon_temp && attr == hwmon_temp_input) {
177 temp = chip->hwmon_read_temp_reg(phydev);
178 if (temp < 0)
179 return temp;
180
181 *value = ((temp & 0xff) - 75) * 1000;
182
183 return 0;
184 }
185
186 return -EOPNOTSUPP;
187}
188
189static const struct hwmon_ops mv3310_hwmon_ops = {
190 .is_visible = mv3310_hwmon_is_visible,
191 .read = mv3310_hwmon_read,
192};
193
194static u32 mv3310_hwmon_chip_config[] = {
195 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
196 0,
197};
198
199static const struct hwmon_channel_info mv3310_hwmon_chip = {
200 .type = hwmon_chip,
201 .config = mv3310_hwmon_chip_config,
202};
203
204static u32 mv3310_hwmon_temp_config[] = {
205 HWMON_T_INPUT,
206 0,
207};
208
209static const struct hwmon_channel_info mv3310_hwmon_temp = {
210 .type = hwmon_temp,
211 .config = mv3310_hwmon_temp_config,
212};
213
214static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
215 &mv3310_hwmon_chip,
216 &mv3310_hwmon_temp,
217 NULL,
218};
219
220static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
221 .ops = &mv3310_hwmon_ops,
222 .info = mv3310_hwmon_info,
223};
224
225static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
226{
227 u16 val;
228 int ret;
229
230 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
231 return 0;
232
233 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
234 MV_V2_TEMP_UNKNOWN);
235 if (ret < 0)
236 return ret;
237
238 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
239
240 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
241 MV_V2_TEMP_CTRL_MASK, val);
242}
243
244static int mv3310_hwmon_probe(struct phy_device *phydev)
245{
246 struct device *dev = &phydev->mdio.dev;
247 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
248 int i, j, ret;
249
250 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
251 if (!priv->hwmon_name)
252 return -ENODEV;
253
254 for (i = j = 0; priv->hwmon_name[i]; i++) {
255 if (isalnum(priv->hwmon_name[i])) {
256 if (i != j)
257 priv->hwmon_name[j] = priv->hwmon_name[i];
258 j++;
259 }
260 }
261 priv->hwmon_name[j] = '\0';
262
263 ret = mv3310_hwmon_config(phydev, true);
264 if (ret)
265 return ret;
266
267 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
268 priv->hwmon_name, phydev,
269 &mv3310_hwmon_chip_info, NULL);
270
271 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
272}
273#else
274static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
275{
276 return 0;
277}
278
279static int mv3310_hwmon_probe(struct phy_device *phydev)
280{
281 return 0;
282}
283#endif
284
285static int mv3310_power_down(struct phy_device *phydev)
286{
287 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
288 MV_V2_PORT_CTRL_PWRDOWN);
289}
290
291static int mv3310_power_up(struct phy_device *phydev)
292{
293 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
294 int ret;
295
296 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
297 MV_V2_PORT_CTRL_PWRDOWN);
298
299 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
300 priv->firmware_ver < 0x00030000)
301 return ret;
302
303 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
304 MV_V2_33X0_PORT_CTRL_SWRST);
305}
306
307static int mv3310_reset(struct phy_device *phydev, u32 unit)
308{
309 int val, err;
310
311 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
312 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
313 if (err < 0)
314 return err;
315
316 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
317 unit + MDIO_CTRL1, val,
318 !(val & MDIO_CTRL1_RESET),
319 5000, 100000, true);
320}
321
322static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
323{
324 int val;
325
326 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
327 if (val < 0)
328 return val;
329
330 switch (val & MV_PCS_CSCR1_ED_MASK) {
331 case MV_PCS_CSCR1_ED_NLP:
332 *edpd = 1000;
333 break;
334 case MV_PCS_CSCR1_ED_RX:
335 *edpd = ETHTOOL_PHY_EDPD_NO_TX;
336 break;
337 default:
338 *edpd = ETHTOOL_PHY_EDPD_DISABLE;
339 break;
340 }
341 return 0;
342}
343
344static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
345{
346 u16 val;
347 int err;
348
349 switch (edpd) {
350 case 1000:
351 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
352 val = MV_PCS_CSCR1_ED_NLP;
353 break;
354
355 case ETHTOOL_PHY_EDPD_NO_TX:
356 val = MV_PCS_CSCR1_ED_RX;
357 break;
358
359 case ETHTOOL_PHY_EDPD_DISABLE:
360 val = MV_PCS_CSCR1_ED_OFF;
361 break;
362
363 default:
364 return -EINVAL;
365 }
366
367 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
368 MV_PCS_CSCR1_ED_MASK, val);
369 if (err > 0)
370 err = mv3310_reset(phydev, MV_PCS_BASE_T);
371
372 return err;
373}
374
375static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
376{
377 struct phy_device *phydev = upstream;
378 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
379 phy_interface_t iface;
380
381 sfp_parse_support(phydev->sfp_bus, id, support);
382 iface = sfp_select_interface(phydev->sfp_bus, support);
383
384 if (iface != PHY_INTERFACE_MODE_10GBASER) {
385 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
386 return -EINVAL;
387 }
388 return 0;
389}
390
391static const struct sfp_upstream_ops mv3310_sfp_ops = {
392 .attach = phy_sfp_attach,
393 .detach = phy_sfp_detach,
394 .module_insert = mv3310_sfp_insert,
395};
396
397static int mv3310_probe(struct phy_device *phydev)
398{
399 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
400 struct mv3310_priv *priv;
401 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
402 int ret;
403
404 if (!phydev->is_c45 ||
405 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
406 return -ENODEV;
407
408 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
409 if (ret < 0)
410 return ret;
411
412 if (ret & MV_PMA_BOOT_FATAL) {
413 dev_warn(&phydev->mdio.dev,
414 "PHY failed to boot firmware, status=%04x\n", ret);
415 return -ENODEV;
416 }
417
418 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
419 if (!priv)
420 return -ENOMEM;
421
422 dev_set_drvdata(&phydev->mdio.dev, priv);
423
424 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
425 if (ret < 0)
426 return ret;
427
428 priv->firmware_ver = ret << 16;
429
430 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
431 if (ret < 0)
432 return ret;
433
434 priv->firmware_ver |= ret;
435
436 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
437 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
438 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
439
440 /* Powering down the port when not in use saves about 600mW */
441 ret = mv3310_power_down(phydev);
442 if (ret)
443 return ret;
444
445 ret = mv3310_hwmon_probe(phydev);
446 if (ret)
447 return ret;
448
449 chip->init_supported_interfaces(priv->supported_interfaces);
450
451 return phy_sfp_probe(phydev, &mv3310_sfp_ops);
452}
453
454static void mv3310_remove(struct phy_device *phydev)
455{
456 mv3310_hwmon_config(phydev, false);
457}
458
459static int mv3310_suspend(struct phy_device *phydev)
460{
461 return mv3310_power_down(phydev);
462}
463
464static int mv3310_resume(struct phy_device *phydev)
465{
466 int ret;
467
468 ret = mv3310_power_up(phydev);
469 if (ret)
470 return ret;
471
472 return mv3310_hwmon_config(phydev, true);
473}
474
475/* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
476 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
477 * support 2.5GBASET and 5GBASET. For these models, we can still read their
478 * 2.5G/5G extended abilities register (1.21). We detect these models based on
479 * the PMA device identifier, with a mask matching models known to have this
480 * issue
481 */
482static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
483{
484 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
485 return false;
486
487 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
488 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
489 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
490}
491
492static int mv2110_get_mactype(struct phy_device *phydev)
493{
494 int mactype;
495
496 mactype = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_21X0_PORT_CTRL);
497 if (mactype < 0)
498 return mactype;
499
500 return mactype & MV_PMA_21X0_PORT_CTRL_MACTYPE_MASK;
501}
502
503static int mv3310_get_mactype(struct phy_device *phydev)
504{
505 int mactype;
506
507 mactype = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
508 if (mactype < 0)
509 return mactype;
510
511 return mactype & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK;
512}
513
514static int mv2110_init_interface(struct phy_device *phydev, int mactype)
515{
516 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
517
518 priv->rate_match = false;
519
520 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
521 priv->rate_match = true;
522
523 if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII)
524 priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
525 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
526 priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
527 else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER ||
528 mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN)
529 priv->const_interface = PHY_INTERFACE_MODE_NA;
530 else
531 return -EINVAL;
532
533 return 0;
534}
535
536static int mv3310_init_interface(struct phy_device *phydev, int mactype)
537{
538 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
539
540 priv->rate_match = false;
541
542 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
543 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
544 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
545 priv->rate_match = true;
546
547 if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII)
548 priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
549 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
550 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN ||
551 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)
552 priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
553 else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
554 mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI)
555 priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
556 else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH ||
557 mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI)
558 priv->const_interface = PHY_INTERFACE_MODE_XAUI;
559 else
560 return -EINVAL;
561
562 return 0;
563}
564
565static int mv3340_init_interface(struct phy_device *phydev, int mactype)
566{
567 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
568 int err = 0;
569
570 priv->rate_match = false;
571
572 if (mactype == MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN)
573 priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
574 else
575 err = mv3310_init_interface(phydev, mactype);
576
577 return err;
578}
579
580static int mv3310_config_init(struct phy_device *phydev)
581{
582 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
583 const struct mv3310_chip *chip = to_mv3310_chip(phydev);
584 int err, mactype;
585
586 /* Check that the PHY interface type is compatible */
587 if (!test_bit(phydev->interface, priv->supported_interfaces))
588 return -ENODEV;
589
590 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
591
592 /* Power up so reset works */
593 err = mv3310_power_up(phydev);
594 if (err)
595 return err;
596
597 mactype = chip->get_mactype(phydev);
598 if (mactype < 0)
599 return mactype;
600
601 err = chip->init_interface(phydev, mactype);
602 if (err) {
603 phydev_err(phydev, "MACTYPE configuration invalid\n");
604 return err;
605 }
606
607 /* Enable EDPD mode - saving 600mW */
608 return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
609}
610
611static int mv3310_get_features(struct phy_device *phydev)
612{
613 int ret, val;
614
615 ret = genphy_c45_pma_read_abilities(phydev);
616 if (ret)
617 return ret;
618
619 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
620 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
621 MDIO_PMA_NG_EXTABLE);
622 if (val < 0)
623 return val;
624
625 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
626 phydev->supported,
627 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
628
629 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
630 phydev->supported,
631 val & MDIO_PMA_NG_EXTABLE_5GBT);
632 }
633
634 return 0;
635}
636
637static int mv3310_config_mdix(struct phy_device *phydev)
638{
639 u16 val;
640 int err;
641
642 switch (phydev->mdix_ctrl) {
643 case ETH_TP_MDI_AUTO:
644 val = MV_PCS_CSCR1_MDIX_AUTO;
645 break;
646 case ETH_TP_MDI_X:
647 val = MV_PCS_CSCR1_MDIX_MDIX;
648 break;
649 case ETH_TP_MDI:
650 val = MV_PCS_CSCR1_MDIX_MDI;
651 break;
652 default:
653 return -EINVAL;
654 }
655
656 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
657 MV_PCS_CSCR1_MDIX_MASK, val);
658 if (err > 0)
659 err = mv3310_reset(phydev, MV_PCS_BASE_T);
660
661 return err;
662}
663
664static int mv3310_config_aneg(struct phy_device *phydev)
665{
666 bool changed = false;
667 u16 reg;
668 int ret;
669
670 ret = mv3310_config_mdix(phydev);
671 if (ret < 0)
672 return ret;
673
674 if (phydev->autoneg == AUTONEG_DISABLE)
675 return genphy_c45_pma_setup_forced(phydev);
676
677 ret = genphy_c45_an_config_aneg(phydev);
678 if (ret < 0)
679 return ret;
680 if (ret > 0)
681 changed = true;
682
683 /* Clause 45 has no standardized support for 1000BaseT, therefore
684 * use vendor registers for this mode.
685 */
686 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
687 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
688 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
689 if (ret < 0)
690 return ret;
691 if (ret > 0)
692 changed = true;
693
694 return genphy_c45_check_and_restart_aneg(phydev, changed);
695}
696
697static int mv3310_aneg_done(struct phy_device *phydev)
698{
699 int val;
700
701 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
702 if (val < 0)
703 return val;
704
705 if (val & MDIO_STAT1_LSTATUS)
706 return 1;
707
708 return genphy_c45_aneg_done(phydev);
709}
710
711static void mv3310_update_interface(struct phy_device *phydev)
712{
713 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
714
715 if (!phydev->link)
716 return;
717
718 /* In all of the "* with Rate Matching" modes the PHY interface is fixed
719 * at 10Gb. The PHY adapts the rate to actual wire speed with help of
720 * internal 16KB buffer.
721 *
722 * In USXGMII mode the PHY interface mode is also fixed.
723 */
724 if (priv->rate_match ||
725 priv->const_interface == PHY_INTERFACE_MODE_USXGMII) {
726 phydev->interface = priv->const_interface;
727 return;
728 }
729
730 /* The PHY automatically switches its serdes interface (and active PHYXS
731 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
732 * xaui / rxaui modes according to the speed.
733 * Florian suggests setting phydev->interface to communicate this to the
734 * MAC. Only do this if we are already in one of the above modes.
735 */
736 switch (phydev->speed) {
737 case SPEED_10000:
738 phydev->interface = priv->const_interface;
739 break;
740 case SPEED_5000:
741 phydev->interface = PHY_INTERFACE_MODE_5GBASER;
742 break;
743 case SPEED_2500:
744 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
745 break;
746 case SPEED_1000:
747 case SPEED_100:
748 case SPEED_10:
749 phydev->interface = PHY_INTERFACE_MODE_SGMII;
750 break;
751 default:
752 break;
753 }
754}
755
756/* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
757static int mv3310_read_status_10gbaser(struct phy_device *phydev)
758{
759 phydev->link = 1;
760 phydev->speed = SPEED_10000;
761 phydev->duplex = DUPLEX_FULL;
762 phydev->port = PORT_FIBRE;
763
764 return 0;
765}
766
767static int mv3310_read_status_copper(struct phy_device *phydev)
768{
769 int cssr1, speed, val;
770
771 val = genphy_c45_read_link(phydev);
772 if (val < 0)
773 return val;
774
775 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
776 if (val < 0)
777 return val;
778
779 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
780 if (cssr1 < 0)
781 return val;
782
783 /* If the link settings are not resolved, mark the link down */
784 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
785 phydev->link = 0;
786 return 0;
787 }
788
789 /* Read the copper link settings */
790 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
791 if (speed == MV_PCS_CSSR1_SPD1_SPD2)
792 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
793
794 switch (speed) {
795 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
796 phydev->speed = SPEED_10000;
797 break;
798
799 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
800 phydev->speed = SPEED_5000;
801 break;
802
803 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
804 phydev->speed = SPEED_2500;
805 break;
806
807 case MV_PCS_CSSR1_SPD1_1000:
808 phydev->speed = SPEED_1000;
809 break;
810
811 case MV_PCS_CSSR1_SPD1_100:
812 phydev->speed = SPEED_100;
813 break;
814
815 case MV_PCS_CSSR1_SPD1_10:
816 phydev->speed = SPEED_10;
817 break;
818 }
819
820 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
821 DUPLEX_FULL : DUPLEX_HALF;
822 phydev->port = PORT_TP;
823 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
824 ETH_TP_MDI_X : ETH_TP_MDI;
825
826 if (val & MDIO_AN_STAT1_COMPLETE) {
827 val = genphy_c45_read_lpa(phydev);
828 if (val < 0)
829 return val;
830
831 /* Read the link partner's 1G advertisement */
832 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
833 if (val < 0)
834 return val;
835
836 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
837
838 /* Update the pause status */
839 phy_resolve_aneg_pause(phydev);
840 }
841
842 return 0;
843}
844
845static int mv3310_read_status(struct phy_device *phydev)
846{
847 int err, val;
848
849 phydev->speed = SPEED_UNKNOWN;
850 phydev->duplex = DUPLEX_UNKNOWN;
851 linkmode_zero(phydev->lp_advertising);
852 phydev->link = 0;
853 phydev->pause = 0;
854 phydev->asym_pause = 0;
855 phydev->mdix = ETH_TP_MDI_INVALID;
856
857 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
858 if (val < 0)
859 return val;
860
861 if (val & MDIO_STAT1_LSTATUS)
862 err = mv3310_read_status_10gbaser(phydev);
863 else
864 err = mv3310_read_status_copper(phydev);
865 if (err < 0)
866 return err;
867
868 if (phydev->link)
869 mv3310_update_interface(phydev);
870
871 return 0;
872}
873
874static int mv3310_get_tunable(struct phy_device *phydev,
875 struct ethtool_tunable *tuna, void *data)
876{
877 switch (tuna->id) {
878 case ETHTOOL_PHY_EDPD:
879 return mv3310_get_edpd(phydev, data);
880 default:
881 return -EOPNOTSUPP;
882 }
883}
884
885static int mv3310_set_tunable(struct phy_device *phydev,
886 struct ethtool_tunable *tuna, const void *data)
887{
888 switch (tuna->id) {
889 case ETHTOOL_PHY_EDPD:
890 return mv3310_set_edpd(phydev, *(u16 *)data);
891 default:
892 return -EOPNOTSUPP;
893 }
894}
895
896static void mv3310_init_supported_interfaces(unsigned long *mask)
897{
898 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
899 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
900 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
901 __set_bit(PHY_INTERFACE_MODE_XAUI, mask);
902 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
903 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
904 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
905}
906
907static void mv3340_init_supported_interfaces(unsigned long *mask)
908{
909 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
910 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
911 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
912 __set_bit(PHY_INTERFACE_MODE_RXAUI, mask);
913 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
914 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
915}
916
917static void mv2110_init_supported_interfaces(unsigned long *mask)
918{
919 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
920 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
921 __set_bit(PHY_INTERFACE_MODE_5GBASER, mask);
922 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
923 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
924}
925
926static void mv2111_init_supported_interfaces(unsigned long *mask)
927{
928 __set_bit(PHY_INTERFACE_MODE_SGMII, mask);
929 __set_bit(PHY_INTERFACE_MODE_2500BASEX, mask);
930 __set_bit(PHY_INTERFACE_MODE_10GBASER, mask);
931 __set_bit(PHY_INTERFACE_MODE_USXGMII, mask);
932}
933
934static const struct mv3310_chip mv3310_type = {
935 .init_supported_interfaces = mv3310_init_supported_interfaces,
936 .get_mactype = mv3310_get_mactype,
937 .init_interface = mv3310_init_interface,
938
939#ifdef CONFIG_HWMON
940 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
941#endif
942};
943
944static const struct mv3310_chip mv3340_type = {
945 .init_supported_interfaces = mv3340_init_supported_interfaces,
946 .get_mactype = mv3310_get_mactype,
947 .init_interface = mv3340_init_interface,
948
949#ifdef CONFIG_HWMON
950 .hwmon_read_temp_reg = mv3310_hwmon_read_temp_reg,
951#endif
952};
953
954static const struct mv3310_chip mv2110_type = {
955 .init_supported_interfaces = mv2110_init_supported_interfaces,
956 .get_mactype = mv2110_get_mactype,
957 .init_interface = mv2110_init_interface,
958
959#ifdef CONFIG_HWMON
960 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
961#endif
962};
963
964static const struct mv3310_chip mv2111_type = {
965 .init_supported_interfaces = mv2111_init_supported_interfaces,
966 .get_mactype = mv2110_get_mactype,
967 .init_interface = mv2110_init_interface,
968
969#ifdef CONFIG_HWMON
970 .hwmon_read_temp_reg = mv2110_hwmon_read_temp_reg,
971#endif
972};
973
974static int mv3310_get_number_of_ports(struct phy_device *phydev)
975{
976 int ret;
977
978 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_PORT_INFO);
979 if (ret < 0)
980 return ret;
981
982 ret &= MV_PCS_PORT_INFO_NPORTS_MASK;
983 ret >>= MV_PCS_PORT_INFO_NPORTS_SHIFT;
984
985 return ret + 1;
986}
987
988static int mv3310_match_phy_device(struct phy_device *phydev)
989{
990 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
991 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
992 return 0;
993
994 return mv3310_get_number_of_ports(phydev) == 1;
995}
996
997static int mv3340_match_phy_device(struct phy_device *phydev)
998{
999 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1000 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88X3310)
1001 return 0;
1002
1003 return mv3310_get_number_of_ports(phydev) == 4;
1004}
1005
1006static int mv211x_match_phy_device(struct phy_device *phydev, bool has_5g)
1007{
1008 int val;
1009
1010 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
1011 MARVELL_PHY_ID_MASK) != MARVELL_PHY_ID_88E2110)
1012 return 0;
1013
1014 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_SPEED);
1015 if (val < 0)
1016 return val;
1017
1018 return !!(val & MDIO_PCS_SPEED_5G) == has_5g;
1019}
1020
1021static int mv2110_match_phy_device(struct phy_device *phydev)
1022{
1023 return mv211x_match_phy_device(phydev, true);
1024}
1025
1026static int mv2111_match_phy_device(struct phy_device *phydev)
1027{
1028 return mv211x_match_phy_device(phydev, false);
1029}
1030
1031static struct phy_driver mv3310_drivers[] = {
1032 {
1033 .phy_id = MARVELL_PHY_ID_88X3310,
1034 .phy_id_mask = MARVELL_PHY_ID_MASK,
1035 .match_phy_device = mv3310_match_phy_device,
1036 .name = "mv88x3310",
1037 .driver_data = &mv3310_type,
1038 .get_features = mv3310_get_features,
1039 .config_init = mv3310_config_init,
1040 .probe = mv3310_probe,
1041 .suspend = mv3310_suspend,
1042 .resume = mv3310_resume,
1043 .config_aneg = mv3310_config_aneg,
1044 .aneg_done = mv3310_aneg_done,
1045 .read_status = mv3310_read_status,
1046 .get_tunable = mv3310_get_tunable,
1047 .set_tunable = mv3310_set_tunable,
1048 .remove = mv3310_remove,
1049 .set_loopback = genphy_c45_loopback,
1050 },
1051 {
1052 .phy_id = MARVELL_PHY_ID_88X3310,
1053 .phy_id_mask = MARVELL_PHY_ID_MASK,
1054 .match_phy_device = mv3340_match_phy_device,
1055 .name = "mv88x3340",
1056 .driver_data = &mv3340_type,
1057 .get_features = mv3310_get_features,
1058 .config_init = mv3310_config_init,
1059 .probe = mv3310_probe,
1060 .suspend = mv3310_suspend,
1061 .resume = mv3310_resume,
1062 .config_aneg = mv3310_config_aneg,
1063 .aneg_done = mv3310_aneg_done,
1064 .read_status = mv3310_read_status,
1065 .get_tunable = mv3310_get_tunable,
1066 .set_tunable = mv3310_set_tunable,
1067 .remove = mv3310_remove,
1068 .set_loopback = genphy_c45_loopback,
1069 },
1070 {
1071 .phy_id = MARVELL_PHY_ID_88E2110,
1072 .phy_id_mask = MARVELL_PHY_ID_MASK,
1073 .match_phy_device = mv2110_match_phy_device,
1074 .name = "mv88e2110",
1075 .driver_data = &mv2110_type,
1076 .probe = mv3310_probe,
1077 .suspend = mv3310_suspend,
1078 .resume = mv3310_resume,
1079 .config_init = mv3310_config_init,
1080 .config_aneg = mv3310_config_aneg,
1081 .aneg_done = mv3310_aneg_done,
1082 .read_status = mv3310_read_status,
1083 .get_tunable = mv3310_get_tunable,
1084 .set_tunable = mv3310_set_tunable,
1085 .remove = mv3310_remove,
1086 .set_loopback = genphy_c45_loopback,
1087 },
1088 {
1089 .phy_id = MARVELL_PHY_ID_88E2110,
1090 .phy_id_mask = MARVELL_PHY_ID_MASK,
1091 .match_phy_device = mv2111_match_phy_device,
1092 .name = "mv88e2111",
1093 .driver_data = &mv2111_type,
1094 .probe = mv3310_probe,
1095 .suspend = mv3310_suspend,
1096 .resume = mv3310_resume,
1097 .config_init = mv3310_config_init,
1098 .config_aneg = mv3310_config_aneg,
1099 .aneg_done = mv3310_aneg_done,
1100 .read_status = mv3310_read_status,
1101 .get_tunable = mv3310_get_tunable,
1102 .set_tunable = mv3310_set_tunable,
1103 .remove = mv3310_remove,
1104 .set_loopback = genphy_c45_loopback,
1105 },
1106};
1107
1108module_phy_driver(mv3310_drivers);
1109
1110static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
1111 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
1112 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
1113 { },
1114};
1115MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
1116MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");
1117MODULE_LICENSE("GPL");