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1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2019-2021 Linaro Ltd.
5 */
6
7#include <linux/log2.h>
8
9#include "gsi.h"
10#include "ipa_data.h"
11#include "ipa_endpoint.h"
12#include "ipa_mem.h"
13
14/** enum ipa_resource_type - IPA resource types for an SoC having IPA v3.5.1 */
15enum ipa_resource_type {
16 /* Source resource types; first must have value 0 */
17 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
18 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
19 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
20 IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
21 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
22
23 /* Destination resource types; first must have value 0 */
24 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
25 IPA_RESOURCE_TYPE_DST_DPS_DMARS,
26};
27
28/* Resource groups used for an SoC having IPA v3.5.1 */
29enum ipa_rsrc_group_id {
30 /* Source resource group identifiers */
31 IPA_RSRC_GROUP_SRC_LWA_DL = 0,
32 IPA_RSRC_GROUP_SRC_UL_DL,
33 IPA_RSRC_GROUP_SRC_MHI_DMA,
34 IPA_RSRC_GROUP_SRC_UC_RX_Q,
35 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
36
37 /* Destination resource group identifiers */
38 IPA_RSRC_GROUP_DST_LWA_DL = 0,
39 IPA_RSRC_GROUP_DST_UL_DL_DPL,
40 IPA_RSRC_GROUP_DST_UNUSED_2,
41 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
42};
43
44/* QSB configuration data for an SoC having IPA v3.5.1 */
45static const struct ipa_qsb_data ipa_qsb_data[] = {
46 [IPA_QSB_MASTER_DDR] = {
47 .max_writes = 8,
48 .max_reads = 8,
49 },
50 [IPA_QSB_MASTER_PCIE] = {
51 .max_writes = 4,
52 .max_reads = 12,
53 },
54};
55
56/* Endpoint datdata for an SoC having IPA v3.5.1 */
57static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
58 [IPA_ENDPOINT_AP_COMMAND_TX] = {
59 .ee_id = GSI_EE_AP,
60 .channel_id = 4,
61 .endpoint_id = 5,
62 .toward_ipa = true,
63 .channel = {
64 .tre_count = 512,
65 .event_count = 256,
66 .tlv_count = 20,
67 },
68 .endpoint = {
69 .config = {
70 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
71 .dma_mode = true,
72 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
73 .tx = {
74 .seq_type = IPA_SEQ_DMA,
75 },
76 },
77 },
78 },
79 [IPA_ENDPOINT_AP_LAN_RX] = {
80 .ee_id = GSI_EE_AP,
81 .channel_id = 5,
82 .endpoint_id = 9,
83 .toward_ipa = false,
84 .channel = {
85 .tre_count = 256,
86 .event_count = 256,
87 .tlv_count = 8,
88 },
89 .endpoint = {
90 .config = {
91 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
92 .aggregation = true,
93 .status_enable = true,
94 .rx = {
95 .pad_align = ilog2(sizeof(u32)),
96 },
97 },
98 },
99 },
100 [IPA_ENDPOINT_AP_MODEM_TX] = {
101 .ee_id = GSI_EE_AP,
102 .channel_id = 3,
103 .endpoint_id = 2,
104 .toward_ipa = true,
105 .channel = {
106 .tre_count = 512,
107 .event_count = 512,
108 .tlv_count = 16,
109 },
110 .endpoint = {
111 .filter_support = true,
112 .config = {
113 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
114 .checksum = true,
115 .qmap = true,
116 .status_enable = true,
117 .tx = {
118 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
119 .seq_rep_type = IPA_SEQ_REP_DMA_PARSER,
120 .status_endpoint =
121 IPA_ENDPOINT_MODEM_AP_RX,
122 },
123 },
124 },
125 },
126 [IPA_ENDPOINT_AP_MODEM_RX] = {
127 .ee_id = GSI_EE_AP,
128 .channel_id = 6,
129 .endpoint_id = 10,
130 .toward_ipa = false,
131 .channel = {
132 .tre_count = 256,
133 .event_count = 256,
134 .tlv_count = 8,
135 },
136 .endpoint = {
137 .config = {
138 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
139 .checksum = true,
140 .qmap = true,
141 .aggregation = true,
142 .rx = {
143 .aggr_close_eof = true,
144 },
145 },
146 },
147 },
148 [IPA_ENDPOINT_MODEM_LAN_TX] = {
149 .ee_id = GSI_EE_MODEM,
150 .channel_id = 0,
151 .endpoint_id = 3,
152 .toward_ipa = true,
153 .endpoint = {
154 .filter_support = true,
155 },
156 },
157 [IPA_ENDPOINT_MODEM_AP_TX] = {
158 .ee_id = GSI_EE_MODEM,
159 .channel_id = 4,
160 .endpoint_id = 6,
161 .toward_ipa = true,
162 .endpoint = {
163 .filter_support = true,
164 },
165 },
166 [IPA_ENDPOINT_MODEM_AP_RX] = {
167 .ee_id = GSI_EE_MODEM,
168 .channel_id = 2,
169 .endpoint_id = 12,
170 .toward_ipa = false,
171 },
172};
173
174/* Source resource configuration data for an SoC having IPA v3.5.1 */
175static const struct ipa_resource ipa_resource_src[] = {
176 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
177 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
178 .min = 1, .max = 255,
179 },
180 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
181 .min = 1, .max = 255,
182 },
183 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
184 .min = 1, .max = 63,
185 },
186 },
187 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
188 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
189 .min = 10, .max = 10,
190 },
191 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
192 .min = 10, .max = 10,
193 },
194 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
195 .min = 8, .max = 8,
196 },
197 },
198 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
199 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
200 .min = 12, .max = 12,
201 },
202 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
203 .min = 14, .max = 14,
204 },
205 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
206 .min = 8, .max = 8,
207 },
208 },
209 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
210 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
211 .min = 0, .max = 63,
212 },
213 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
214 .min = 0, .max = 63,
215 },
216 .limits[IPA_RSRC_GROUP_SRC_MHI_DMA] = {
217 .min = 0, .max = 63,
218 },
219 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
220 .min = 0, .max = 63,
221 },
222 },
223 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
224 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
225 .min = 14, .max = 14,
226 },
227 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
228 .min = 20, .max = 20,
229 },
230 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
231 .min = 14, .max = 14,
232 },
233 },
234};
235
236/* Destination resource configuration data for an SoC having IPA v3.5.1 */
237static const struct ipa_resource ipa_resource_dst[] = {
238 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
239 .limits[IPA_RSRC_GROUP_DST_LWA_DL] = {
240 .min = 4, .max = 4,
241 },
242 .limits[1] = {
243 .min = 4, .max = 4,
244 },
245 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
246 .min = 3, .max = 3,
247 }
248 },
249 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
250 .limits[IPA_RSRC_GROUP_DST_LWA_DL] = {
251 .min = 2, .max = 63,
252 },
253 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
254 .min = 1, .max = 63,
255 },
256 .limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
257 .min = 1, .max = 2,
258 }
259 },
260};
261
262/* Resource configuration data for an SoC having IPA v3.5.1 */
263static const struct ipa_resource_data ipa_resource_data = {
264 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
265 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
266 .resource_src_count = ARRAY_SIZE(ipa_resource_src),
267 .resource_src = ipa_resource_src,
268 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
269 .resource_dst = ipa_resource_dst,
270};
271
272/* IPA-resident memory region data for an SoC having IPA v3.5.1 */
273static const struct ipa_mem ipa_mem_local_data[] = {
274 {
275 .id = IPA_MEM_UC_SHARED,
276 .offset = 0x0000,
277 .size = 0x0080,
278 .canary_count = 0,
279 },
280 {
281 .id = IPA_MEM_UC_INFO,
282 .offset = 0x0080,
283 .size = 0x0200,
284 .canary_count = 0,
285 },
286 {
287 .id = IPA_MEM_V4_FILTER_HASHED,
288 .offset = 0x0288,
289 .size = 0x0078,
290 .canary_count = 2,
291 },
292 {
293 .id = IPA_MEM_V4_FILTER,
294 .offset = 0x0308,
295 .size = 0x0078,
296 .canary_count = 2,
297 },
298 {
299 .id = IPA_MEM_V6_FILTER_HASHED,
300 .offset = 0x0388,
301 .size = 0x0078,
302 .canary_count = 2,
303 },
304 {
305 .id = IPA_MEM_V6_FILTER,
306 .offset = 0x0408,
307 .size = 0x0078,
308 .canary_count = 2,
309 },
310 {
311 .id = IPA_MEM_V4_ROUTE_HASHED,
312 .offset = 0x0488,
313 .size = 0x0078,
314 .canary_count = 2,
315 },
316 {
317 .id = IPA_MEM_V4_ROUTE,
318 .offset = 0x0508,
319 .size = 0x0078,
320 .canary_count = 2,
321 },
322 {
323 .id = IPA_MEM_V6_ROUTE_HASHED,
324 .offset = 0x0588,
325 .size = 0x0078,
326 .canary_count = 2,
327 },
328 {
329 .id = IPA_MEM_V6_ROUTE,
330 .offset = 0x0608,
331 .size = 0x0078,
332 .canary_count = 2,
333 },
334 {
335 .id = IPA_MEM_MODEM_HEADER,
336 .offset = 0x0688,
337 .size = 0x0140,
338 .canary_count = 2,
339 },
340 {
341 .id = IPA_MEM_MODEM_PROC_CTX,
342 .offset = 0x07d0,
343 .size = 0x0200,
344 .canary_count = 2,
345 },
346 {
347 .id = IPA_MEM_AP_PROC_CTX,
348 .offset = 0x09d0,
349 .size = 0x0200,
350 .canary_count = 0,
351 },
352 {
353 .id = IPA_MEM_MODEM,
354 .offset = 0x0bd8,
355 .size = 0x1024,
356 .canary_count = 0,
357 },
358 {
359 .id = IPA_MEM_UC_EVENT_RING,
360 .offset = 0x1c00,
361 .size = 0x0400,
362 .canary_count = 1,
363 },
364};
365
366/* Memory configuration data for an SoC having IPA v3.5.1 */
367static const struct ipa_mem_data ipa_mem_data = {
368 .local_count = ARRAY_SIZE(ipa_mem_local_data),
369 .local = ipa_mem_local_data,
370 .imem_addr = 0x146bd000,
371 .imem_size = 0x00002000,
372 .smem_id = 497,
373 .smem_size = 0x00002000,
374};
375
376/* Interconnect bandwidths are in 1000 byte/second units */
377static const struct ipa_interconnect_data ipa_interconnect_data[] = {
378 {
379 .name = "memory",
380 .peak_bandwidth = 600000, /* 600 MBps */
381 .average_bandwidth = 80000, /* 80 MBps */
382 },
383 /* Average bandwidth is unused for the next two interconnects */
384 {
385 .name = "imem",
386 .peak_bandwidth = 350000, /* 350 MBps */
387 .average_bandwidth = 0, /* unused */
388 },
389 {
390 .name = "config",
391 .peak_bandwidth = 40000, /* 40 MBps */
392 .average_bandwidth = 0, /* unused */
393 },
394};
395
396/* Clock and interconnect configuration data for an SoC having IPA v3.5.1 */
397static const struct ipa_clock_data ipa_clock_data = {
398 .core_clock_rate = 75 * 1000 * 1000, /* Hz */
399 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
400 .interconnect_data = ipa_interconnect_data,
401};
402
403/* Configuration data for an SoC having IPA v3.5.1 */
404const struct ipa_data ipa_data_v3_5_1 = {
405 .version = IPA_VERSION_3_5_1,
406 .backward_compat = BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK |
407 BCR_TX_NOT_USING_BRESP_FMASK |
408 BCR_SUSPEND_L2_IRQ_FMASK |
409 BCR_HOLB_DROP_L2_IRQ_FMASK |
410 BCR_DUAL_TX_FMASK,
411 .qsb_count = ARRAY_SIZE(ipa_qsb_data),
412 .qsb_data = ipa_qsb_data,
413 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
414 .endpoint_data = ipa_gsi_endpoint_data,
415 .resource_data = &ipa_resource_data,
416 .mem_data = &ipa_mem_data,
417 .clock_data = &ipa_clock_data,
418};