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1/*
2 * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device.
3 *
4 * This is a new flat driver which is based on the original emac_lite
5 * driver from John Williams <john.williams@xilinx.com>.
6 *
7 * 2007 - 2013 (c) Xilinx, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/module.h>
16#include <linux/uaccess.h>
17#include <linux/netdevice.h>
18#include <linux/etherdevice.h>
19#include <linux/skbuff.h>
20#include <linux/io.h>
21#include <linux/slab.h>
22#include <linux/of_address.h>
23#include <linux/of_device.h>
24#include <linux/of_platform.h>
25#include <linux/of_mdio.h>
26#include <linux/of_net.h>
27#include <linux/phy.h>
28#include <linux/interrupt.h>
29
30#define DRIVER_NAME "xilinx_emaclite"
31
32/* Register offsets for the EmacLite Core */
33#define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */
34#define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */
35#define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */
36#define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */
37#define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */
38#define XEL_GIER_OFFSET 0x07F8 /* GIE Register */
39#define XEL_TSR_OFFSET 0x07FC /* Tx status */
40#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
41
42#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
43#define XEL_RPLR_OFFSET 0x100C /* Rx packet length */
44#define XEL_RSR_OFFSET 0x17FC /* Rx status */
45
46#define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */
47
48/* MDIO Address Register Bit Masks */
49#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
50#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
51#define XEL_MDIOADDR_PHYADR_SHIFT 5
52#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
53
54/* MDIO Write Data Register Bit Masks */
55#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
56
57/* MDIO Read Data Register Bit Masks */
58#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
59
60/* MDIO Control Register Bit Masks */
61#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
62#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
63
64/* Global Interrupt Enable Register (GIER) Bit Masks */
65#define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */
66
67/* Transmit Status Register (TSR) Bit Masks */
68#define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */
69#define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */
70#define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */
71#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit
72 * only. This is not documented
73 * in the HW spec */
74
75/* Define for programming the MAC address into the EmacLite */
76#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
77
78/* Receive Status Register (RSR) */
79#define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */
80#define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */
81
82/* Transmit Packet Length Register (TPLR) */
83#define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */
84
85/* Receive Packet Length Register (RPLR) */
86#define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */
87
88#define XEL_HEADER_OFFSET 12 /* Offset to length field */
89#define XEL_HEADER_SHIFT 16 /* Shift value for length */
90
91/* General Ethernet Definitions */
92#define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */
93#define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */
94
95
96
97#define TX_TIMEOUT (60*HZ) /* Tx timeout is 60 seconds. */
98#define ALIGNMENT 4
99
100/* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */
101#define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32) adr)) % ALIGNMENT)
102
103#ifdef __BIG_ENDIAN
104#define xemaclite_readl ioread32be
105#define xemaclite_writel iowrite32be
106#else
107#define xemaclite_readl ioread32
108#define xemaclite_writel iowrite32
109#endif
110
111/**
112 * struct net_local - Our private per device data
113 * @ndev: instance of the network device
114 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW
115 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW
116 * @next_tx_buf_to_use: next Tx buffer to write to
117 * @next_rx_buf_to_use: next Rx buffer to read from
118 * @base_addr: base address of the Emaclite device
119 * @reset_lock: lock used for synchronization
120 * @deferred_skb: holds an skb (for transmission at a later time) when the
121 * Tx buffer is not free
122 * @phy_dev: pointer to the PHY device
123 * @phy_node: pointer to the PHY device node
124 * @mii_bus: pointer to the MII bus
125 * @last_link: last link status
126 * @has_mdio: indicates whether MDIO is included in the HW
127 */
128struct net_local {
129
130 struct net_device *ndev;
131
132 bool tx_ping_pong;
133 bool rx_ping_pong;
134 u32 next_tx_buf_to_use;
135 u32 next_rx_buf_to_use;
136 void __iomem *base_addr;
137
138 spinlock_t reset_lock;
139 struct sk_buff *deferred_skb;
140
141 struct phy_device *phy_dev;
142 struct device_node *phy_node;
143
144 struct mii_bus *mii_bus;
145
146 int last_link;
147 bool has_mdio;
148};
149
150
151/*************************/
152/* EmacLite driver calls */
153/*************************/
154
155/**
156 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device
157 * @drvdata: Pointer to the Emaclite device private data
158 *
159 * This function enables the Tx and Rx interrupts for the Emaclite device along
160 * with the Global Interrupt Enable.
161 */
162static void xemaclite_enable_interrupts(struct net_local *drvdata)
163{
164 u32 reg_data;
165
166 /* Enable the Tx interrupts for the first Buffer */
167 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
168 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
169 drvdata->base_addr + XEL_TSR_OFFSET);
170
171 /* Enable the Rx interrupts for the first buffer */
172 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
173
174 /* Enable the Global Interrupt Enable */
175 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
176}
177
178/**
179 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device
180 * @drvdata: Pointer to the Emaclite device private data
181 *
182 * This function disables the Tx and Rx interrupts for the Emaclite device,
183 * along with the Global Interrupt Enable.
184 */
185static void xemaclite_disable_interrupts(struct net_local *drvdata)
186{
187 u32 reg_data;
188
189 /* Disable the Global Interrupt Enable */
190 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
191
192 /* Disable the Tx interrupts for the first buffer */
193 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
194 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),
195 drvdata->base_addr + XEL_TSR_OFFSET);
196
197 /* Disable the Rx interrupts for the first buffer */
198 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET);
199 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),
200 drvdata->base_addr + XEL_RSR_OFFSET);
201}
202
203/**
204 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address
205 * @src_ptr: Void pointer to the 16-bit aligned source address
206 * @dest_ptr: Pointer to the 32-bit aligned destination address
207 * @length: Number bytes to write from source to destination
208 *
209 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned
210 * address in the EmacLite device.
211 */
212static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr,
213 unsigned length)
214{
215 u32 align_buffer;
216 u32 *to_u32_ptr;
217 u16 *from_u16_ptr, *to_u16_ptr;
218
219 to_u32_ptr = dest_ptr;
220 from_u16_ptr = src_ptr;
221 align_buffer = 0;
222
223 for (; length > 3; length -= 4) {
224 to_u16_ptr = (u16 *)&align_buffer;
225 *to_u16_ptr++ = *from_u16_ptr++;
226 *to_u16_ptr++ = *from_u16_ptr++;
227
228 /* This barrier resolves occasional issues seen around
229 * cases where the data is not properly flushed out
230 * from the processor store buffers to the destination
231 * memory locations.
232 */
233 wmb();
234
235 /* Output a word */
236 *to_u32_ptr++ = align_buffer;
237 }
238 if (length) {
239 u8 *from_u8_ptr, *to_u8_ptr;
240
241 /* Set up to output the remaining data */
242 align_buffer = 0;
243 to_u8_ptr = (u8 *) &align_buffer;
244 from_u8_ptr = (u8 *) from_u16_ptr;
245
246 /* Output the remaining data */
247 for (; length > 0; length--)
248 *to_u8_ptr++ = *from_u8_ptr++;
249
250 /* This barrier resolves occasional issues seen around
251 * cases where the data is not properly flushed out
252 * from the processor store buffers to the destination
253 * memory locations.
254 */
255 wmb();
256 *to_u32_ptr = align_buffer;
257 }
258}
259
260/**
261 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer
262 * @src_ptr: Pointer to the 32-bit aligned source address
263 * @dest_ptr: Pointer to the 16-bit aligned destination address
264 * @length: Number bytes to read from source to destination
265 *
266 * This function reads data from a 32-bit aligned address in the EmacLite device
267 * to a 16-bit aligned buffer.
268 */
269static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr,
270 unsigned length)
271{
272 u16 *to_u16_ptr, *from_u16_ptr;
273 u32 *from_u32_ptr;
274 u32 align_buffer;
275
276 from_u32_ptr = src_ptr;
277 to_u16_ptr = (u16 *) dest_ptr;
278
279 for (; length > 3; length -= 4) {
280 /* Copy each word into the temporary buffer */
281 align_buffer = *from_u32_ptr++;
282 from_u16_ptr = (u16 *)&align_buffer;
283
284 /* Read data from source */
285 *to_u16_ptr++ = *from_u16_ptr++;
286 *to_u16_ptr++ = *from_u16_ptr++;
287 }
288
289 if (length) {
290 u8 *to_u8_ptr, *from_u8_ptr;
291
292 /* Set up to read the remaining data */
293 to_u8_ptr = (u8 *) to_u16_ptr;
294 align_buffer = *from_u32_ptr++;
295 from_u8_ptr = (u8 *) &align_buffer;
296
297 /* Read the remaining data */
298 for (; length > 0; length--)
299 *to_u8_ptr = *from_u8_ptr;
300 }
301}
302
303/**
304 * xemaclite_send_data - Send an Ethernet frame
305 * @drvdata: Pointer to the Emaclite device private data
306 * @data: Pointer to the data to be sent
307 * @byte_count: Total frame size, including header
308 *
309 * This function checks if the Tx buffer of the Emaclite device is free to send
310 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it
311 * returns an error.
312 *
313 * Return: 0 upon success or -1 if the buffer(s) are full.
314 *
315 * Note: The maximum Tx packet size can not be more than Ethernet header
316 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS.
317 */
318static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
319 unsigned int byte_count)
320{
321 u32 reg_data;
322 void __iomem *addr;
323
324 /* Determine the expected Tx buffer address */
325 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
326
327 /* If the length is too large, truncate it */
328 if (byte_count > ETH_FRAME_LEN)
329 byte_count = ETH_FRAME_LEN;
330
331 /* Check if the expected buffer is available */
332 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
333 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
334 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
335
336 /* Switch to next buffer if configured */
337 if (drvdata->tx_ping_pong != 0)
338 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET;
339 } else if (drvdata->tx_ping_pong != 0) {
340 /* If the expected buffer is full, try the other buffer,
341 * if it is configured in HW */
342
343 addr = (void __iomem __force *)((u32 __force)addr ^
344 XEL_BUFFER_OFFSET);
345 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
346
347 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
348 XEL_TSR_XMIT_ACTIVE_MASK)) != 0)
349 return -1; /* Buffers were full, return failure */
350 } else
351 return -1; /* Buffer was full, return failure */
352
353 /* Write the frame to the buffer */
354 xemaclite_aligned_write(data, (u32 __force *) addr, byte_count);
355
356 xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK),
357 addr + XEL_TPLR_OFFSET);
358
359 /* Update the Tx Status Register to indicate that there is a
360 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which
361 * is used by the interrupt handler to check whether a frame
362 * has been transmitted */
363 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
364 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK);
365 xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET);
366
367 return 0;
368}
369
370/**
371 * xemaclite_recv_data - Receive a frame
372 * @drvdata: Pointer to the Emaclite device private data
373 * @data: Address where the data is to be received
374 *
375 * This function is intended to be called from the interrupt context or
376 * with a wrapper which waits for the receive frame to be available.
377 *
378 * Return: Total number of bytes received
379 */
380static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen)
381{
382 void __iomem *addr;
383 u16 length, proto_type;
384 u32 reg_data;
385
386 /* Determine the expected buffer address */
387 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);
388
389 /* Verify which buffer has valid data */
390 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
391
392 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
393 if (drvdata->rx_ping_pong != 0)
394 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET;
395 } else {
396 /* The instance is out of sync, try other buffer if other
397 * buffer is configured, return 0 otherwise. If the instance is
398 * out of sync, do not update the 'next_rx_buf_to_use' since it
399 * will correct on subsequent calls */
400 if (drvdata->rx_ping_pong != 0)
401 addr = (void __iomem __force *)((u32 __force)addr ^
402 XEL_BUFFER_OFFSET);
403 else
404 return 0; /* No data was available */
405
406 /* Verify that buffer has valid data */
407 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
408 if ((reg_data & XEL_RSR_RECV_DONE_MASK) !=
409 XEL_RSR_RECV_DONE_MASK)
410 return 0; /* No data was available */
411 }
412
413 /* Get the protocol type of the ethernet frame that arrived */
414 proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET +
415 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) &
416 XEL_RPLR_LENGTH_MASK);
417
418 /* Check if received ethernet frame is a raw ethernet frame
419 * or an IP packet or an ARP packet */
420 if (proto_type > ETH_DATA_LEN) {
421
422 if (proto_type == ETH_P_IP) {
423 length = ((ntohl(xemaclite_readl(addr +
424 XEL_HEADER_IP_LENGTH_OFFSET +
425 XEL_RXBUFF_OFFSET)) >>
426 XEL_HEADER_SHIFT) &
427 XEL_RPLR_LENGTH_MASK);
428 length = min_t(u16, length, ETH_DATA_LEN);
429 length += ETH_HLEN + ETH_FCS_LEN;
430
431 } else if (proto_type == ETH_P_ARP)
432 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN;
433 else
434 /* Field contains type other than IP or ARP, use max
435 * frame size and let user parse it */
436 length = ETH_FRAME_LEN + ETH_FCS_LEN;
437 } else
438 /* Use the length in the frame, plus the header and trailer */
439 length = proto_type + ETH_HLEN + ETH_FCS_LEN;
440
441 if (WARN_ON(length > maxlen))
442 length = maxlen;
443
444 /* Read from the EmacLite device */
445 xemaclite_aligned_read((u32 __force *) (addr + XEL_RXBUFF_OFFSET),
446 data, length);
447
448 /* Acknowledge the frame */
449 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
450 reg_data &= ~XEL_RSR_RECV_DONE_MASK;
451 xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET);
452
453 return length;
454}
455
456/**
457 * xemaclite_update_address - Update the MAC address in the device
458 * @drvdata: Pointer to the Emaclite device private data
459 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value)
460 *
461 * Tx must be idle and Rx should be idle for deterministic results.
462 * It is recommended that this function should be called after the
463 * initialization and before transmission of any packets from the device.
464 * The MAC address can be programmed using any of the two transmit
465 * buffers (if configured).
466 */
467static void xemaclite_update_address(struct net_local *drvdata,
468 u8 *address_ptr)
469{
470 void __iomem *addr;
471 u32 reg_data;
472
473 /* Determine the expected Tx buffer address */
474 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
475
476 xemaclite_aligned_write(address_ptr, (u32 __force *) addr, ETH_ALEN);
477
478 xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET);
479
480 /* Update the MAC address in the EmacLite */
481 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
482 xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET);
483
484 /* Wait for EmacLite to finish with the MAC address update */
485 while ((xemaclite_readl(addr + XEL_TSR_OFFSET) &
486 XEL_TSR_PROG_MAC_ADDR) != 0)
487 ;
488}
489
490/**
491 * xemaclite_set_mac_address - Set the MAC address for this device
492 * @dev: Pointer to the network device instance
493 * @addr: Void pointer to the sockaddr structure
494 *
495 * This function copies the HW address from the sockaddr strucutre to the
496 * net_device structure and updates the address in HW.
497 *
498 * Return: Error if the net device is busy or 0 if the addr is set
499 * successfully
500 */
501static int xemaclite_set_mac_address(struct net_device *dev, void *address)
502{
503 struct net_local *lp = netdev_priv(dev);
504 struct sockaddr *addr = address;
505
506 if (netif_running(dev))
507 return -EBUSY;
508
509 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
510 xemaclite_update_address(lp, dev->dev_addr);
511 return 0;
512}
513
514/**
515 * xemaclite_tx_timeout - Callback for Tx Timeout
516 * @dev: Pointer to the network device
517 *
518 * This function is called when Tx time out occurs for Emaclite device.
519 */
520static void xemaclite_tx_timeout(struct net_device *dev)
521{
522 struct net_local *lp = netdev_priv(dev);
523 unsigned long flags;
524
525 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n",
526 TX_TIMEOUT * 1000UL / HZ);
527
528 dev->stats.tx_errors++;
529
530 /* Reset the device */
531 spin_lock_irqsave(&lp->reset_lock, flags);
532
533 /* Shouldn't really be necessary, but shouldn't hurt */
534 netif_stop_queue(dev);
535
536 xemaclite_disable_interrupts(lp);
537 xemaclite_enable_interrupts(lp);
538
539 if (lp->deferred_skb) {
540 dev_kfree_skb(lp->deferred_skb);
541 lp->deferred_skb = NULL;
542 dev->stats.tx_errors++;
543 }
544
545 /* To exclude tx timeout */
546 netif_trans_update(dev); /* prevent tx timeout */
547
548 /* We're all ready to go. Start the queue */
549 netif_wake_queue(dev);
550 spin_unlock_irqrestore(&lp->reset_lock, flags);
551}
552
553/**********************/
554/* Interrupt Handlers */
555/**********************/
556
557/**
558 * xemaclite_tx_handler - Interrupt handler for frames sent
559 * @dev: Pointer to the network device
560 *
561 * This function updates the number of packets transmitted and handles the
562 * deferred skb, if there is one.
563 */
564static void xemaclite_tx_handler(struct net_device *dev)
565{
566 struct net_local *lp = netdev_priv(dev);
567
568 dev->stats.tx_packets++;
569 if (lp->deferred_skb) {
570 if (xemaclite_send_data(lp,
571 (u8 *) lp->deferred_skb->data,
572 lp->deferred_skb->len) != 0)
573 return;
574 else {
575 dev->stats.tx_bytes += lp->deferred_skb->len;
576 dev_kfree_skb_irq(lp->deferred_skb);
577 lp->deferred_skb = NULL;
578 netif_trans_update(dev); /* prevent tx timeout */
579 netif_wake_queue(dev);
580 }
581 }
582}
583
584/**
585 * xemaclite_rx_handler- Interrupt handler for frames received
586 * @dev: Pointer to the network device
587 *
588 * This function allocates memory for a socket buffer, fills it with data
589 * received and hands it over to the TCP/IP stack.
590 */
591static void xemaclite_rx_handler(struct net_device *dev)
592{
593 struct net_local *lp = netdev_priv(dev);
594 struct sk_buff *skb;
595 unsigned int align;
596 u32 len;
597
598 len = ETH_FRAME_LEN + ETH_FCS_LEN;
599 skb = netdev_alloc_skb(dev, len + ALIGNMENT);
600 if (!skb) {
601 /* Couldn't get memory. */
602 dev->stats.rx_dropped++;
603 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n");
604 return;
605 }
606
607 /*
608 * A new skb should have the data halfword aligned, but this code is
609 * here just in case that isn't true. Calculate how many
610 * bytes we should reserve to get the data to start on a word
611 * boundary */
612 align = BUFFER_ALIGN(skb->data);
613 if (align)
614 skb_reserve(skb, align);
615
616 skb_reserve(skb, 2);
617
618 len = xemaclite_recv_data(lp, (u8 *) skb->data, len);
619
620 if (!len) {
621 dev->stats.rx_errors++;
622 dev_kfree_skb_irq(skb);
623 return;
624 }
625
626 skb_put(skb, len); /* Tell the skb how much data we got */
627
628 skb->protocol = eth_type_trans(skb, dev);
629 skb_checksum_none_assert(skb);
630
631 dev->stats.rx_packets++;
632 dev->stats.rx_bytes += len;
633
634 if (!skb_defer_rx_timestamp(skb))
635 netif_rx(skb); /* Send the packet upstream */
636}
637
638/**
639 * xemaclite_interrupt - Interrupt handler for this driver
640 * @irq: Irq of the Emaclite device
641 * @dev_id: Void pointer to the network device instance used as callback
642 * reference
643 *
644 * This function handles the Tx and Rx interrupts of the EmacLite device.
645 */
646static irqreturn_t xemaclite_interrupt(int irq, void *dev_id)
647{
648 bool tx_complete = false;
649 struct net_device *dev = dev_id;
650 struct net_local *lp = netdev_priv(dev);
651 void __iomem *base_addr = lp->base_addr;
652 u32 tx_status;
653
654 /* Check if there is Rx Data available */
655 if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) &
656 XEL_RSR_RECV_DONE_MASK) ||
657 (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
658 & XEL_RSR_RECV_DONE_MASK))
659
660 xemaclite_rx_handler(dev);
661
662 /* Check if the Transmission for the first buffer is completed */
663 tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET);
664 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
665 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
666
667 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
668 xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET);
669
670 tx_complete = true;
671 }
672
673 /* Check if the Transmission for the second buffer is completed */
674 tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
675 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
676 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
677
678 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
679 xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +
680 XEL_TSR_OFFSET);
681
682 tx_complete = true;
683 }
684
685 /* If there was a Tx interrupt, call the Tx Handler */
686 if (tx_complete != 0)
687 xemaclite_tx_handler(dev);
688
689 return IRQ_HANDLED;
690}
691
692/**********************/
693/* MDIO Bus functions */
694/**********************/
695
696/**
697 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use
698 * @lp: Pointer to the Emaclite device private data
699 *
700 * This function waits till the device is ready to accept a new MDIO
701 * request.
702 *
703 * Return: 0 for success or ETIMEDOUT for a timeout
704 */
705
706static int xemaclite_mdio_wait(struct net_local *lp)
707{
708 unsigned long end = jiffies + 2;
709
710 /* wait for the MDIO interface to not be busy or timeout
711 after some time.
712 */
713 while (xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) &
714 XEL_MDIOCTRL_MDIOSTS_MASK) {
715 if (time_before_eq(end, jiffies)) {
716 WARN_ON(1);
717 return -ETIMEDOUT;
718 }
719 msleep(1);
720 }
721 return 0;
722}
723
724/**
725 * xemaclite_mdio_read - Read from a given MII management register
726 * @bus: the mii_bus struct
727 * @phy_id: the phy address
728 * @reg: register number to read from
729 *
730 * This function waits till the device is ready to accept a new MDIO
731 * request and then writes the phy address to the MDIO Address register
732 * and reads data from MDIO Read Data register, when its available.
733 *
734 * Return: Value read from the MII management register
735 */
736static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg)
737{
738 struct net_local *lp = bus->priv;
739 u32 ctrl_reg;
740 u32 rc;
741
742 if (xemaclite_mdio_wait(lp))
743 return -ETIMEDOUT;
744
745 /* Write the PHY address, register number and set the OP bit in the
746 * MDIO Address register. Set the Status bit in the MDIO Control
747 * register to start a MDIO read transaction.
748 */
749 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
750 xemaclite_writel(XEL_MDIOADDR_OP_MASK |
751 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
752 lp->base_addr + XEL_MDIOADDR_OFFSET);
753 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
754 lp->base_addr + XEL_MDIOCTRL_OFFSET);
755
756 if (xemaclite_mdio_wait(lp))
757 return -ETIMEDOUT;
758
759 rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET);
760
761 dev_dbg(&lp->ndev->dev,
762 "xemaclite_mdio_read(phy_id=%i, reg=%x) == %x\n",
763 phy_id, reg, rc);
764
765 return rc;
766}
767
768/**
769 * xemaclite_mdio_write - Write to a given MII management register
770 * @bus: the mii_bus struct
771 * @phy_id: the phy address
772 * @reg: register number to write to
773 * @val: value to write to the register number specified by reg
774 *
775 * This function waits till the device is ready to accept a new MDIO
776 * request and then writes the val to the MDIO Write Data register.
777 */
778static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg,
779 u16 val)
780{
781 struct net_local *lp = bus->priv;
782 u32 ctrl_reg;
783
784 dev_dbg(&lp->ndev->dev,
785 "xemaclite_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
786 phy_id, reg, val);
787
788 if (xemaclite_mdio_wait(lp))
789 return -ETIMEDOUT;
790
791 /* Write the PHY address, register number and clear the OP bit in the
792 * MDIO Address register and then write the value into the MDIO Write
793 * Data register. Finally, set the Status bit in the MDIO Control
794 * register to start a MDIO write transaction.
795 */
796 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
797 xemaclite_writel(~XEL_MDIOADDR_OP_MASK &
798 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
799 lp->base_addr + XEL_MDIOADDR_OFFSET);
800 xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);
801 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
802 lp->base_addr + XEL_MDIOCTRL_OFFSET);
803
804 return 0;
805}
806
807/**
808 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device
809 * @lp: Pointer to the Emaclite device private data
810 * @ofdev: Pointer to OF device structure
811 *
812 * This function enables MDIO bus in the Emaclite device and registers a
813 * mii_bus.
814 *
815 * Return: 0 upon success or a negative error upon failure
816 */
817static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev)
818{
819 struct mii_bus *bus;
820 int rc;
821 struct resource res;
822 struct device_node *np = of_get_parent(lp->phy_node);
823 struct device_node *npp;
824
825 /* Don't register the MDIO bus if the phy_node or its parent node
826 * can't be found.
827 */
828 if (!np) {
829 dev_err(dev, "Failed to register mdio bus.\n");
830 return -ENODEV;
831 }
832 npp = of_get_parent(np);
833
834 of_address_to_resource(npp, 0, &res);
835 if (lp->ndev->mem_start != res.start) {
836 struct phy_device *phydev;
837 phydev = of_phy_find_device(lp->phy_node);
838 if (!phydev)
839 dev_info(dev,
840 "MDIO of the phy is not registered yet\n");
841 else
842 put_device(&phydev->mdio.dev);
843 return 0;
844 }
845
846 /* Enable the MDIO bus by asserting the enable bit in MDIO Control
847 * register.
848 */
849 xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK,
850 lp->base_addr + XEL_MDIOCTRL_OFFSET);
851
852 bus = mdiobus_alloc();
853 if (!bus) {
854 dev_err(dev, "Failed to allocate mdiobus\n");
855 return -ENOMEM;
856 }
857
858 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
859 (unsigned long long)res.start);
860 bus->priv = lp;
861 bus->name = "Xilinx Emaclite MDIO";
862 bus->read = xemaclite_mdio_read;
863 bus->write = xemaclite_mdio_write;
864 bus->parent = dev;
865
866 lp->mii_bus = bus;
867
868 rc = of_mdiobus_register(bus, np);
869 if (rc) {
870 dev_err(dev, "Failed to register mdio bus.\n");
871 goto err_register;
872 }
873
874 return 0;
875
876err_register:
877 mdiobus_free(bus);
878 return rc;
879}
880
881/**
882 * xemaclite_adjust_link - Link state callback for the Emaclite device
883 * @ndev: pointer to net_device struct
884 *
885 * There's nothing in the Emaclite device to be configured when the link
886 * state changes. We just print the status.
887 */
888static void xemaclite_adjust_link(struct net_device *ndev)
889{
890 struct net_local *lp = netdev_priv(ndev);
891 struct phy_device *phy = lp->phy_dev;
892 int link_state;
893
894 /* hash together the state values to decide if something has changed */
895 link_state = phy->speed | (phy->duplex << 1) | phy->link;
896
897 if (lp->last_link != link_state) {
898 lp->last_link = link_state;
899 phy_print_status(phy);
900 }
901}
902
903/**
904 * xemaclite_open - Open the network device
905 * @dev: Pointer to the network device
906 *
907 * This function sets the MAC address, requests an IRQ and enables interrupts
908 * for the Emaclite device and starts the Tx queue.
909 * It also connects to the phy device, if MDIO is included in Emaclite device.
910 */
911static int xemaclite_open(struct net_device *dev)
912{
913 struct net_local *lp = netdev_priv(dev);
914 int retval;
915
916 /* Just to be safe, stop the device first */
917 xemaclite_disable_interrupts(lp);
918
919 if (lp->phy_node) {
920 u32 bmcr;
921
922 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
923 xemaclite_adjust_link, 0,
924 PHY_INTERFACE_MODE_MII);
925 if (!lp->phy_dev) {
926 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n");
927 return -ENODEV;
928 }
929
930 /* EmacLite doesn't support giga-bit speeds */
931 lp->phy_dev->supported &= (PHY_BASIC_FEATURES);
932 lp->phy_dev->advertising = lp->phy_dev->supported;
933
934 /* Don't advertise 1000BASE-T Full/Half duplex speeds */
935 phy_write(lp->phy_dev, MII_CTRL1000, 0);
936
937 /* Advertise only 10 and 100mbps full/half duplex speeds */
938 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL |
939 ADVERTISE_CSMA);
940
941 /* Restart auto negotiation */
942 bmcr = phy_read(lp->phy_dev, MII_BMCR);
943 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
944 phy_write(lp->phy_dev, MII_BMCR, bmcr);
945
946 phy_start(lp->phy_dev);
947 }
948
949 /* Set the MAC address each time opened */
950 xemaclite_update_address(lp, dev->dev_addr);
951
952 /* Grab the IRQ */
953 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev);
954 if (retval) {
955 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n",
956 dev->irq);
957 if (lp->phy_dev)
958 phy_disconnect(lp->phy_dev);
959 lp->phy_dev = NULL;
960
961 return retval;
962 }
963
964 /* Enable Interrupts */
965 xemaclite_enable_interrupts(lp);
966
967 /* We're ready to go */
968 netif_start_queue(dev);
969
970 return 0;
971}
972
973/**
974 * xemaclite_close - Close the network device
975 * @dev: Pointer to the network device
976 *
977 * This function stops the Tx queue, disables interrupts and frees the IRQ for
978 * the Emaclite device.
979 * It also disconnects the phy device associated with the Emaclite device.
980 */
981static int xemaclite_close(struct net_device *dev)
982{
983 struct net_local *lp = netdev_priv(dev);
984
985 netif_stop_queue(dev);
986 xemaclite_disable_interrupts(lp);
987 free_irq(dev->irq, dev);
988
989 if (lp->phy_dev)
990 phy_disconnect(lp->phy_dev);
991 lp->phy_dev = NULL;
992
993 return 0;
994}
995
996/**
997 * xemaclite_send - Transmit a frame
998 * @orig_skb: Pointer to the socket buffer to be transmitted
999 * @dev: Pointer to the network device
1000 *
1001 * This function checks if the Tx buffer of the Emaclite device is free to send
1002 * data. If so, it fills the Tx buffer with data from socket buffer data,
1003 * updates the stats and frees the socket buffer. The Tx completion is signaled
1004 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is
1005 * deferred and the Tx queue is stopped so that the deferred socket buffer can
1006 * be transmitted when the Emaclite device is free to transmit data.
1007 *
1008 * Return: 0, always.
1009 */
1010static int xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev)
1011{
1012 struct net_local *lp = netdev_priv(dev);
1013 struct sk_buff *new_skb;
1014 unsigned int len;
1015 unsigned long flags;
1016
1017 len = orig_skb->len;
1018
1019 new_skb = orig_skb;
1020
1021 spin_lock_irqsave(&lp->reset_lock, flags);
1022 if (xemaclite_send_data(lp, (u8 *) new_skb->data, len) != 0) {
1023 /* If the Emaclite Tx buffer is busy, stop the Tx queue and
1024 * defer the skb for transmission during the ISR, after the
1025 * current transmission is complete */
1026 netif_stop_queue(dev);
1027 lp->deferred_skb = new_skb;
1028 /* Take the time stamp now, since we can't do this in an ISR. */
1029 skb_tx_timestamp(new_skb);
1030 spin_unlock_irqrestore(&lp->reset_lock, flags);
1031 return 0;
1032 }
1033 spin_unlock_irqrestore(&lp->reset_lock, flags);
1034
1035 skb_tx_timestamp(new_skb);
1036
1037 dev->stats.tx_bytes += len;
1038 dev_consume_skb_any(new_skb);
1039
1040 return 0;
1041}
1042
1043/**
1044 * get_bool - Get a parameter from the OF device
1045 * @ofdev: Pointer to OF device structure
1046 * @s: Property to be retrieved
1047 *
1048 * This function looks for a property in the device node and returns the value
1049 * of the property if its found or 0 if the property is not found.
1050 *
1051 * Return: Value of the parameter if the parameter is found, or 0 otherwise
1052 */
1053static bool get_bool(struct platform_device *ofdev, const char *s)
1054{
1055 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL);
1056
1057 if (p) {
1058 return (bool)*p;
1059 } else {
1060 dev_warn(&ofdev->dev, "Parameter %s not found,"
1061 "defaulting to false\n", s);
1062 return false;
1063 }
1064}
1065
1066static const struct net_device_ops xemaclite_netdev_ops;
1067
1068/**
1069 * xemaclite_of_probe - Probe method for the Emaclite device.
1070 * @ofdev: Pointer to OF device structure
1071 * @match: Pointer to the structure used for matching a device
1072 *
1073 * This function probes for the Emaclite device in the device tree.
1074 * It initializes the driver data structure and the hardware, sets the MAC
1075 * address and registers the network device.
1076 * It also registers a mii_bus for the Emaclite device, if MDIO is included
1077 * in the device.
1078 *
1079 * Return: 0, if the driver is bound to the Emaclite device, or
1080 * a negative error if there is failure.
1081 */
1082static int xemaclite_of_probe(struct platform_device *ofdev)
1083{
1084 struct resource *res;
1085 struct net_device *ndev = NULL;
1086 struct net_local *lp = NULL;
1087 struct device *dev = &ofdev->dev;
1088 const void *mac_address;
1089
1090 int rc = 0;
1091
1092 dev_info(dev, "Device Tree Probing\n");
1093
1094 /* Create an ethernet device instance */
1095 ndev = alloc_etherdev(sizeof(struct net_local));
1096 if (!ndev)
1097 return -ENOMEM;
1098
1099 dev_set_drvdata(dev, ndev);
1100 SET_NETDEV_DEV(ndev, &ofdev->dev);
1101
1102 lp = netdev_priv(ndev);
1103 lp->ndev = ndev;
1104
1105 /* Get IRQ for the device */
1106 res = platform_get_resource(ofdev, IORESOURCE_IRQ, 0);
1107 if (!res) {
1108 dev_err(dev, "no IRQ found\n");
1109 rc = -ENXIO;
1110 goto error;
1111 }
1112
1113 ndev->irq = res->start;
1114
1115 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1116 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res);
1117 if (IS_ERR(lp->base_addr)) {
1118 rc = PTR_ERR(lp->base_addr);
1119 goto error;
1120 }
1121
1122 ndev->mem_start = res->start;
1123 ndev->mem_end = res->end;
1124
1125 spin_lock_init(&lp->reset_lock);
1126 lp->next_tx_buf_to_use = 0x0;
1127 lp->next_rx_buf_to_use = 0x0;
1128 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong");
1129 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong");
1130 mac_address = of_get_mac_address(ofdev->dev.of_node);
1131
1132 if (mac_address) {
1133 /* Set the MAC address. */
1134 memcpy(ndev->dev_addr, mac_address, ETH_ALEN);
1135 } else {
1136 dev_warn(dev, "No MAC address found, using random\n");
1137 eth_hw_addr_random(ndev);
1138 }
1139
1140 /* Clear the Tx CSR's in case this is a restart */
1141 xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET);
1142 xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
1143
1144 /* Set the MAC address in the EmacLite device */
1145 xemaclite_update_address(lp, ndev->dev_addr);
1146
1147 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0);
1148 rc = xemaclite_mdio_setup(lp, &ofdev->dev);
1149 if (rc)
1150 dev_warn(&ofdev->dev, "error registering MDIO bus\n");
1151
1152 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr);
1153
1154 ndev->netdev_ops = &xemaclite_netdev_ops;
1155 ndev->flags &= ~IFF_MULTICAST;
1156 ndev->watchdog_timeo = TX_TIMEOUT;
1157
1158 /* Finally, register the device */
1159 rc = register_netdev(ndev);
1160 if (rc) {
1161 dev_err(dev,
1162 "Cannot register network device, aborting\n");
1163 goto error;
1164 }
1165
1166 dev_info(dev,
1167 "Xilinx EmacLite at 0x%08X mapped to 0x%08X, irq=%d\n",
1168 (unsigned int __force)ndev->mem_start,
1169 (unsigned int __force)lp->base_addr, ndev->irq);
1170 return 0;
1171
1172error:
1173 free_netdev(ndev);
1174 return rc;
1175}
1176
1177/**
1178 * xemaclite_of_remove - Unbind the driver from the Emaclite device.
1179 * @of_dev: Pointer to OF device structure
1180 *
1181 * This function is called if a device is physically removed from the system or
1182 * if the driver module is being unloaded. It frees any resources allocated to
1183 * the device.
1184 *
1185 * Return: 0, always.
1186 */
1187static int xemaclite_of_remove(struct platform_device *of_dev)
1188{
1189 struct net_device *ndev = platform_get_drvdata(of_dev);
1190
1191 struct net_local *lp = netdev_priv(ndev);
1192
1193 /* Un-register the mii_bus, if configured */
1194 if (lp->has_mdio) {
1195 mdiobus_unregister(lp->mii_bus);
1196 mdiobus_free(lp->mii_bus);
1197 lp->mii_bus = NULL;
1198 }
1199
1200 unregister_netdev(ndev);
1201
1202 of_node_put(lp->phy_node);
1203 lp->phy_node = NULL;
1204
1205 free_netdev(ndev);
1206
1207 return 0;
1208}
1209
1210#ifdef CONFIG_NET_POLL_CONTROLLER
1211static void
1212xemaclite_poll_controller(struct net_device *ndev)
1213{
1214 disable_irq(ndev->irq);
1215 xemaclite_interrupt(ndev->irq, ndev);
1216 enable_irq(ndev->irq);
1217}
1218#endif
1219
1220static const struct net_device_ops xemaclite_netdev_ops = {
1221 .ndo_open = xemaclite_open,
1222 .ndo_stop = xemaclite_close,
1223 .ndo_start_xmit = xemaclite_send,
1224 .ndo_set_mac_address = xemaclite_set_mac_address,
1225 .ndo_tx_timeout = xemaclite_tx_timeout,
1226#ifdef CONFIG_NET_POLL_CONTROLLER
1227 .ndo_poll_controller = xemaclite_poll_controller,
1228#endif
1229};
1230
1231/* Match table for OF platform binding */
1232static const struct of_device_id xemaclite_of_match[] = {
1233 { .compatible = "xlnx,opb-ethernetlite-1.01.a", },
1234 { .compatible = "xlnx,opb-ethernetlite-1.01.b", },
1235 { .compatible = "xlnx,xps-ethernetlite-1.00.a", },
1236 { .compatible = "xlnx,xps-ethernetlite-2.00.a", },
1237 { .compatible = "xlnx,xps-ethernetlite-2.01.a", },
1238 { .compatible = "xlnx,xps-ethernetlite-3.00.a", },
1239 { /* end of list */ },
1240};
1241MODULE_DEVICE_TABLE(of, xemaclite_of_match);
1242
1243static struct platform_driver xemaclite_of_driver = {
1244 .driver = {
1245 .name = DRIVER_NAME,
1246 .of_match_table = xemaclite_of_match,
1247 },
1248 .probe = xemaclite_of_probe,
1249 .remove = xemaclite_of_remove,
1250};
1251
1252module_platform_driver(xemaclite_of_driver);
1253
1254MODULE_AUTHOR("Xilinx, Inc.");
1255MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver");
1256MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device.
4 *
5 * This is a new flat driver which is based on the original emac_lite
6 * driver from John Williams <john.williams@xilinx.com>.
7 *
8 * 2007 - 2013 (c) Xilinx, Inc.
9 */
10
11#include <linux/module.h>
12#include <linux/uaccess.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/skbuff.h>
16#include <linux/ethtool.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19#include <linux/of_address.h>
20#include <linux/of_device.h>
21#include <linux/of_platform.h>
22#include <linux/of_mdio.h>
23#include <linux/of_net.h>
24#include <linux/phy.h>
25#include <linux/interrupt.h>
26#include <linux/iopoll.h>
27
28#define DRIVER_NAME "xilinx_emaclite"
29
30/* Register offsets for the EmacLite Core */
31#define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */
32#define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */
33#define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */
34#define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */
35#define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */
36#define XEL_GIER_OFFSET 0x07F8 /* GIE Register */
37#define XEL_TSR_OFFSET 0x07FC /* Tx status */
38#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
39
40#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
41#define XEL_RPLR_OFFSET 0x100C /* Rx packet length */
42#define XEL_RSR_OFFSET 0x17FC /* Rx status */
43
44#define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */
45
46/* MDIO Address Register Bit Masks */
47#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
48#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
49#define XEL_MDIOADDR_PHYADR_SHIFT 5
50#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
51
52/* MDIO Write Data Register Bit Masks */
53#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
54
55/* MDIO Read Data Register Bit Masks */
56#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
57
58/* MDIO Control Register Bit Masks */
59#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
60#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
61
62/* Global Interrupt Enable Register (GIER) Bit Masks */
63#define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */
64
65/* Transmit Status Register (TSR) Bit Masks */
66#define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */
67#define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */
68#define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */
69#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit
70 * only. This is not documented
71 * in the HW spec
72 */
73
74/* Define for programming the MAC address into the EmacLite */
75#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
76
77/* Receive Status Register (RSR) */
78#define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */
79#define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */
80
81/* Transmit Packet Length Register (TPLR) */
82#define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */
83
84/* Receive Packet Length Register (RPLR) */
85#define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */
86
87#define XEL_HEADER_OFFSET 12 /* Offset to length field */
88#define XEL_HEADER_SHIFT 16 /* Shift value for length */
89
90/* General Ethernet Definitions */
91#define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */
92#define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */
93
94
95
96#define TX_TIMEOUT (60 * HZ) /* Tx timeout is 60 seconds. */
97#define ALIGNMENT 4
98
99/* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */
100#define BUFFER_ALIGN(adr) ((ALIGNMENT - ((uintptr_t)adr)) % ALIGNMENT)
101
102#ifdef __BIG_ENDIAN
103#define xemaclite_readl ioread32be
104#define xemaclite_writel iowrite32be
105#else
106#define xemaclite_readl ioread32
107#define xemaclite_writel iowrite32
108#endif
109
110/**
111 * struct net_local - Our private per device data
112 * @ndev: instance of the network device
113 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW
114 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW
115 * @next_tx_buf_to_use: next Tx buffer to write to
116 * @next_rx_buf_to_use: next Rx buffer to read from
117 * @base_addr: base address of the Emaclite device
118 * @reset_lock: lock used for synchronization
119 * @deferred_skb: holds an skb (for transmission at a later time) when the
120 * Tx buffer is not free
121 * @phy_dev: pointer to the PHY device
122 * @phy_node: pointer to the PHY device node
123 * @mii_bus: pointer to the MII bus
124 * @last_link: last link status
125 */
126struct net_local {
127
128 struct net_device *ndev;
129
130 bool tx_ping_pong;
131 bool rx_ping_pong;
132 u32 next_tx_buf_to_use;
133 u32 next_rx_buf_to_use;
134 void __iomem *base_addr;
135
136 spinlock_t reset_lock;
137 struct sk_buff *deferred_skb;
138
139 struct phy_device *phy_dev;
140 struct device_node *phy_node;
141
142 struct mii_bus *mii_bus;
143
144 int last_link;
145};
146
147
148/*************************/
149/* EmacLite driver calls */
150/*************************/
151
152/**
153 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device
154 * @drvdata: Pointer to the Emaclite device private data
155 *
156 * This function enables the Tx and Rx interrupts for the Emaclite device along
157 * with the Global Interrupt Enable.
158 */
159static void xemaclite_enable_interrupts(struct net_local *drvdata)
160{
161 u32 reg_data;
162
163 /* Enable the Tx interrupts for the first Buffer */
164 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
165 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK,
166 drvdata->base_addr + XEL_TSR_OFFSET);
167
168 /* Enable the Rx interrupts for the first buffer */
169 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET);
170
171 /* Enable the Global Interrupt Enable */
172 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
173}
174
175/**
176 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device
177 * @drvdata: Pointer to the Emaclite device private data
178 *
179 * This function disables the Tx and Rx interrupts for the Emaclite device,
180 * along with the Global Interrupt Enable.
181 */
182static void xemaclite_disable_interrupts(struct net_local *drvdata)
183{
184 u32 reg_data;
185
186 /* Disable the Global Interrupt Enable */
187 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET);
188
189 /* Disable the Tx interrupts for the first buffer */
190 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET);
191 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK),
192 drvdata->base_addr + XEL_TSR_OFFSET);
193
194 /* Disable the Rx interrupts for the first buffer */
195 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET);
196 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK),
197 drvdata->base_addr + XEL_RSR_OFFSET);
198}
199
200/**
201 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address
202 * @src_ptr: Void pointer to the 16-bit aligned source address
203 * @dest_ptr: Pointer to the 32-bit aligned destination address
204 * @length: Number bytes to write from source to destination
205 *
206 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned
207 * address in the EmacLite device.
208 */
209static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr,
210 unsigned length)
211{
212 u32 align_buffer;
213 u32 *to_u32_ptr;
214 u16 *from_u16_ptr, *to_u16_ptr;
215
216 to_u32_ptr = dest_ptr;
217 from_u16_ptr = src_ptr;
218 align_buffer = 0;
219
220 for (; length > 3; length -= 4) {
221 to_u16_ptr = (u16 *)&align_buffer;
222 *to_u16_ptr++ = *from_u16_ptr++;
223 *to_u16_ptr++ = *from_u16_ptr++;
224
225 /* This barrier resolves occasional issues seen around
226 * cases where the data is not properly flushed out
227 * from the processor store buffers to the destination
228 * memory locations.
229 */
230 wmb();
231
232 /* Output a word */
233 *to_u32_ptr++ = align_buffer;
234 }
235 if (length) {
236 u8 *from_u8_ptr, *to_u8_ptr;
237
238 /* Set up to output the remaining data */
239 align_buffer = 0;
240 to_u8_ptr = (u8 *)&align_buffer;
241 from_u8_ptr = (u8 *)from_u16_ptr;
242
243 /* Output the remaining data */
244 for (; length > 0; length--)
245 *to_u8_ptr++ = *from_u8_ptr++;
246
247 /* This barrier resolves occasional issues seen around
248 * cases where the data is not properly flushed out
249 * from the processor store buffers to the destination
250 * memory locations.
251 */
252 wmb();
253 *to_u32_ptr = align_buffer;
254 }
255}
256
257/**
258 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer
259 * @src_ptr: Pointer to the 32-bit aligned source address
260 * @dest_ptr: Pointer to the 16-bit aligned destination address
261 * @length: Number bytes to read from source to destination
262 *
263 * This function reads data from a 32-bit aligned address in the EmacLite device
264 * to a 16-bit aligned buffer.
265 */
266static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr,
267 unsigned length)
268{
269 u16 *to_u16_ptr, *from_u16_ptr;
270 u32 *from_u32_ptr;
271 u32 align_buffer;
272
273 from_u32_ptr = src_ptr;
274 to_u16_ptr = (u16 *)dest_ptr;
275
276 for (; length > 3; length -= 4) {
277 /* Copy each word into the temporary buffer */
278 align_buffer = *from_u32_ptr++;
279 from_u16_ptr = (u16 *)&align_buffer;
280
281 /* Read data from source */
282 *to_u16_ptr++ = *from_u16_ptr++;
283 *to_u16_ptr++ = *from_u16_ptr++;
284 }
285
286 if (length) {
287 u8 *to_u8_ptr, *from_u8_ptr;
288
289 /* Set up to read the remaining data */
290 to_u8_ptr = (u8 *)to_u16_ptr;
291 align_buffer = *from_u32_ptr++;
292 from_u8_ptr = (u8 *)&align_buffer;
293
294 /* Read the remaining data */
295 for (; length > 0; length--)
296 *to_u8_ptr = *from_u8_ptr;
297 }
298}
299
300/**
301 * xemaclite_send_data - Send an Ethernet frame
302 * @drvdata: Pointer to the Emaclite device private data
303 * @data: Pointer to the data to be sent
304 * @byte_count: Total frame size, including header
305 *
306 * This function checks if the Tx buffer of the Emaclite device is free to send
307 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it
308 * returns an error.
309 *
310 * Return: 0 upon success or -1 if the buffer(s) are full.
311 *
312 * Note: The maximum Tx packet size can not be more than Ethernet header
313 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS.
314 */
315static int xemaclite_send_data(struct net_local *drvdata, u8 *data,
316 unsigned int byte_count)
317{
318 u32 reg_data;
319 void __iomem *addr;
320
321 /* Determine the expected Tx buffer address */
322 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
323
324 /* If the length is too large, truncate it */
325 if (byte_count > ETH_FRAME_LEN)
326 byte_count = ETH_FRAME_LEN;
327
328 /* Check if the expected buffer is available */
329 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
330 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
331 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) {
332
333 /* Switch to next buffer if configured */
334 if (drvdata->tx_ping_pong != 0)
335 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET;
336 } else if (drvdata->tx_ping_pong != 0) {
337 /* If the expected buffer is full, try the other buffer,
338 * if it is configured in HW
339 */
340
341 addr = (void __iomem __force *)((uintptr_t __force)addr ^
342 XEL_BUFFER_OFFSET);
343 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
344
345 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK |
346 XEL_TSR_XMIT_ACTIVE_MASK)) != 0)
347 return -1; /* Buffers were full, return failure */
348 } else
349 return -1; /* Buffer was full, return failure */
350
351 /* Write the frame to the buffer */
352 xemaclite_aligned_write(data, (u32 __force *)addr, byte_count);
353
354 xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK),
355 addr + XEL_TPLR_OFFSET);
356
357 /* Update the Tx Status Register to indicate that there is a
358 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which
359 * is used by the interrupt handler to check whether a frame
360 * has been transmitted
361 */
362 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
363 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK);
364 xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET);
365
366 return 0;
367}
368
369/**
370 * xemaclite_recv_data - Receive a frame
371 * @drvdata: Pointer to the Emaclite device private data
372 * @data: Address where the data is to be received
373 * @maxlen: Maximum supported ethernet packet length
374 *
375 * This function is intended to be called from the interrupt context or
376 * with a wrapper which waits for the receive frame to be available.
377 *
378 * Return: Total number of bytes received
379 */
380static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen)
381{
382 void __iomem *addr;
383 u16 length, proto_type;
384 u32 reg_data;
385
386 /* Determine the expected buffer address */
387 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use);
388
389 /* Verify which buffer has valid data */
390 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
391
392 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
393 if (drvdata->rx_ping_pong != 0)
394 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET;
395 } else {
396 /* The instance is out of sync, try other buffer if other
397 * buffer is configured, return 0 otherwise. If the instance is
398 * out of sync, do not update the 'next_rx_buf_to_use' since it
399 * will correct on subsequent calls
400 */
401 if (drvdata->rx_ping_pong != 0)
402 addr = (void __iomem __force *)
403 ((uintptr_t __force)addr ^
404 XEL_BUFFER_OFFSET);
405 else
406 return 0; /* No data was available */
407
408 /* Verify that buffer has valid data */
409 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
410 if ((reg_data & XEL_RSR_RECV_DONE_MASK) !=
411 XEL_RSR_RECV_DONE_MASK)
412 return 0; /* No data was available */
413 }
414
415 /* Get the protocol type of the ethernet frame that arrived
416 */
417 proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET +
418 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) &
419 XEL_RPLR_LENGTH_MASK);
420
421 /* Check if received ethernet frame is a raw ethernet frame
422 * or an IP packet or an ARP packet
423 */
424 if (proto_type > ETH_DATA_LEN) {
425
426 if (proto_type == ETH_P_IP) {
427 length = ((ntohl(xemaclite_readl(addr +
428 XEL_HEADER_IP_LENGTH_OFFSET +
429 XEL_RXBUFF_OFFSET)) >>
430 XEL_HEADER_SHIFT) &
431 XEL_RPLR_LENGTH_MASK);
432 length = min_t(u16, length, ETH_DATA_LEN);
433 length += ETH_HLEN + ETH_FCS_LEN;
434
435 } else if (proto_type == ETH_P_ARP)
436 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN;
437 else
438 /* Field contains type other than IP or ARP, use max
439 * frame size and let user parse it
440 */
441 length = ETH_FRAME_LEN + ETH_FCS_LEN;
442 } else
443 /* Use the length in the frame, plus the header and trailer */
444 length = proto_type + ETH_HLEN + ETH_FCS_LEN;
445
446 if (WARN_ON(length > maxlen))
447 length = maxlen;
448
449 /* Read from the EmacLite device */
450 xemaclite_aligned_read((u32 __force *)(addr + XEL_RXBUFF_OFFSET),
451 data, length);
452
453 /* Acknowledge the frame */
454 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET);
455 reg_data &= ~XEL_RSR_RECV_DONE_MASK;
456 xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET);
457
458 return length;
459}
460
461/**
462 * xemaclite_update_address - Update the MAC address in the device
463 * @drvdata: Pointer to the Emaclite device private data
464 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value)
465 *
466 * Tx must be idle and Rx should be idle for deterministic results.
467 * It is recommended that this function should be called after the
468 * initialization and before transmission of any packets from the device.
469 * The MAC address can be programmed using any of the two transmit
470 * buffers (if configured).
471 */
472static void xemaclite_update_address(struct net_local *drvdata,
473 u8 *address_ptr)
474{
475 void __iomem *addr;
476 u32 reg_data;
477
478 /* Determine the expected Tx buffer address */
479 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use;
480
481 xemaclite_aligned_write(address_ptr, (u32 __force *)addr, ETH_ALEN);
482
483 xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET);
484
485 /* Update the MAC address in the EmacLite */
486 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET);
487 xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET);
488
489 /* Wait for EmacLite to finish with the MAC address update */
490 while ((xemaclite_readl(addr + XEL_TSR_OFFSET) &
491 XEL_TSR_PROG_MAC_ADDR) != 0)
492 ;
493}
494
495/**
496 * xemaclite_set_mac_address - Set the MAC address for this device
497 * @dev: Pointer to the network device instance
498 * @address: Void pointer to the sockaddr structure
499 *
500 * This function copies the HW address from the sockaddr strucutre to the
501 * net_device structure and updates the address in HW.
502 *
503 * Return: Error if the net device is busy or 0 if the addr is set
504 * successfully
505 */
506static int xemaclite_set_mac_address(struct net_device *dev, void *address)
507{
508 struct net_local *lp = netdev_priv(dev);
509 struct sockaddr *addr = address;
510
511 if (netif_running(dev))
512 return -EBUSY;
513
514 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
515 xemaclite_update_address(lp, dev->dev_addr);
516 return 0;
517}
518
519/**
520 * xemaclite_tx_timeout - Callback for Tx Timeout
521 * @dev: Pointer to the network device
522 * @txqueue: Unused
523 *
524 * This function is called when Tx time out occurs for Emaclite device.
525 */
526static void xemaclite_tx_timeout(struct net_device *dev, unsigned int txqueue)
527{
528 struct net_local *lp = netdev_priv(dev);
529 unsigned long flags;
530
531 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n",
532 TX_TIMEOUT * 1000UL / HZ);
533
534 dev->stats.tx_errors++;
535
536 /* Reset the device */
537 spin_lock_irqsave(&lp->reset_lock, flags);
538
539 /* Shouldn't really be necessary, but shouldn't hurt */
540 netif_stop_queue(dev);
541
542 xemaclite_disable_interrupts(lp);
543 xemaclite_enable_interrupts(lp);
544
545 if (lp->deferred_skb) {
546 dev_kfree_skb(lp->deferred_skb);
547 lp->deferred_skb = NULL;
548 dev->stats.tx_errors++;
549 }
550
551 /* To exclude tx timeout */
552 netif_trans_update(dev); /* prevent tx timeout */
553
554 /* We're all ready to go. Start the queue */
555 netif_wake_queue(dev);
556 spin_unlock_irqrestore(&lp->reset_lock, flags);
557}
558
559/**********************/
560/* Interrupt Handlers */
561/**********************/
562
563/**
564 * xemaclite_tx_handler - Interrupt handler for frames sent
565 * @dev: Pointer to the network device
566 *
567 * This function updates the number of packets transmitted and handles the
568 * deferred skb, if there is one.
569 */
570static void xemaclite_tx_handler(struct net_device *dev)
571{
572 struct net_local *lp = netdev_priv(dev);
573
574 dev->stats.tx_packets++;
575
576 if (!lp->deferred_skb)
577 return;
578
579 if (xemaclite_send_data(lp, (u8 *)lp->deferred_skb->data,
580 lp->deferred_skb->len))
581 return;
582
583 dev->stats.tx_bytes += lp->deferred_skb->len;
584 dev_consume_skb_irq(lp->deferred_skb);
585 lp->deferred_skb = NULL;
586 netif_trans_update(dev); /* prevent tx timeout */
587 netif_wake_queue(dev);
588}
589
590/**
591 * xemaclite_rx_handler- Interrupt handler for frames received
592 * @dev: Pointer to the network device
593 *
594 * This function allocates memory for a socket buffer, fills it with data
595 * received and hands it over to the TCP/IP stack.
596 */
597static void xemaclite_rx_handler(struct net_device *dev)
598{
599 struct net_local *lp = netdev_priv(dev);
600 struct sk_buff *skb;
601 unsigned int align;
602 u32 len;
603
604 len = ETH_FRAME_LEN + ETH_FCS_LEN;
605 skb = netdev_alloc_skb(dev, len + ALIGNMENT);
606 if (!skb) {
607 /* Couldn't get memory. */
608 dev->stats.rx_dropped++;
609 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n");
610 return;
611 }
612
613 /* A new skb should have the data halfword aligned, but this code is
614 * here just in case that isn't true. Calculate how many
615 * bytes we should reserve to get the data to start on a word
616 * boundary
617 */
618 align = BUFFER_ALIGN(skb->data);
619 if (align)
620 skb_reserve(skb, align);
621
622 skb_reserve(skb, 2);
623
624 len = xemaclite_recv_data(lp, (u8 *)skb->data, len);
625
626 if (!len) {
627 dev->stats.rx_errors++;
628 dev_kfree_skb_irq(skb);
629 return;
630 }
631
632 skb_put(skb, len); /* Tell the skb how much data we got */
633
634 skb->protocol = eth_type_trans(skb, dev);
635 skb_checksum_none_assert(skb);
636
637 dev->stats.rx_packets++;
638 dev->stats.rx_bytes += len;
639
640 if (!skb_defer_rx_timestamp(skb))
641 netif_rx(skb); /* Send the packet upstream */
642}
643
644/**
645 * xemaclite_interrupt - Interrupt handler for this driver
646 * @irq: Irq of the Emaclite device
647 * @dev_id: Void pointer to the network device instance used as callback
648 * reference
649 *
650 * Return: IRQ_HANDLED
651 *
652 * This function handles the Tx and Rx interrupts of the EmacLite device.
653 */
654static irqreturn_t xemaclite_interrupt(int irq, void *dev_id)
655{
656 bool tx_complete = false;
657 struct net_device *dev = dev_id;
658 struct net_local *lp = netdev_priv(dev);
659 void __iomem *base_addr = lp->base_addr;
660 u32 tx_status;
661
662 /* Check if there is Rx Data available */
663 if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) &
664 XEL_RSR_RECV_DONE_MASK) ||
665 (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET)
666 & XEL_RSR_RECV_DONE_MASK))
667
668 xemaclite_rx_handler(dev);
669
670 /* Check if the Transmission for the first buffer is completed */
671 tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET);
672 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
673 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
674
675 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
676 xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET);
677
678 tx_complete = true;
679 }
680
681 /* Check if the Transmission for the second buffer is completed */
682 tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
683 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) &&
684 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) {
685
686 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK;
687 xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET +
688 XEL_TSR_OFFSET);
689
690 tx_complete = true;
691 }
692
693 /* If there was a Tx interrupt, call the Tx Handler */
694 if (tx_complete != 0)
695 xemaclite_tx_handler(dev);
696
697 return IRQ_HANDLED;
698}
699
700/**********************/
701/* MDIO Bus functions */
702/**********************/
703
704/**
705 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use
706 * @lp: Pointer to the Emaclite device private data
707 *
708 * This function waits till the device is ready to accept a new MDIO
709 * request.
710 *
711 * Return: 0 for success or ETIMEDOUT for a timeout
712 */
713
714static int xemaclite_mdio_wait(struct net_local *lp)
715{
716 u32 val;
717
718 /* wait for the MDIO interface to not be busy or timeout
719 * after some time.
720 */
721 return readx_poll_timeout(xemaclite_readl,
722 lp->base_addr + XEL_MDIOCTRL_OFFSET,
723 val, !(val & XEL_MDIOCTRL_MDIOSTS_MASK),
724 1000, 20000);
725}
726
727/**
728 * xemaclite_mdio_read - Read from a given MII management register
729 * @bus: the mii_bus struct
730 * @phy_id: the phy address
731 * @reg: register number to read from
732 *
733 * This function waits till the device is ready to accept a new MDIO
734 * request and then writes the phy address to the MDIO Address register
735 * and reads data from MDIO Read Data register, when its available.
736 *
737 * Return: Value read from the MII management register
738 */
739static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg)
740{
741 struct net_local *lp = bus->priv;
742 u32 ctrl_reg;
743 u32 rc;
744
745 if (xemaclite_mdio_wait(lp))
746 return -ETIMEDOUT;
747
748 /* Write the PHY address, register number and set the OP bit in the
749 * MDIO Address register. Set the Status bit in the MDIO Control
750 * register to start a MDIO read transaction.
751 */
752 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
753 xemaclite_writel(XEL_MDIOADDR_OP_MASK |
754 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
755 lp->base_addr + XEL_MDIOADDR_OFFSET);
756 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
757 lp->base_addr + XEL_MDIOCTRL_OFFSET);
758
759 if (xemaclite_mdio_wait(lp))
760 return -ETIMEDOUT;
761
762 rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET);
763
764 dev_dbg(&lp->ndev->dev,
765 "%s(phy_id=%i, reg=%x) == %x\n", __func__,
766 phy_id, reg, rc);
767
768 return rc;
769}
770
771/**
772 * xemaclite_mdio_write - Write to a given MII management register
773 * @bus: the mii_bus struct
774 * @phy_id: the phy address
775 * @reg: register number to write to
776 * @val: value to write to the register number specified by reg
777 *
778 * This function waits till the device is ready to accept a new MDIO
779 * request and then writes the val to the MDIO Write Data register.
780 *
781 * Return: 0 upon success or a negative error upon failure
782 */
783static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg,
784 u16 val)
785{
786 struct net_local *lp = bus->priv;
787 u32 ctrl_reg;
788
789 dev_dbg(&lp->ndev->dev,
790 "%s(phy_id=%i, reg=%x, val=%x)\n", __func__,
791 phy_id, reg, val);
792
793 if (xemaclite_mdio_wait(lp))
794 return -ETIMEDOUT;
795
796 /* Write the PHY address, register number and clear the OP bit in the
797 * MDIO Address register and then write the value into the MDIO Write
798 * Data register. Finally, set the Status bit in the MDIO Control
799 * register to start a MDIO write transaction.
800 */
801 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET);
802 xemaclite_writel(~XEL_MDIOADDR_OP_MASK &
803 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg),
804 lp->base_addr + XEL_MDIOADDR_OFFSET);
805 xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET);
806 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK,
807 lp->base_addr + XEL_MDIOCTRL_OFFSET);
808
809 return 0;
810}
811
812/**
813 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device
814 * @lp: Pointer to the Emaclite device private data
815 * @dev: Pointer to OF device structure
816 *
817 * This function enables MDIO bus in the Emaclite device and registers a
818 * mii_bus.
819 *
820 * Return: 0 upon success or a negative error upon failure
821 */
822static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev)
823{
824 struct mii_bus *bus;
825 int rc;
826 struct resource res;
827 struct device_node *np = of_get_parent(lp->phy_node);
828 struct device_node *npp;
829
830 /* Don't register the MDIO bus if the phy_node or its parent node
831 * can't be found.
832 */
833 if (!np) {
834 dev_err(dev, "Failed to register mdio bus.\n");
835 return -ENODEV;
836 }
837 npp = of_get_parent(np);
838
839 of_address_to_resource(npp, 0, &res);
840 if (lp->ndev->mem_start != res.start) {
841 struct phy_device *phydev;
842 phydev = of_phy_find_device(lp->phy_node);
843 if (!phydev)
844 dev_info(dev,
845 "MDIO of the phy is not registered yet\n");
846 else
847 put_device(&phydev->mdio.dev);
848 return 0;
849 }
850
851 /* Enable the MDIO bus by asserting the enable bit in MDIO Control
852 * register.
853 */
854 xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK,
855 lp->base_addr + XEL_MDIOCTRL_OFFSET);
856
857 bus = mdiobus_alloc();
858 if (!bus) {
859 dev_err(dev, "Failed to allocate mdiobus\n");
860 return -ENOMEM;
861 }
862
863 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
864 (unsigned long long)res.start);
865 bus->priv = lp;
866 bus->name = "Xilinx Emaclite MDIO";
867 bus->read = xemaclite_mdio_read;
868 bus->write = xemaclite_mdio_write;
869 bus->parent = dev;
870
871 rc = of_mdiobus_register(bus, np);
872 if (rc) {
873 dev_err(dev, "Failed to register mdio bus.\n");
874 goto err_register;
875 }
876
877 lp->mii_bus = bus;
878
879 return 0;
880
881err_register:
882 mdiobus_free(bus);
883 return rc;
884}
885
886/**
887 * xemaclite_adjust_link - Link state callback for the Emaclite device
888 * @ndev: pointer to net_device struct
889 *
890 * There's nothing in the Emaclite device to be configured when the link
891 * state changes. We just print the status.
892 */
893static void xemaclite_adjust_link(struct net_device *ndev)
894{
895 struct net_local *lp = netdev_priv(ndev);
896 struct phy_device *phy = lp->phy_dev;
897 int link_state;
898
899 /* hash together the state values to decide if something has changed */
900 link_state = phy->speed | (phy->duplex << 1) | phy->link;
901
902 if (lp->last_link != link_state) {
903 lp->last_link = link_state;
904 phy_print_status(phy);
905 }
906}
907
908/**
909 * xemaclite_open - Open the network device
910 * @dev: Pointer to the network device
911 *
912 * This function sets the MAC address, requests an IRQ and enables interrupts
913 * for the Emaclite device and starts the Tx queue.
914 * It also connects to the phy device, if MDIO is included in Emaclite device.
915 *
916 * Return: 0 on success. -ENODEV, if PHY cannot be connected.
917 * Non-zero error value on failure.
918 */
919static int xemaclite_open(struct net_device *dev)
920{
921 struct net_local *lp = netdev_priv(dev);
922 int retval;
923
924 /* Just to be safe, stop the device first */
925 xemaclite_disable_interrupts(lp);
926
927 if (lp->phy_node) {
928 u32 bmcr;
929
930 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
931 xemaclite_adjust_link, 0,
932 PHY_INTERFACE_MODE_MII);
933 if (!lp->phy_dev) {
934 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n");
935 return -ENODEV;
936 }
937
938 /* EmacLite doesn't support giga-bit speeds */
939 phy_set_max_speed(lp->phy_dev, SPEED_100);
940
941 /* Don't advertise 1000BASE-T Full/Half duplex speeds */
942 phy_write(lp->phy_dev, MII_CTRL1000, 0);
943
944 /* Advertise only 10 and 100mbps full/half duplex speeds */
945 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL |
946 ADVERTISE_CSMA);
947
948 /* Restart auto negotiation */
949 bmcr = phy_read(lp->phy_dev, MII_BMCR);
950 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
951 phy_write(lp->phy_dev, MII_BMCR, bmcr);
952
953 phy_start(lp->phy_dev);
954 }
955
956 /* Set the MAC address each time opened */
957 xemaclite_update_address(lp, dev->dev_addr);
958
959 /* Grab the IRQ */
960 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev);
961 if (retval) {
962 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n",
963 dev->irq);
964 if (lp->phy_dev)
965 phy_disconnect(lp->phy_dev);
966 lp->phy_dev = NULL;
967
968 return retval;
969 }
970
971 /* Enable Interrupts */
972 xemaclite_enable_interrupts(lp);
973
974 /* We're ready to go */
975 netif_start_queue(dev);
976
977 return 0;
978}
979
980/**
981 * xemaclite_close - Close the network device
982 * @dev: Pointer to the network device
983 *
984 * This function stops the Tx queue, disables interrupts and frees the IRQ for
985 * the Emaclite device.
986 * It also disconnects the phy device associated with the Emaclite device.
987 *
988 * Return: 0, always.
989 */
990static int xemaclite_close(struct net_device *dev)
991{
992 struct net_local *lp = netdev_priv(dev);
993
994 netif_stop_queue(dev);
995 xemaclite_disable_interrupts(lp);
996 free_irq(dev->irq, dev);
997
998 if (lp->phy_dev)
999 phy_disconnect(lp->phy_dev);
1000 lp->phy_dev = NULL;
1001
1002 return 0;
1003}
1004
1005/**
1006 * xemaclite_send - Transmit a frame
1007 * @orig_skb: Pointer to the socket buffer to be transmitted
1008 * @dev: Pointer to the network device
1009 *
1010 * This function checks if the Tx buffer of the Emaclite device is free to send
1011 * data. If so, it fills the Tx buffer with data from socket buffer data,
1012 * updates the stats and frees the socket buffer. The Tx completion is signaled
1013 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is
1014 * deferred and the Tx queue is stopped so that the deferred socket buffer can
1015 * be transmitted when the Emaclite device is free to transmit data.
1016 *
1017 * Return: NETDEV_TX_OK, always.
1018 */
1019static netdev_tx_t
1020xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev)
1021{
1022 struct net_local *lp = netdev_priv(dev);
1023 struct sk_buff *new_skb;
1024 unsigned int len;
1025 unsigned long flags;
1026
1027 len = orig_skb->len;
1028
1029 new_skb = orig_skb;
1030
1031 spin_lock_irqsave(&lp->reset_lock, flags);
1032 if (xemaclite_send_data(lp, (u8 *)new_skb->data, len) != 0) {
1033 /* If the Emaclite Tx buffer is busy, stop the Tx queue and
1034 * defer the skb for transmission during the ISR, after the
1035 * current transmission is complete
1036 */
1037 netif_stop_queue(dev);
1038 lp->deferred_skb = new_skb;
1039 /* Take the time stamp now, since we can't do this in an ISR. */
1040 skb_tx_timestamp(new_skb);
1041 spin_unlock_irqrestore(&lp->reset_lock, flags);
1042 return NETDEV_TX_OK;
1043 }
1044 spin_unlock_irqrestore(&lp->reset_lock, flags);
1045
1046 skb_tx_timestamp(new_skb);
1047
1048 dev->stats.tx_bytes += len;
1049 dev_consume_skb_any(new_skb);
1050
1051 return NETDEV_TX_OK;
1052}
1053
1054/**
1055 * get_bool - Get a parameter from the OF device
1056 * @ofdev: Pointer to OF device structure
1057 * @s: Property to be retrieved
1058 *
1059 * This function looks for a property in the device node and returns the value
1060 * of the property if its found or 0 if the property is not found.
1061 *
1062 * Return: Value of the parameter if the parameter is found, or 0 otherwise
1063 */
1064static bool get_bool(struct platform_device *ofdev, const char *s)
1065{
1066 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL);
1067
1068 if (!p) {
1069 dev_warn(&ofdev->dev, "Parameter %s not found, defaulting to false\n", s);
1070 return false;
1071 }
1072
1073 return (bool)*p;
1074}
1075
1076/**
1077 * xemaclite_ethtools_get_drvinfo - Get various Axi Emac Lite driver info
1078 * @ndev: Pointer to net_device structure
1079 * @ed: Pointer to ethtool_drvinfo structure
1080 *
1081 * This implements ethtool command for getting the driver information.
1082 * Issue "ethtool -i ethX" under linux prompt to execute this function.
1083 */
1084static void xemaclite_ethtools_get_drvinfo(struct net_device *ndev,
1085 struct ethtool_drvinfo *ed)
1086{
1087 strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver));
1088}
1089
1090static const struct ethtool_ops xemaclite_ethtool_ops = {
1091 .get_drvinfo = xemaclite_ethtools_get_drvinfo,
1092 .get_link = ethtool_op_get_link,
1093 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1094 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1095};
1096
1097static const struct net_device_ops xemaclite_netdev_ops;
1098
1099/**
1100 * xemaclite_of_probe - Probe method for the Emaclite device.
1101 * @ofdev: Pointer to OF device structure
1102 *
1103 * This function probes for the Emaclite device in the device tree.
1104 * It initializes the driver data structure and the hardware, sets the MAC
1105 * address and registers the network device.
1106 * It also registers a mii_bus for the Emaclite device, if MDIO is included
1107 * in the device.
1108 *
1109 * Return: 0, if the driver is bound to the Emaclite device, or
1110 * a negative error if there is failure.
1111 */
1112static int xemaclite_of_probe(struct platform_device *ofdev)
1113{
1114 struct resource *res;
1115 struct net_device *ndev = NULL;
1116 struct net_local *lp = NULL;
1117 struct device *dev = &ofdev->dev;
1118
1119 int rc = 0;
1120
1121 dev_info(dev, "Device Tree Probing\n");
1122
1123 /* Create an ethernet device instance */
1124 ndev = alloc_etherdev(sizeof(struct net_local));
1125 if (!ndev)
1126 return -ENOMEM;
1127
1128 dev_set_drvdata(dev, ndev);
1129 SET_NETDEV_DEV(ndev, &ofdev->dev);
1130
1131 lp = netdev_priv(ndev);
1132 lp->ndev = ndev;
1133
1134 /* Get IRQ for the device */
1135 res = platform_get_resource(ofdev, IORESOURCE_IRQ, 0);
1136 if (!res) {
1137 dev_err(dev, "no IRQ found\n");
1138 rc = -ENXIO;
1139 goto error;
1140 }
1141
1142 ndev->irq = res->start;
1143
1144 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1145 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res);
1146 if (IS_ERR(lp->base_addr)) {
1147 rc = PTR_ERR(lp->base_addr);
1148 goto error;
1149 }
1150
1151 ndev->mem_start = res->start;
1152 ndev->mem_end = res->end;
1153
1154 spin_lock_init(&lp->reset_lock);
1155 lp->next_tx_buf_to_use = 0x0;
1156 lp->next_rx_buf_to_use = 0x0;
1157 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong");
1158 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong");
1159
1160 rc = of_get_mac_address(ofdev->dev.of_node, ndev->dev_addr);
1161 if (rc) {
1162 dev_warn(dev, "No MAC address found, using random\n");
1163 eth_hw_addr_random(ndev);
1164 }
1165
1166 /* Clear the Tx CSR's in case this is a restart */
1167 xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET);
1168 xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET);
1169
1170 /* Set the MAC address in the EmacLite device */
1171 xemaclite_update_address(lp, ndev->dev_addr);
1172
1173 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0);
1174 xemaclite_mdio_setup(lp, &ofdev->dev);
1175
1176 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr);
1177
1178 ndev->netdev_ops = &xemaclite_netdev_ops;
1179 ndev->ethtool_ops = &xemaclite_ethtool_ops;
1180 ndev->flags &= ~IFF_MULTICAST;
1181 ndev->watchdog_timeo = TX_TIMEOUT;
1182
1183 /* Finally, register the device */
1184 rc = register_netdev(ndev);
1185 if (rc) {
1186 dev_err(dev,
1187 "Cannot register network device, aborting\n");
1188 goto error;
1189 }
1190
1191 dev_info(dev,
1192 "Xilinx EmacLite at 0x%08lX mapped to 0x%p, irq=%d\n",
1193 (unsigned long __force)ndev->mem_start, lp->base_addr, ndev->irq);
1194 return 0;
1195
1196error:
1197 free_netdev(ndev);
1198 return rc;
1199}
1200
1201/**
1202 * xemaclite_of_remove - Unbind the driver from the Emaclite device.
1203 * @of_dev: Pointer to OF device structure
1204 *
1205 * This function is called if a device is physically removed from the system or
1206 * if the driver module is being unloaded. It frees any resources allocated to
1207 * the device.
1208 *
1209 * Return: 0, always.
1210 */
1211static int xemaclite_of_remove(struct platform_device *of_dev)
1212{
1213 struct net_device *ndev = platform_get_drvdata(of_dev);
1214
1215 struct net_local *lp = netdev_priv(ndev);
1216
1217 /* Un-register the mii_bus, if configured */
1218 if (lp->mii_bus) {
1219 mdiobus_unregister(lp->mii_bus);
1220 mdiobus_free(lp->mii_bus);
1221 lp->mii_bus = NULL;
1222 }
1223
1224 unregister_netdev(ndev);
1225
1226 of_node_put(lp->phy_node);
1227 lp->phy_node = NULL;
1228
1229 free_netdev(ndev);
1230
1231 return 0;
1232}
1233
1234#ifdef CONFIG_NET_POLL_CONTROLLER
1235static void
1236xemaclite_poll_controller(struct net_device *ndev)
1237{
1238 disable_irq(ndev->irq);
1239 xemaclite_interrupt(ndev->irq, ndev);
1240 enable_irq(ndev->irq);
1241}
1242#endif
1243
1244/* Ioctl MII Interface */
1245static int xemaclite_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1246{
1247 if (!dev->phydev || !netif_running(dev))
1248 return -EINVAL;
1249
1250 switch (cmd) {
1251 case SIOCGMIIPHY:
1252 case SIOCGMIIREG:
1253 case SIOCSMIIREG:
1254 return phy_mii_ioctl(dev->phydev, rq, cmd);
1255 default:
1256 return -EOPNOTSUPP;
1257 }
1258}
1259
1260static const struct net_device_ops xemaclite_netdev_ops = {
1261 .ndo_open = xemaclite_open,
1262 .ndo_stop = xemaclite_close,
1263 .ndo_start_xmit = xemaclite_send,
1264 .ndo_set_mac_address = xemaclite_set_mac_address,
1265 .ndo_tx_timeout = xemaclite_tx_timeout,
1266 .ndo_do_ioctl = xemaclite_ioctl,
1267#ifdef CONFIG_NET_POLL_CONTROLLER
1268 .ndo_poll_controller = xemaclite_poll_controller,
1269#endif
1270};
1271
1272/* Match table for OF platform binding */
1273static const struct of_device_id xemaclite_of_match[] = {
1274 { .compatible = "xlnx,opb-ethernetlite-1.01.a", },
1275 { .compatible = "xlnx,opb-ethernetlite-1.01.b", },
1276 { .compatible = "xlnx,xps-ethernetlite-1.00.a", },
1277 { .compatible = "xlnx,xps-ethernetlite-2.00.a", },
1278 { .compatible = "xlnx,xps-ethernetlite-2.01.a", },
1279 { .compatible = "xlnx,xps-ethernetlite-3.00.a", },
1280 { /* end of list */ },
1281};
1282MODULE_DEVICE_TABLE(of, xemaclite_of_match);
1283
1284static struct platform_driver xemaclite_of_driver = {
1285 .driver = {
1286 .name = DRIVER_NAME,
1287 .of_match_table = xemaclite_of_match,
1288 },
1289 .probe = xemaclite_of_probe,
1290 .remove = xemaclite_of_remove,
1291};
1292
1293module_platform_driver(xemaclite_of_driver);
1294
1295MODULE_AUTHOR("Xilinx, Inc.");
1296MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver");
1297MODULE_LICENSE("GPL");