Loading...
1/*
2 * Driver for Xilinx TEMAC Ethernet device
3 *
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 *
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
10 *
11 * Notes:
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
21 *
22 * TODO:
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/etherdevice.h>
32#include <linux/mii.h>
33#include <linux/module.h>
34#include <linux/mutex.h>
35#include <linux/netdevice.h>
36#include <linux/of.h>
37#include <linux/of_device.h>
38#include <linux/of_irq.h>
39#include <linux/of_mdio.h>
40#include <linux/of_net.h>
41#include <linux/of_platform.h>
42#include <linux/of_address.h>
43#include <linux/skbuff.h>
44#include <linux/spinlock.h>
45#include <linux/tcp.h> /* needed for sizeof(tcphdr) */
46#include <linux/udp.h> /* needed for sizeof(udphdr) */
47#include <linux/phy.h>
48#include <linux/in.h>
49#include <linux/io.h>
50#include <linux/ip.h>
51#include <linux/slab.h>
52#include <linux/interrupt.h>
53#include <linux/dma-mapping.h>
54
55#include "ll_temac.h"
56
57#define TX_BD_NUM 64
58#define RX_BD_NUM 128
59
60/* ---------------------------------------------------------------------
61 * Low level register access functions
62 */
63
64u32 temac_ior(struct temac_local *lp, int offset)
65{
66 return in_be32(lp->regs + offset);
67}
68
69void temac_iow(struct temac_local *lp, int offset, u32 value)
70{
71 out_be32(lp->regs + offset, value);
72}
73
74int temac_indirect_busywait(struct temac_local *lp)
75{
76 unsigned long end = jiffies + 2;
77
78 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
79 if (time_before_eq(end, jiffies)) {
80 WARN_ON(1);
81 return -ETIMEDOUT;
82 }
83 msleep(1);
84 }
85 return 0;
86}
87
88/**
89 * temac_indirect_in32
90 *
91 * lp->indirect_mutex must be held when calling this function
92 */
93u32 temac_indirect_in32(struct temac_local *lp, int reg)
94{
95 u32 val;
96
97 if (temac_indirect_busywait(lp))
98 return -ETIMEDOUT;
99 temac_iow(lp, XTE_CTL0_OFFSET, reg);
100 if (temac_indirect_busywait(lp))
101 return -ETIMEDOUT;
102 val = temac_ior(lp, XTE_LSW0_OFFSET);
103
104 return val;
105}
106
107/**
108 * temac_indirect_out32
109 *
110 * lp->indirect_mutex must be held when calling this function
111 */
112void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
113{
114 if (temac_indirect_busywait(lp))
115 return;
116 temac_iow(lp, XTE_LSW0_OFFSET, value);
117 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
118 temac_indirect_busywait(lp);
119}
120
121/**
122 * temac_dma_in32 - Memory mapped DMA read, this function expects a
123 * register input that is based on DCR word addresses which
124 * are then converted to memory mapped byte addresses
125 */
126static u32 temac_dma_in32(struct temac_local *lp, int reg)
127{
128 return in_be32(lp->sdma_regs + (reg << 2));
129}
130
131/**
132 * temac_dma_out32 - Memory mapped DMA read, this function expects a
133 * register input that is based on DCR word addresses which
134 * are then converted to memory mapped byte addresses
135 */
136static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
137{
138 out_be32(lp->sdma_regs + (reg << 2), value);
139}
140
141/* DMA register access functions can be DCR based or memory mapped.
142 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
143 * memory mapped.
144 */
145#ifdef CONFIG_PPC_DCR
146
147/**
148 * temac_dma_dcr_in32 - DCR based DMA read
149 */
150static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
151{
152 return dcr_read(lp->sdma_dcrs, reg);
153}
154
155/**
156 * temac_dma_dcr_out32 - DCR based DMA write
157 */
158static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
159{
160 dcr_write(lp->sdma_dcrs, reg, value);
161}
162
163/**
164 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
165 * I/O functions
166 */
167static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
168 struct device_node *np)
169{
170 unsigned int dcrs;
171
172 /* setup the dcr address mapping if it's in the device tree */
173
174 dcrs = dcr_resource_start(np, 0);
175 if (dcrs != 0) {
176 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
177 lp->dma_in = temac_dma_dcr_in;
178 lp->dma_out = temac_dma_dcr_out;
179 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
180 return 0;
181 }
182 /* no DCR in the device tree, indicate a failure */
183 return -1;
184}
185
186#else
187
188/*
189 * temac_dcr_setup - This is a stub for when DCR is not supported,
190 * such as with MicroBlaze
191 */
192static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
193 struct device_node *np)
194{
195 return -1;
196}
197
198#endif
199
200/**
201 * temac_dma_bd_release - Release buffer descriptor rings
202 */
203static void temac_dma_bd_release(struct net_device *ndev)
204{
205 struct temac_local *lp = netdev_priv(ndev);
206 int i;
207
208 /* Reset Local Link (DMA) */
209 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
210
211 for (i = 0; i < RX_BD_NUM; i++) {
212 if (!lp->rx_skb[i])
213 break;
214 else {
215 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
216 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
217 dev_kfree_skb(lp->rx_skb[i]);
218 }
219 }
220 if (lp->rx_bd_v)
221 dma_free_coherent(ndev->dev.parent,
222 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
223 lp->rx_bd_v, lp->rx_bd_p);
224 if (lp->tx_bd_v)
225 dma_free_coherent(ndev->dev.parent,
226 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
227 lp->tx_bd_v, lp->tx_bd_p);
228 kfree(lp->rx_skb);
229}
230
231/**
232 * temac_dma_bd_init - Setup buffer descriptor rings
233 */
234static int temac_dma_bd_init(struct net_device *ndev)
235{
236 struct temac_local *lp = netdev_priv(ndev);
237 struct sk_buff *skb;
238 int i;
239
240 lp->rx_skb = kcalloc(RX_BD_NUM, sizeof(*lp->rx_skb), GFP_KERNEL);
241 if (!lp->rx_skb)
242 goto out;
243
244 /* allocate the tx and rx ring buffer descriptors. */
245 /* returns a virtual address and a physical address. */
246 lp->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
247 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
248 &lp->tx_bd_p, GFP_KERNEL);
249 if (!lp->tx_bd_v)
250 goto out;
251
252 lp->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
253 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
254 &lp->rx_bd_p, GFP_KERNEL);
255 if (!lp->rx_bd_v)
256 goto out;
257
258 for (i = 0; i < TX_BD_NUM; i++) {
259 lp->tx_bd_v[i].next = lp->tx_bd_p +
260 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
261 }
262
263 for (i = 0; i < RX_BD_NUM; i++) {
264 lp->rx_bd_v[i].next = lp->rx_bd_p +
265 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
266
267 skb = netdev_alloc_skb_ip_align(ndev,
268 XTE_MAX_JUMBO_FRAME_SIZE);
269 if (!skb)
270 goto out;
271
272 lp->rx_skb[i] = skb;
273 /* returns physical address of skb->data */
274 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
275 skb->data,
276 XTE_MAX_JUMBO_FRAME_SIZE,
277 DMA_FROM_DEVICE);
278 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
279 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
280 }
281
282 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
283 CHNL_CTRL_IRQ_EN |
284 CHNL_CTRL_IRQ_DLY_EN |
285 CHNL_CTRL_IRQ_COAL_EN);
286 /* 0x10220483 */
287 /* 0x00100483 */
288 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
289 CHNL_CTRL_IRQ_EN |
290 CHNL_CTRL_IRQ_DLY_EN |
291 CHNL_CTRL_IRQ_COAL_EN |
292 CHNL_CTRL_IRQ_IOE);
293 /* 0xff010283 */
294
295 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
296 lp->dma_out(lp, RX_TAILDESC_PTR,
297 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
298 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
299
300 /* Init descriptor indexes */
301 lp->tx_bd_ci = 0;
302 lp->tx_bd_next = 0;
303 lp->tx_bd_tail = 0;
304 lp->rx_bd_ci = 0;
305
306 return 0;
307
308out:
309 temac_dma_bd_release(ndev);
310 return -ENOMEM;
311}
312
313/* ---------------------------------------------------------------------
314 * net_device_ops
315 */
316
317static void temac_do_set_mac_address(struct net_device *ndev)
318{
319 struct temac_local *lp = netdev_priv(ndev);
320
321 /* set up unicast MAC address filter set its mac address */
322 mutex_lock(&lp->indirect_mutex);
323 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
324 (ndev->dev_addr[0]) |
325 (ndev->dev_addr[1] << 8) |
326 (ndev->dev_addr[2] << 16) |
327 (ndev->dev_addr[3] << 24));
328 /* There are reserved bits in EUAW1
329 * so don't affect them Set MAC bits [47:32] in EUAW1 */
330 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
331 (ndev->dev_addr[4] & 0x000000ff) |
332 (ndev->dev_addr[5] << 8));
333 mutex_unlock(&lp->indirect_mutex);
334}
335
336static int temac_init_mac_address(struct net_device *ndev, const void *address)
337{
338 memcpy(ndev->dev_addr, address, ETH_ALEN);
339 if (!is_valid_ether_addr(ndev->dev_addr))
340 eth_hw_addr_random(ndev);
341 temac_do_set_mac_address(ndev);
342 return 0;
343}
344
345static int temac_set_mac_address(struct net_device *ndev, void *p)
346{
347 struct sockaddr *addr = p;
348
349 if (!is_valid_ether_addr(addr->sa_data))
350 return -EADDRNOTAVAIL;
351 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
352 temac_do_set_mac_address(ndev);
353 return 0;
354}
355
356static void temac_set_multicast_list(struct net_device *ndev)
357{
358 struct temac_local *lp = netdev_priv(ndev);
359 u32 multi_addr_msw, multi_addr_lsw, val;
360 int i;
361
362 mutex_lock(&lp->indirect_mutex);
363 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
364 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
365 /*
366 * We must make the kernel realise we had to move
367 * into promisc mode or we start all out war on
368 * the cable. If it was a promisc request the
369 * flag is already set. If not we assert it.
370 */
371 ndev->flags |= IFF_PROMISC;
372 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
373 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
374 } else if (!netdev_mc_empty(ndev)) {
375 struct netdev_hw_addr *ha;
376
377 i = 0;
378 netdev_for_each_mc_addr(ha, ndev) {
379 if (i >= MULTICAST_CAM_TABLE_NUM)
380 break;
381 multi_addr_msw = ((ha->addr[3] << 24) |
382 (ha->addr[2] << 16) |
383 (ha->addr[1] << 8) |
384 (ha->addr[0]));
385 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
386 multi_addr_msw);
387 multi_addr_lsw = ((ha->addr[5] << 8) |
388 (ha->addr[4]) | (i << 16));
389 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
390 multi_addr_lsw);
391 i++;
392 }
393 } else {
394 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
395 temac_indirect_out32(lp, XTE_AFM_OFFSET,
396 val & ~XTE_AFM_EPPRM_MASK);
397 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
398 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
399 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
400 }
401 mutex_unlock(&lp->indirect_mutex);
402}
403
404static struct temac_option {
405 int flg;
406 u32 opt;
407 u32 reg;
408 u32 m_or;
409 u32 m_and;
410} temac_options[] = {
411 /* Turn on jumbo packet support for both Rx and Tx */
412 {
413 .opt = XTE_OPTION_JUMBO,
414 .reg = XTE_TXC_OFFSET,
415 .m_or = XTE_TXC_TXJMBO_MASK,
416 },
417 {
418 .opt = XTE_OPTION_JUMBO,
419 .reg = XTE_RXC1_OFFSET,
420 .m_or =XTE_RXC1_RXJMBO_MASK,
421 },
422 /* Turn on VLAN packet support for both Rx and Tx */
423 {
424 .opt = XTE_OPTION_VLAN,
425 .reg = XTE_TXC_OFFSET,
426 .m_or =XTE_TXC_TXVLAN_MASK,
427 },
428 {
429 .opt = XTE_OPTION_VLAN,
430 .reg = XTE_RXC1_OFFSET,
431 .m_or =XTE_RXC1_RXVLAN_MASK,
432 },
433 /* Turn on FCS stripping on receive packets */
434 {
435 .opt = XTE_OPTION_FCS_STRIP,
436 .reg = XTE_RXC1_OFFSET,
437 .m_or =XTE_RXC1_RXFCS_MASK,
438 },
439 /* Turn on FCS insertion on transmit packets */
440 {
441 .opt = XTE_OPTION_FCS_INSERT,
442 .reg = XTE_TXC_OFFSET,
443 .m_or =XTE_TXC_TXFCS_MASK,
444 },
445 /* Turn on length/type field checking on receive packets */
446 {
447 .opt = XTE_OPTION_LENTYPE_ERR,
448 .reg = XTE_RXC1_OFFSET,
449 .m_or =XTE_RXC1_RXLT_MASK,
450 },
451 /* Turn on flow control */
452 {
453 .opt = XTE_OPTION_FLOW_CONTROL,
454 .reg = XTE_FCC_OFFSET,
455 .m_or =XTE_FCC_RXFLO_MASK,
456 },
457 /* Turn on flow control */
458 {
459 .opt = XTE_OPTION_FLOW_CONTROL,
460 .reg = XTE_FCC_OFFSET,
461 .m_or =XTE_FCC_TXFLO_MASK,
462 },
463 /* Turn on promiscuous frame filtering (all frames are received ) */
464 {
465 .opt = XTE_OPTION_PROMISC,
466 .reg = XTE_AFM_OFFSET,
467 .m_or =XTE_AFM_EPPRM_MASK,
468 },
469 /* Enable transmitter if not already enabled */
470 {
471 .opt = XTE_OPTION_TXEN,
472 .reg = XTE_TXC_OFFSET,
473 .m_or =XTE_TXC_TXEN_MASK,
474 },
475 /* Enable receiver? */
476 {
477 .opt = XTE_OPTION_RXEN,
478 .reg = XTE_RXC1_OFFSET,
479 .m_or =XTE_RXC1_RXEN_MASK,
480 },
481 {}
482};
483
484/**
485 * temac_setoptions
486 */
487static u32 temac_setoptions(struct net_device *ndev, u32 options)
488{
489 struct temac_local *lp = netdev_priv(ndev);
490 struct temac_option *tp = &temac_options[0];
491 int reg;
492
493 mutex_lock(&lp->indirect_mutex);
494 while (tp->opt) {
495 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
496 if (options & tp->opt)
497 reg |= tp->m_or;
498 temac_indirect_out32(lp, tp->reg, reg);
499 tp++;
500 }
501 lp->options |= options;
502 mutex_unlock(&lp->indirect_mutex);
503
504 return 0;
505}
506
507/* Initialize temac */
508static void temac_device_reset(struct net_device *ndev)
509{
510 struct temac_local *lp = netdev_priv(ndev);
511 u32 timeout;
512 u32 val;
513
514 /* Perform a software reset */
515
516 /* 0x300 host enable bit ? */
517 /* reset PHY through control register ?:1 */
518
519 dev_dbg(&ndev->dev, "%s()\n", __func__);
520
521 mutex_lock(&lp->indirect_mutex);
522 /* Reset the receiver and wait for it to finish reset */
523 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
524 timeout = 1000;
525 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
526 udelay(1);
527 if (--timeout == 0) {
528 dev_err(&ndev->dev,
529 "temac_device_reset RX reset timeout!!\n");
530 break;
531 }
532 }
533
534 /* Reset the transmitter and wait for it to finish reset */
535 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
536 timeout = 1000;
537 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
538 udelay(1);
539 if (--timeout == 0) {
540 dev_err(&ndev->dev,
541 "temac_device_reset TX reset timeout!!\n");
542 break;
543 }
544 }
545
546 /* Disable the receiver */
547 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
548 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
549
550 /* Reset Local Link (DMA) */
551 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
552 timeout = 1000;
553 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
554 udelay(1);
555 if (--timeout == 0) {
556 dev_err(&ndev->dev,
557 "temac_device_reset DMA reset timeout!!\n");
558 break;
559 }
560 }
561 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
562
563 if (temac_dma_bd_init(ndev)) {
564 dev_err(&ndev->dev,
565 "temac_device_reset descriptor allocation failed\n");
566 }
567
568 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
569 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
570 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
571 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
572
573 mutex_unlock(&lp->indirect_mutex);
574
575 /* Sync default options with HW
576 * but leave receiver and transmitter disabled. */
577 temac_setoptions(ndev,
578 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
579
580 temac_do_set_mac_address(ndev);
581
582 /* Set address filter table */
583 temac_set_multicast_list(ndev);
584 if (temac_setoptions(ndev, lp->options))
585 dev_err(&ndev->dev, "Error setting TEMAC options\n");
586
587 /* Init Driver variable */
588 netif_trans_update(ndev); /* prevent tx timeout */
589}
590
591static void temac_adjust_link(struct net_device *ndev)
592{
593 struct temac_local *lp = netdev_priv(ndev);
594 struct phy_device *phy = ndev->phydev;
595 u32 mii_speed;
596 int link_state;
597
598 /* hash together the state values to decide if something has changed */
599 link_state = phy->speed | (phy->duplex << 1) | phy->link;
600
601 mutex_lock(&lp->indirect_mutex);
602 if (lp->last_link != link_state) {
603 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
604 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
605
606 switch (phy->speed) {
607 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
608 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
609 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
610 }
611
612 /* Write new speed setting out to TEMAC */
613 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
614 lp->last_link = link_state;
615 phy_print_status(phy);
616 }
617 mutex_unlock(&lp->indirect_mutex);
618}
619
620static void temac_start_xmit_done(struct net_device *ndev)
621{
622 struct temac_local *lp = netdev_priv(ndev);
623 struct cdmac_bd *cur_p;
624 unsigned int stat = 0;
625
626 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
627 stat = cur_p->app0;
628
629 while (stat & STS_CTRL_APP0_CMPLT) {
630 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
631 DMA_TO_DEVICE);
632 if (cur_p->app4)
633 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
634 cur_p->app0 = 0;
635 cur_p->app1 = 0;
636 cur_p->app2 = 0;
637 cur_p->app3 = 0;
638 cur_p->app4 = 0;
639
640 ndev->stats.tx_packets++;
641 ndev->stats.tx_bytes += cur_p->len;
642
643 lp->tx_bd_ci++;
644 if (lp->tx_bd_ci >= TX_BD_NUM)
645 lp->tx_bd_ci = 0;
646
647 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
648 stat = cur_p->app0;
649 }
650
651 netif_wake_queue(ndev);
652}
653
654static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
655{
656 struct cdmac_bd *cur_p;
657 int tail;
658
659 tail = lp->tx_bd_tail;
660 cur_p = &lp->tx_bd_v[tail];
661
662 do {
663 if (cur_p->app0)
664 return NETDEV_TX_BUSY;
665
666 tail++;
667 if (tail >= TX_BD_NUM)
668 tail = 0;
669
670 cur_p = &lp->tx_bd_v[tail];
671 num_frag--;
672 } while (num_frag >= 0);
673
674 return 0;
675}
676
677static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
678{
679 struct temac_local *lp = netdev_priv(ndev);
680 struct cdmac_bd *cur_p;
681 dma_addr_t start_p, tail_p;
682 int ii;
683 unsigned long num_frag;
684 skb_frag_t *frag;
685
686 num_frag = skb_shinfo(skb)->nr_frags;
687 frag = &skb_shinfo(skb)->frags[0];
688 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
689 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
690
691 if (temac_check_tx_bd_space(lp, num_frag)) {
692 if (!netif_queue_stopped(ndev))
693 netif_stop_queue(ndev);
694 return NETDEV_TX_BUSY;
695 }
696
697 cur_p->app0 = 0;
698 if (skb->ip_summed == CHECKSUM_PARTIAL) {
699 unsigned int csum_start_off = skb_checksum_start_offset(skb);
700 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
701
702 cur_p->app0 |= 1; /* TX Checksum Enabled */
703 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
704 cur_p->app2 = 0; /* initial checksum seed */
705 }
706
707 cur_p->app0 |= STS_CTRL_APP0_SOP;
708 cur_p->len = skb_headlen(skb);
709 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
710 skb_headlen(skb), DMA_TO_DEVICE);
711 cur_p->app4 = (unsigned long)skb;
712
713 for (ii = 0; ii < num_frag; ii++) {
714 lp->tx_bd_tail++;
715 if (lp->tx_bd_tail >= TX_BD_NUM)
716 lp->tx_bd_tail = 0;
717
718 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
719 cur_p->phys = dma_map_single(ndev->dev.parent,
720 skb_frag_address(frag),
721 skb_frag_size(frag), DMA_TO_DEVICE);
722 cur_p->len = skb_frag_size(frag);
723 cur_p->app0 = 0;
724 frag++;
725 }
726 cur_p->app0 |= STS_CTRL_APP0_EOP;
727
728 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
729 lp->tx_bd_tail++;
730 if (lp->tx_bd_tail >= TX_BD_NUM)
731 lp->tx_bd_tail = 0;
732
733 skb_tx_timestamp(skb);
734
735 /* Kick off the transfer */
736 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
737
738 return NETDEV_TX_OK;
739}
740
741
742static void ll_temac_recv(struct net_device *ndev)
743{
744 struct temac_local *lp = netdev_priv(ndev);
745 struct sk_buff *skb, *new_skb;
746 unsigned int bdstat;
747 struct cdmac_bd *cur_p;
748 dma_addr_t tail_p;
749 int length;
750 unsigned long flags;
751
752 spin_lock_irqsave(&lp->rx_lock, flags);
753
754 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
755 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
756
757 bdstat = cur_p->app0;
758 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
759
760 skb = lp->rx_skb[lp->rx_bd_ci];
761 length = cur_p->app4 & 0x3FFF;
762
763 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
764 DMA_FROM_DEVICE);
765
766 skb_put(skb, length);
767 skb->protocol = eth_type_trans(skb, ndev);
768 skb_checksum_none_assert(skb);
769
770 /* if we're doing rx csum offload, set it up */
771 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
772 (skb->protocol == htons(ETH_P_IP)) &&
773 (skb->len > 64)) {
774
775 skb->csum = cur_p->app3 & 0xFFFF;
776 skb->ip_summed = CHECKSUM_COMPLETE;
777 }
778
779 if (!skb_defer_rx_timestamp(skb))
780 netif_rx(skb);
781
782 ndev->stats.rx_packets++;
783 ndev->stats.rx_bytes += length;
784
785 new_skb = netdev_alloc_skb_ip_align(ndev,
786 XTE_MAX_JUMBO_FRAME_SIZE);
787 if (!new_skb) {
788 spin_unlock_irqrestore(&lp->rx_lock, flags);
789 return;
790 }
791
792 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
793 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
794 XTE_MAX_JUMBO_FRAME_SIZE,
795 DMA_FROM_DEVICE);
796 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
797 lp->rx_skb[lp->rx_bd_ci] = new_skb;
798
799 lp->rx_bd_ci++;
800 if (lp->rx_bd_ci >= RX_BD_NUM)
801 lp->rx_bd_ci = 0;
802
803 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
804 bdstat = cur_p->app0;
805 }
806 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
807
808 spin_unlock_irqrestore(&lp->rx_lock, flags);
809}
810
811static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
812{
813 struct net_device *ndev = _ndev;
814 struct temac_local *lp = netdev_priv(ndev);
815 unsigned int status;
816
817 status = lp->dma_in(lp, TX_IRQ_REG);
818 lp->dma_out(lp, TX_IRQ_REG, status);
819
820 if (status & (IRQ_COAL | IRQ_DLY))
821 temac_start_xmit_done(lp->ndev);
822 if (status & 0x080)
823 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
824
825 return IRQ_HANDLED;
826}
827
828static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
829{
830 struct net_device *ndev = _ndev;
831 struct temac_local *lp = netdev_priv(ndev);
832 unsigned int status;
833
834 /* Read and clear the status registers */
835 status = lp->dma_in(lp, RX_IRQ_REG);
836 lp->dma_out(lp, RX_IRQ_REG, status);
837
838 if (status & (IRQ_COAL | IRQ_DLY))
839 ll_temac_recv(lp->ndev);
840
841 return IRQ_HANDLED;
842}
843
844static int temac_open(struct net_device *ndev)
845{
846 struct temac_local *lp = netdev_priv(ndev);
847 struct phy_device *phydev = NULL;
848 int rc;
849
850 dev_dbg(&ndev->dev, "temac_open()\n");
851
852 if (lp->phy_node) {
853 phydev = of_phy_connect(lp->ndev, lp->phy_node,
854 temac_adjust_link, 0, 0);
855 if (!phydev) {
856 dev_err(lp->dev, "of_phy_connect() failed\n");
857 return -ENODEV;
858 }
859
860 phy_start(phydev);
861 }
862
863 temac_device_reset(ndev);
864
865 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
866 if (rc)
867 goto err_tx_irq;
868 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
869 if (rc)
870 goto err_rx_irq;
871
872 return 0;
873
874 err_rx_irq:
875 free_irq(lp->tx_irq, ndev);
876 err_tx_irq:
877 if (phydev)
878 phy_disconnect(phydev);
879 dev_err(lp->dev, "request_irq() failed\n");
880 return rc;
881}
882
883static int temac_stop(struct net_device *ndev)
884{
885 struct temac_local *lp = netdev_priv(ndev);
886 struct phy_device *phydev = ndev->phydev;
887
888 dev_dbg(&ndev->dev, "temac_close()\n");
889
890 free_irq(lp->tx_irq, ndev);
891 free_irq(lp->rx_irq, ndev);
892
893 if (phydev)
894 phy_disconnect(phydev);
895
896 temac_dma_bd_release(ndev);
897
898 return 0;
899}
900
901#ifdef CONFIG_NET_POLL_CONTROLLER
902static void
903temac_poll_controller(struct net_device *ndev)
904{
905 struct temac_local *lp = netdev_priv(ndev);
906
907 disable_irq(lp->tx_irq);
908 disable_irq(lp->rx_irq);
909
910 ll_temac_rx_irq(lp->tx_irq, ndev);
911 ll_temac_tx_irq(lp->rx_irq, ndev);
912
913 enable_irq(lp->tx_irq);
914 enable_irq(lp->rx_irq);
915}
916#endif
917
918static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
919{
920 if (!netif_running(ndev))
921 return -EINVAL;
922
923 if (!ndev->phydev)
924 return -EINVAL;
925
926 return phy_mii_ioctl(ndev->phydev, rq, cmd);
927}
928
929static const struct net_device_ops temac_netdev_ops = {
930 .ndo_open = temac_open,
931 .ndo_stop = temac_stop,
932 .ndo_start_xmit = temac_start_xmit,
933 .ndo_set_mac_address = temac_set_mac_address,
934 .ndo_validate_addr = eth_validate_addr,
935 .ndo_do_ioctl = temac_ioctl,
936#ifdef CONFIG_NET_POLL_CONTROLLER
937 .ndo_poll_controller = temac_poll_controller,
938#endif
939};
940
941/* ---------------------------------------------------------------------
942 * SYSFS device attributes
943 */
944static ssize_t temac_show_llink_regs(struct device *dev,
945 struct device_attribute *attr, char *buf)
946{
947 struct net_device *ndev = dev_get_drvdata(dev);
948 struct temac_local *lp = netdev_priv(ndev);
949 int i, len = 0;
950
951 for (i = 0; i < 0x11; i++)
952 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
953 (i % 8) == 7 ? "\n" : " ");
954 len += sprintf(buf + len, "\n");
955
956 return len;
957}
958
959static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
960
961static struct attribute *temac_device_attrs[] = {
962 &dev_attr_llink_regs.attr,
963 NULL,
964};
965
966static const struct attribute_group temac_attr_group = {
967 .attrs = temac_device_attrs,
968};
969
970/* ethtool support */
971static const struct ethtool_ops temac_ethtool_ops = {
972 .nway_reset = phy_ethtool_nway_reset,
973 .get_link = ethtool_op_get_link,
974 .get_ts_info = ethtool_op_get_ts_info,
975 .get_link_ksettings = phy_ethtool_get_link_ksettings,
976 .set_link_ksettings = phy_ethtool_set_link_ksettings,
977};
978
979static int temac_of_probe(struct platform_device *op)
980{
981 struct device_node *np;
982 struct temac_local *lp;
983 struct net_device *ndev;
984 const void *addr;
985 __be32 *p;
986 int rc = 0;
987
988 /* Init network device structure */
989 ndev = alloc_etherdev(sizeof(*lp));
990 if (!ndev)
991 return -ENOMEM;
992
993 platform_set_drvdata(op, ndev);
994 SET_NETDEV_DEV(ndev, &op->dev);
995 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
996 ndev->features = NETIF_F_SG;
997 ndev->netdev_ops = &temac_netdev_ops;
998 ndev->ethtool_ops = &temac_ethtool_ops;
999#if 0
1000 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1001 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1002 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1003 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1004 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1005 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1006 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
1007 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1008 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1009 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1010 ndev->features |= NETIF_F_LRO; /* large receive offload */
1011#endif
1012
1013 /* setup temac private info structure */
1014 lp = netdev_priv(ndev);
1015 lp->ndev = ndev;
1016 lp->dev = &op->dev;
1017 lp->options = XTE_OPTION_DEFAULTS;
1018 spin_lock_init(&lp->rx_lock);
1019 mutex_init(&lp->indirect_mutex);
1020
1021 /* map device registers */
1022 lp->regs = of_iomap(op->dev.of_node, 0);
1023 if (!lp->regs) {
1024 dev_err(&op->dev, "could not map temac regs.\n");
1025 rc = -ENOMEM;
1026 goto nodev;
1027 }
1028
1029 /* Setup checksum offload, but default to off if not specified */
1030 lp->temac_features = 0;
1031 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1032 if (p && be32_to_cpu(*p)) {
1033 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1034 /* Can checksum TCP/UDP over IPv4. */
1035 ndev->features |= NETIF_F_IP_CSUM;
1036 }
1037 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1038 if (p && be32_to_cpu(*p))
1039 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1040
1041 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1042 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
1043 if (!np) {
1044 dev_err(&op->dev, "could not find DMA node\n");
1045 rc = -ENODEV;
1046 goto err_iounmap;
1047 }
1048
1049 /* Setup the DMA register accesses, could be DCR or memory mapped */
1050 if (temac_dcr_setup(lp, op, np)) {
1051
1052 /* no DCR in the device tree, try non-DCR */
1053 lp->sdma_regs = of_iomap(np, 0);
1054 if (lp->sdma_regs) {
1055 lp->dma_in = temac_dma_in32;
1056 lp->dma_out = temac_dma_out32;
1057 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1058 } else {
1059 dev_err(&op->dev, "unable to map DMA registers\n");
1060 of_node_put(np);
1061 goto err_iounmap;
1062 }
1063 }
1064
1065 lp->rx_irq = irq_of_parse_and_map(np, 0);
1066 lp->tx_irq = irq_of_parse_and_map(np, 1);
1067
1068 of_node_put(np); /* Finished with the DMA node; drop the reference */
1069
1070 if (!lp->rx_irq || !lp->tx_irq) {
1071 dev_err(&op->dev, "could not determine irqs\n");
1072 rc = -ENOMEM;
1073 goto err_iounmap_2;
1074 }
1075
1076
1077 /* Retrieve the MAC address */
1078 addr = of_get_mac_address(op->dev.of_node);
1079 if (!addr) {
1080 dev_err(&op->dev, "could not find MAC address\n");
1081 rc = -ENODEV;
1082 goto err_iounmap_2;
1083 }
1084 temac_init_mac_address(ndev, addr);
1085
1086 rc = temac_mdio_setup(lp, op->dev.of_node);
1087 if (rc)
1088 dev_warn(&op->dev, "error registering MDIO bus\n");
1089
1090 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1091 if (lp->phy_node)
1092 dev_dbg(lp->dev, "using PHY node %pOF (%p)\n", np, np);
1093
1094 /* Add the device attributes */
1095 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1096 if (rc) {
1097 dev_err(lp->dev, "Error creating sysfs files\n");
1098 goto err_iounmap_2;
1099 }
1100
1101 rc = register_netdev(lp->ndev);
1102 if (rc) {
1103 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1104 goto err_register_ndev;
1105 }
1106
1107 return 0;
1108
1109 err_register_ndev:
1110 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1111 err_iounmap_2:
1112 if (lp->sdma_regs)
1113 iounmap(lp->sdma_regs);
1114 err_iounmap:
1115 iounmap(lp->regs);
1116 nodev:
1117 free_netdev(ndev);
1118 ndev = NULL;
1119 return rc;
1120}
1121
1122static int temac_of_remove(struct platform_device *op)
1123{
1124 struct net_device *ndev = platform_get_drvdata(op);
1125 struct temac_local *lp = netdev_priv(ndev);
1126
1127 temac_mdio_teardown(lp);
1128 unregister_netdev(ndev);
1129 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1130 of_node_put(lp->phy_node);
1131 lp->phy_node = NULL;
1132 iounmap(lp->regs);
1133 if (lp->sdma_regs)
1134 iounmap(lp->sdma_regs);
1135 free_netdev(ndev);
1136 return 0;
1137}
1138
1139static const struct of_device_id temac_of_match[] = {
1140 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1141 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1142 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1143 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1144 {},
1145};
1146MODULE_DEVICE_TABLE(of, temac_of_match);
1147
1148static struct platform_driver temac_of_driver = {
1149 .probe = temac_of_probe,
1150 .remove = temac_of_remove,
1151 .driver = {
1152 .name = "xilinx_temac",
1153 .of_match_table = temac_of_match,
1154 },
1155};
1156
1157module_platform_driver(temac_of_driver);
1158
1159MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1160MODULE_AUTHOR("Yoshio Kashiwagi");
1161MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Xilinx TEMAC Ethernet device
4 *
5 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 *
9 * This is a driver for the Xilinx ll_temac ipcore which is often used
10 * in the Virtex and Spartan series of chips.
11 *
12 * Notes:
13 * - The ll_temac hardware uses indirect access for many of the TEMAC
14 * registers, include the MDIO bus. However, indirect access to MDIO
15 * registers take considerably more clock cycles than to TEMAC registers.
16 * MDIO accesses are long, so threads doing them should probably sleep
17 * rather than busywait. However, since only one indirect access can be
18 * in progress at any given time, that means that *all* indirect accesses
19 * could end up sleeping (to wait for an MDIO access to complete).
20 * Fortunately none of the indirect accesses are on the 'hot' path for tx
21 * or rx, so this should be okay.
22 *
23 * TODO:
24 * - Factor out locallink DMA code into separate driver
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30#include <linux/delay.h>
31#include <linux/etherdevice.h>
32#include <linux/mii.h>
33#include <linux/module.h>
34#include <linux/mutex.h>
35#include <linux/netdevice.h>
36#include <linux/if_ether.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39#include <linux/of_irq.h>
40#include <linux/of_mdio.h>
41#include <linux/of_net.h>
42#include <linux/of_platform.h>
43#include <linux/of_address.h>
44#include <linux/skbuff.h>
45#include <linux/spinlock.h>
46#include <linux/tcp.h> /* needed for sizeof(tcphdr) */
47#include <linux/udp.h> /* needed for sizeof(udphdr) */
48#include <linux/phy.h>
49#include <linux/in.h>
50#include <linux/io.h>
51#include <linux/ip.h>
52#include <linux/slab.h>
53#include <linux/interrupt.h>
54#include <linux/workqueue.h>
55#include <linux/dma-mapping.h>
56#include <linux/processor.h>
57#include <linux/platform_data/xilinx-ll-temac.h>
58
59#include "ll_temac.h"
60
61/* Descriptors defines for Tx and Rx DMA */
62#define TX_BD_NUM_DEFAULT 64
63#define RX_BD_NUM_DEFAULT 1024
64#define TX_BD_NUM_MAX 4096
65#define RX_BD_NUM_MAX 4096
66
67/* ---------------------------------------------------------------------
68 * Low level register access functions
69 */
70
71static u32 _temac_ior_be(struct temac_local *lp, int offset)
72{
73 return ioread32be(lp->regs + offset);
74}
75
76static void _temac_iow_be(struct temac_local *lp, int offset, u32 value)
77{
78 return iowrite32be(value, lp->regs + offset);
79}
80
81static u32 _temac_ior_le(struct temac_local *lp, int offset)
82{
83 return ioread32(lp->regs + offset);
84}
85
86static void _temac_iow_le(struct temac_local *lp, int offset, u32 value)
87{
88 return iowrite32(value, lp->regs + offset);
89}
90
91static bool hard_acs_rdy(struct temac_local *lp)
92{
93 return temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK;
94}
95
96static bool hard_acs_rdy_or_timeout(struct temac_local *lp, ktime_t timeout)
97{
98 ktime_t cur = ktime_get();
99
100 return hard_acs_rdy(lp) || ktime_after(cur, timeout);
101}
102
103/* Poll for maximum 20 ms. This is similar to the 2 jiffies @ 100 Hz
104 * that was used before, and should cover MDIO bus speed down to 3200
105 * Hz.
106 */
107#define HARD_ACS_RDY_POLL_NS (20 * NSEC_PER_MSEC)
108
109/*
110 * temac_indirect_busywait - Wait for current indirect register access
111 * to complete.
112 */
113int temac_indirect_busywait(struct temac_local *lp)
114{
115 ktime_t timeout = ktime_add_ns(ktime_get(), HARD_ACS_RDY_POLL_NS);
116
117 spin_until_cond(hard_acs_rdy_or_timeout(lp, timeout));
118 if (WARN_ON(!hard_acs_rdy(lp)))
119 return -ETIMEDOUT;
120 else
121 return 0;
122}
123
124/*
125 * temac_indirect_in32 - Indirect register read access. This function
126 * must be called without lp->indirect_lock being held.
127 */
128u32 temac_indirect_in32(struct temac_local *lp, int reg)
129{
130 unsigned long flags;
131 int val;
132
133 spin_lock_irqsave(lp->indirect_lock, flags);
134 val = temac_indirect_in32_locked(lp, reg);
135 spin_unlock_irqrestore(lp->indirect_lock, flags);
136 return val;
137}
138
139/*
140 * temac_indirect_in32_locked - Indirect register read access. This
141 * function must be called with lp->indirect_lock being held. Use
142 * this together with spin_lock_irqsave/spin_lock_irqrestore to avoid
143 * repeated lock/unlock and to ensure uninterrupted access to indirect
144 * registers.
145 */
146u32 temac_indirect_in32_locked(struct temac_local *lp, int reg)
147{
148 /* This initial wait should normally not spin, as we always
149 * try to wait for indirect access to complete before
150 * releasing the indirect_lock.
151 */
152 if (WARN_ON(temac_indirect_busywait(lp)))
153 return -ETIMEDOUT;
154 /* Initiate read from indirect register */
155 temac_iow(lp, XTE_CTL0_OFFSET, reg);
156 /* Wait for indirect register access to complete. We really
157 * should not see timeouts, and could even end up causing
158 * problem for following indirect access, so let's make a bit
159 * of WARN noise.
160 */
161 if (WARN_ON(temac_indirect_busywait(lp)))
162 return -ETIMEDOUT;
163 /* Value is ready now */
164 return temac_ior(lp, XTE_LSW0_OFFSET);
165}
166
167/*
168 * temac_indirect_out32 - Indirect register write access. This function
169 * must be called without lp->indirect_lock being held.
170 */
171void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
172{
173 unsigned long flags;
174
175 spin_lock_irqsave(lp->indirect_lock, flags);
176 temac_indirect_out32_locked(lp, reg, value);
177 spin_unlock_irqrestore(lp->indirect_lock, flags);
178}
179
180/*
181 * temac_indirect_out32_locked - Indirect register write access. This
182 * function must be called with lp->indirect_lock being held. Use
183 * this together with spin_lock_irqsave/spin_lock_irqrestore to avoid
184 * repeated lock/unlock and to ensure uninterrupted access to indirect
185 * registers.
186 */
187void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value)
188{
189 /* As in temac_indirect_in32_locked(), we should normally not
190 * spin here. And if it happens, we actually end up silently
191 * ignoring the write request. Ouch.
192 */
193 if (WARN_ON(temac_indirect_busywait(lp)))
194 return;
195 /* Initiate write to indirect register */
196 temac_iow(lp, XTE_LSW0_OFFSET, value);
197 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
198 /* As in temac_indirect_in32_locked(), we should not see timeouts
199 * here. And if it happens, we continue before the write has
200 * completed. Not good.
201 */
202 WARN_ON(temac_indirect_busywait(lp));
203}
204
205/*
206 * temac_dma_in32_* - Memory mapped DMA read, these function expects a
207 * register input that is based on DCR word addresses which are then
208 * converted to memory mapped byte addresses. To be assigned to
209 * lp->dma_in32.
210 */
211static u32 temac_dma_in32_be(struct temac_local *lp, int reg)
212{
213 return ioread32be(lp->sdma_regs + (reg << 2));
214}
215
216static u32 temac_dma_in32_le(struct temac_local *lp, int reg)
217{
218 return ioread32(lp->sdma_regs + (reg << 2));
219}
220
221/*
222 * temac_dma_out32_* - Memory mapped DMA read, these function expects
223 * a register input that is based on DCR word addresses which are then
224 * converted to memory mapped byte addresses. To be assigned to
225 * lp->dma_out32.
226 */
227static void temac_dma_out32_be(struct temac_local *lp, int reg, u32 value)
228{
229 iowrite32be(value, lp->sdma_regs + (reg << 2));
230}
231
232static void temac_dma_out32_le(struct temac_local *lp, int reg, u32 value)
233{
234 iowrite32(value, lp->sdma_regs + (reg << 2));
235}
236
237/* DMA register access functions can be DCR based or memory mapped.
238 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
239 * memory mapped.
240 */
241#ifdef CONFIG_PPC_DCR
242
243/*
244 * temac_dma_dcr_in32 - DCR based DMA read
245 */
246static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
247{
248 return dcr_read(lp->sdma_dcrs, reg);
249}
250
251/*
252 * temac_dma_dcr_out32 - DCR based DMA write
253 */
254static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
255{
256 dcr_write(lp->sdma_dcrs, reg, value);
257}
258
259/*
260 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
261 * I/O functions
262 */
263static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
264 struct device_node *np)
265{
266 unsigned int dcrs;
267
268 /* setup the dcr address mapping if it's in the device tree */
269
270 dcrs = dcr_resource_start(np, 0);
271 if (dcrs != 0) {
272 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
273 lp->dma_in = temac_dma_dcr_in;
274 lp->dma_out = temac_dma_dcr_out;
275 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
276 return 0;
277 }
278 /* no DCR in the device tree, indicate a failure */
279 return -1;
280}
281
282#else
283
284/*
285 * temac_dcr_setup - This is a stub for when DCR is not supported,
286 * such as with MicroBlaze and x86
287 */
288static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
289 struct device_node *np)
290{
291 return -1;
292}
293
294#endif
295
296/*
297 * temac_dma_bd_release - Release buffer descriptor rings
298 */
299static void temac_dma_bd_release(struct net_device *ndev)
300{
301 struct temac_local *lp = netdev_priv(ndev);
302 int i;
303
304 /* Reset Local Link (DMA) */
305 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
306
307 for (i = 0; i < lp->rx_bd_num; i++) {
308 if (!lp->rx_skb[i])
309 break;
310 else {
311 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
312 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
313 dev_kfree_skb(lp->rx_skb[i]);
314 }
315 }
316 if (lp->rx_bd_v)
317 dma_free_coherent(ndev->dev.parent,
318 sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
319 lp->rx_bd_v, lp->rx_bd_p);
320 if (lp->tx_bd_v)
321 dma_free_coherent(ndev->dev.parent,
322 sizeof(*lp->tx_bd_v) * lp->tx_bd_num,
323 lp->tx_bd_v, lp->tx_bd_p);
324}
325
326/*
327 * temac_dma_bd_init - Setup buffer descriptor rings
328 */
329static int temac_dma_bd_init(struct net_device *ndev)
330{
331 struct temac_local *lp = netdev_priv(ndev);
332 struct sk_buff *skb;
333 dma_addr_t skb_dma_addr;
334 int i;
335
336 lp->rx_skb = devm_kcalloc(&ndev->dev, lp->rx_bd_num,
337 sizeof(*lp->rx_skb), GFP_KERNEL);
338 if (!lp->rx_skb)
339 goto out;
340
341 /* allocate the tx and rx ring buffer descriptors. */
342 /* returns a virtual address and a physical address. */
343 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
344 sizeof(*lp->tx_bd_v) * lp->tx_bd_num,
345 &lp->tx_bd_p, GFP_KERNEL);
346 if (!lp->tx_bd_v)
347 goto out;
348
349 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
350 sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
351 &lp->rx_bd_p, GFP_KERNEL);
352 if (!lp->rx_bd_v)
353 goto out;
354
355 for (i = 0; i < lp->tx_bd_num; i++) {
356 lp->tx_bd_v[i].next = cpu_to_be32(lp->tx_bd_p
357 + sizeof(*lp->tx_bd_v) * ((i + 1) % lp->tx_bd_num));
358 }
359
360 for (i = 0; i < lp->rx_bd_num; i++) {
361 lp->rx_bd_v[i].next = cpu_to_be32(lp->rx_bd_p
362 + sizeof(*lp->rx_bd_v) * ((i + 1) % lp->rx_bd_num));
363
364 skb = netdev_alloc_skb_ip_align(ndev,
365 XTE_MAX_JUMBO_FRAME_SIZE);
366 if (!skb)
367 goto out;
368
369 lp->rx_skb[i] = skb;
370 /* returns physical address of skb->data */
371 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
372 XTE_MAX_JUMBO_FRAME_SIZE,
373 DMA_FROM_DEVICE);
374 if (dma_mapping_error(ndev->dev.parent, skb_dma_addr))
375 goto out;
376 lp->rx_bd_v[i].phys = cpu_to_be32(skb_dma_addr);
377 lp->rx_bd_v[i].len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
378 lp->rx_bd_v[i].app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
379 }
380
381 /* Configure DMA channel (irq setup) */
382 lp->dma_out(lp, TX_CHNL_CTRL,
383 lp->coalesce_delay_tx << 24 | lp->coalesce_count_tx << 16 |
384 0x00000400 | // Use 1 Bit Wide Counters. Currently Not Used!
385 CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
386 CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
387 lp->dma_out(lp, RX_CHNL_CTRL,
388 lp->coalesce_delay_rx << 24 | lp->coalesce_count_rx << 16 |
389 CHNL_CTRL_IRQ_IOE |
390 CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
391 CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
392
393 /* Init descriptor indexes */
394 lp->tx_bd_ci = 0;
395 lp->tx_bd_tail = 0;
396 lp->rx_bd_ci = 0;
397 lp->rx_bd_tail = lp->rx_bd_num - 1;
398
399 /* Enable RX DMA transfers */
400 wmb();
401 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
402 lp->dma_out(lp, RX_TAILDESC_PTR,
403 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * lp->rx_bd_tail));
404
405 /* Prepare for TX DMA transfer */
406 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
407
408 return 0;
409
410out:
411 temac_dma_bd_release(ndev);
412 return -ENOMEM;
413}
414
415/* ---------------------------------------------------------------------
416 * net_device_ops
417 */
418
419static void temac_do_set_mac_address(struct net_device *ndev)
420{
421 struct temac_local *lp = netdev_priv(ndev);
422 unsigned long flags;
423
424 /* set up unicast MAC address filter set its mac address */
425 spin_lock_irqsave(lp->indirect_lock, flags);
426 temac_indirect_out32_locked(lp, XTE_UAW0_OFFSET,
427 (ndev->dev_addr[0]) |
428 (ndev->dev_addr[1] << 8) |
429 (ndev->dev_addr[2] << 16) |
430 (ndev->dev_addr[3] << 24));
431 /* There are reserved bits in EUAW1
432 * so don't affect them Set MAC bits [47:32] in EUAW1 */
433 temac_indirect_out32_locked(lp, XTE_UAW1_OFFSET,
434 (ndev->dev_addr[4] & 0x000000ff) |
435 (ndev->dev_addr[5] << 8));
436 spin_unlock_irqrestore(lp->indirect_lock, flags);
437}
438
439static int temac_init_mac_address(struct net_device *ndev, const void *address)
440{
441 memcpy(ndev->dev_addr, address, ETH_ALEN);
442 if (!is_valid_ether_addr(ndev->dev_addr))
443 eth_hw_addr_random(ndev);
444 temac_do_set_mac_address(ndev);
445 return 0;
446}
447
448static int temac_set_mac_address(struct net_device *ndev, void *p)
449{
450 struct sockaddr *addr = p;
451
452 if (!is_valid_ether_addr(addr->sa_data))
453 return -EADDRNOTAVAIL;
454 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
455 temac_do_set_mac_address(ndev);
456 return 0;
457}
458
459static void temac_set_multicast_list(struct net_device *ndev)
460{
461 struct temac_local *lp = netdev_priv(ndev);
462 u32 multi_addr_msw, multi_addr_lsw;
463 int i = 0;
464 unsigned long flags;
465 bool promisc_mode_disabled = false;
466
467 if (ndev->flags & (IFF_PROMISC | IFF_ALLMULTI) ||
468 (netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM)) {
469 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
470 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
471 return;
472 }
473
474 spin_lock_irqsave(lp->indirect_lock, flags);
475
476 if (!netdev_mc_empty(ndev)) {
477 struct netdev_hw_addr *ha;
478
479 netdev_for_each_mc_addr(ha, ndev) {
480 if (WARN_ON(i >= MULTICAST_CAM_TABLE_NUM))
481 break;
482 multi_addr_msw = ((ha->addr[3] << 24) |
483 (ha->addr[2] << 16) |
484 (ha->addr[1] << 8) |
485 (ha->addr[0]));
486 temac_indirect_out32_locked(lp, XTE_MAW0_OFFSET,
487 multi_addr_msw);
488 multi_addr_lsw = ((ha->addr[5] << 8) |
489 (ha->addr[4]) | (i << 16));
490 temac_indirect_out32_locked(lp, XTE_MAW1_OFFSET,
491 multi_addr_lsw);
492 i++;
493 }
494 }
495
496 /* Clear all or remaining/unused address table entries */
497 while (i < MULTICAST_CAM_TABLE_NUM) {
498 temac_indirect_out32_locked(lp, XTE_MAW0_OFFSET, 0);
499 temac_indirect_out32_locked(lp, XTE_MAW1_OFFSET, i << 16);
500 i++;
501 }
502
503 /* Enable address filter block if currently disabled */
504 if (temac_indirect_in32_locked(lp, XTE_AFM_OFFSET)
505 & XTE_AFM_EPPRM_MASK) {
506 temac_indirect_out32_locked(lp, XTE_AFM_OFFSET, 0);
507 promisc_mode_disabled = true;
508 }
509
510 spin_unlock_irqrestore(lp->indirect_lock, flags);
511
512 if (promisc_mode_disabled)
513 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
514}
515
516static struct temac_option {
517 int flg;
518 u32 opt;
519 u32 reg;
520 u32 m_or;
521 u32 m_and;
522} temac_options[] = {
523 /* Turn on jumbo packet support for both Rx and Tx */
524 {
525 .opt = XTE_OPTION_JUMBO,
526 .reg = XTE_TXC_OFFSET,
527 .m_or = XTE_TXC_TXJMBO_MASK,
528 },
529 {
530 .opt = XTE_OPTION_JUMBO,
531 .reg = XTE_RXC1_OFFSET,
532 .m_or =XTE_RXC1_RXJMBO_MASK,
533 },
534 /* Turn on VLAN packet support for both Rx and Tx */
535 {
536 .opt = XTE_OPTION_VLAN,
537 .reg = XTE_TXC_OFFSET,
538 .m_or =XTE_TXC_TXVLAN_MASK,
539 },
540 {
541 .opt = XTE_OPTION_VLAN,
542 .reg = XTE_RXC1_OFFSET,
543 .m_or =XTE_RXC1_RXVLAN_MASK,
544 },
545 /* Turn on FCS stripping on receive packets */
546 {
547 .opt = XTE_OPTION_FCS_STRIP,
548 .reg = XTE_RXC1_OFFSET,
549 .m_or =XTE_RXC1_RXFCS_MASK,
550 },
551 /* Turn on FCS insertion on transmit packets */
552 {
553 .opt = XTE_OPTION_FCS_INSERT,
554 .reg = XTE_TXC_OFFSET,
555 .m_or =XTE_TXC_TXFCS_MASK,
556 },
557 /* Turn on length/type field checking on receive packets */
558 {
559 .opt = XTE_OPTION_LENTYPE_ERR,
560 .reg = XTE_RXC1_OFFSET,
561 .m_or =XTE_RXC1_RXLT_MASK,
562 },
563 /* Turn on flow control */
564 {
565 .opt = XTE_OPTION_FLOW_CONTROL,
566 .reg = XTE_FCC_OFFSET,
567 .m_or =XTE_FCC_RXFLO_MASK,
568 },
569 /* Turn on flow control */
570 {
571 .opt = XTE_OPTION_FLOW_CONTROL,
572 .reg = XTE_FCC_OFFSET,
573 .m_or =XTE_FCC_TXFLO_MASK,
574 },
575 /* Turn on promiscuous frame filtering (all frames are received ) */
576 {
577 .opt = XTE_OPTION_PROMISC,
578 .reg = XTE_AFM_OFFSET,
579 .m_or =XTE_AFM_EPPRM_MASK,
580 },
581 /* Enable transmitter if not already enabled */
582 {
583 .opt = XTE_OPTION_TXEN,
584 .reg = XTE_TXC_OFFSET,
585 .m_or =XTE_TXC_TXEN_MASK,
586 },
587 /* Enable receiver? */
588 {
589 .opt = XTE_OPTION_RXEN,
590 .reg = XTE_RXC1_OFFSET,
591 .m_or =XTE_RXC1_RXEN_MASK,
592 },
593 {}
594};
595
596/*
597 * temac_setoptions
598 */
599static u32 temac_setoptions(struct net_device *ndev, u32 options)
600{
601 struct temac_local *lp = netdev_priv(ndev);
602 struct temac_option *tp = &temac_options[0];
603 int reg;
604 unsigned long flags;
605
606 spin_lock_irqsave(lp->indirect_lock, flags);
607 while (tp->opt) {
608 reg = temac_indirect_in32_locked(lp, tp->reg) & ~tp->m_or;
609 if (options & tp->opt) {
610 reg |= tp->m_or;
611 temac_indirect_out32_locked(lp, tp->reg, reg);
612 }
613 tp++;
614 }
615 spin_unlock_irqrestore(lp->indirect_lock, flags);
616 lp->options |= options;
617
618 return 0;
619}
620
621/* Initialize temac */
622static void temac_device_reset(struct net_device *ndev)
623{
624 struct temac_local *lp = netdev_priv(ndev);
625 u32 timeout;
626 u32 val;
627 unsigned long flags;
628
629 /* Perform a software reset */
630
631 /* 0x300 host enable bit ? */
632 /* reset PHY through control register ?:1 */
633
634 dev_dbg(&ndev->dev, "%s()\n", __func__);
635
636 /* Reset the receiver and wait for it to finish reset */
637 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
638 timeout = 1000;
639 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
640 udelay(1);
641 if (--timeout == 0) {
642 dev_err(&ndev->dev,
643 "temac_device_reset RX reset timeout!!\n");
644 break;
645 }
646 }
647
648 /* Reset the transmitter and wait for it to finish reset */
649 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
650 timeout = 1000;
651 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
652 udelay(1);
653 if (--timeout == 0) {
654 dev_err(&ndev->dev,
655 "temac_device_reset TX reset timeout!!\n");
656 break;
657 }
658 }
659
660 /* Disable the receiver */
661 spin_lock_irqsave(lp->indirect_lock, flags);
662 val = temac_indirect_in32_locked(lp, XTE_RXC1_OFFSET);
663 temac_indirect_out32_locked(lp, XTE_RXC1_OFFSET,
664 val & ~XTE_RXC1_RXEN_MASK);
665 spin_unlock_irqrestore(lp->indirect_lock, flags);
666
667 /* Reset Local Link (DMA) */
668 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
669 timeout = 1000;
670 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
671 udelay(1);
672 if (--timeout == 0) {
673 dev_err(&ndev->dev,
674 "temac_device_reset DMA reset timeout!!\n");
675 break;
676 }
677 }
678 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
679
680 if (temac_dma_bd_init(ndev)) {
681 dev_err(&ndev->dev,
682 "temac_device_reset descriptor allocation failed\n");
683 }
684
685 spin_lock_irqsave(lp->indirect_lock, flags);
686 temac_indirect_out32_locked(lp, XTE_RXC0_OFFSET, 0);
687 temac_indirect_out32_locked(lp, XTE_RXC1_OFFSET, 0);
688 temac_indirect_out32_locked(lp, XTE_TXC_OFFSET, 0);
689 temac_indirect_out32_locked(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
690 spin_unlock_irqrestore(lp->indirect_lock, flags);
691
692 /* Sync default options with HW
693 * but leave receiver and transmitter disabled. */
694 temac_setoptions(ndev,
695 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
696
697 temac_do_set_mac_address(ndev);
698
699 /* Set address filter table */
700 temac_set_multicast_list(ndev);
701 if (temac_setoptions(ndev, lp->options))
702 dev_err(&ndev->dev, "Error setting TEMAC options\n");
703
704 /* Init Driver variable */
705 netif_trans_update(ndev); /* prevent tx timeout */
706}
707
708static void temac_adjust_link(struct net_device *ndev)
709{
710 struct temac_local *lp = netdev_priv(ndev);
711 struct phy_device *phy = ndev->phydev;
712 u32 mii_speed;
713 int link_state;
714 unsigned long flags;
715
716 /* hash together the state values to decide if something has changed */
717 link_state = phy->speed | (phy->duplex << 1) | phy->link;
718
719 if (lp->last_link != link_state) {
720 spin_lock_irqsave(lp->indirect_lock, flags);
721 mii_speed = temac_indirect_in32_locked(lp, XTE_EMCFG_OFFSET);
722 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
723
724 switch (phy->speed) {
725 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
726 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
727 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
728 }
729
730 /* Write new speed setting out to TEMAC */
731 temac_indirect_out32_locked(lp, XTE_EMCFG_OFFSET, mii_speed);
732 spin_unlock_irqrestore(lp->indirect_lock, flags);
733
734 lp->last_link = link_state;
735 phy_print_status(phy);
736 }
737}
738
739#ifdef CONFIG_64BIT
740
741static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
742{
743 bd->app3 = (u32)(((u64)p) >> 32);
744 bd->app4 = (u32)((u64)p & 0xFFFFFFFF);
745}
746
747static void *ptr_from_txbd(struct cdmac_bd *bd)
748{
749 return (void *)(((u64)(bd->app3) << 32) | bd->app4);
750}
751
752#else
753
754static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
755{
756 bd->app4 = (u32)p;
757}
758
759static void *ptr_from_txbd(struct cdmac_bd *bd)
760{
761 return (void *)(bd->app4);
762}
763
764#endif
765
766static void temac_start_xmit_done(struct net_device *ndev)
767{
768 struct temac_local *lp = netdev_priv(ndev);
769 struct cdmac_bd *cur_p;
770 unsigned int stat = 0;
771 struct sk_buff *skb;
772
773 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
774 stat = be32_to_cpu(cur_p->app0);
775
776 while (stat & STS_CTRL_APP0_CMPLT) {
777 /* Make sure that the other fields are read after bd is
778 * released by dma
779 */
780 rmb();
781 dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys),
782 be32_to_cpu(cur_p->len), DMA_TO_DEVICE);
783 skb = (struct sk_buff *)ptr_from_txbd(cur_p);
784 if (skb)
785 dev_consume_skb_irq(skb);
786 cur_p->app1 = 0;
787 cur_p->app2 = 0;
788 cur_p->app3 = 0;
789 cur_p->app4 = 0;
790
791 ndev->stats.tx_packets++;
792 ndev->stats.tx_bytes += be32_to_cpu(cur_p->len);
793
794 /* app0 must be visible last, as it is used to flag
795 * availability of the bd
796 */
797 smp_mb();
798 cur_p->app0 = 0;
799
800 lp->tx_bd_ci++;
801 if (lp->tx_bd_ci >= lp->tx_bd_num)
802 lp->tx_bd_ci = 0;
803
804 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
805 stat = be32_to_cpu(cur_p->app0);
806 }
807
808 /* Matches barrier in temac_start_xmit */
809 smp_mb();
810
811 netif_wake_queue(ndev);
812}
813
814static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
815{
816 struct cdmac_bd *cur_p;
817 int tail;
818
819 tail = lp->tx_bd_tail;
820 cur_p = &lp->tx_bd_v[tail];
821
822 do {
823 if (cur_p->app0)
824 return NETDEV_TX_BUSY;
825
826 /* Make sure to read next bd app0 after this one */
827 rmb();
828
829 tail++;
830 if (tail >= lp->tx_bd_num)
831 tail = 0;
832
833 cur_p = &lp->tx_bd_v[tail];
834 num_frag--;
835 } while (num_frag >= 0);
836
837 return 0;
838}
839
840static netdev_tx_t
841temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
842{
843 struct temac_local *lp = netdev_priv(ndev);
844 struct cdmac_bd *cur_p;
845 dma_addr_t tail_p, skb_dma_addr;
846 int ii;
847 unsigned long num_frag;
848 skb_frag_t *frag;
849
850 num_frag = skb_shinfo(skb)->nr_frags;
851 frag = &skb_shinfo(skb)->frags[0];
852 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
853
854 if (temac_check_tx_bd_space(lp, num_frag + 1)) {
855 if (netif_queue_stopped(ndev))
856 return NETDEV_TX_BUSY;
857
858 netif_stop_queue(ndev);
859
860 /* Matches barrier in temac_start_xmit_done */
861 smp_mb();
862
863 /* Space might have just been freed - check again */
864 if (temac_check_tx_bd_space(lp, num_frag + 1))
865 return NETDEV_TX_BUSY;
866
867 netif_wake_queue(ndev);
868 }
869
870 cur_p->app0 = 0;
871 if (skb->ip_summed == CHECKSUM_PARTIAL) {
872 unsigned int csum_start_off = skb_checksum_start_offset(skb);
873 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
874
875 cur_p->app0 |= cpu_to_be32(0x000001); /* TX Checksum Enabled */
876 cur_p->app1 = cpu_to_be32((csum_start_off << 16)
877 | csum_index_off);
878 cur_p->app2 = 0; /* initial checksum seed */
879 }
880
881 cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_SOP);
882 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
883 skb_headlen(skb), DMA_TO_DEVICE);
884 cur_p->len = cpu_to_be32(skb_headlen(skb));
885 if (WARN_ON_ONCE(dma_mapping_error(ndev->dev.parent, skb_dma_addr))) {
886 dev_kfree_skb_any(skb);
887 ndev->stats.tx_dropped++;
888 return NETDEV_TX_OK;
889 }
890 cur_p->phys = cpu_to_be32(skb_dma_addr);
891
892 for (ii = 0; ii < num_frag; ii++) {
893 if (++lp->tx_bd_tail >= lp->tx_bd_num)
894 lp->tx_bd_tail = 0;
895
896 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
897 skb_dma_addr = dma_map_single(ndev->dev.parent,
898 skb_frag_address(frag),
899 skb_frag_size(frag),
900 DMA_TO_DEVICE);
901 if (dma_mapping_error(ndev->dev.parent, skb_dma_addr)) {
902 if (--lp->tx_bd_tail < 0)
903 lp->tx_bd_tail = lp->tx_bd_num - 1;
904 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
905 while (--ii >= 0) {
906 --frag;
907 dma_unmap_single(ndev->dev.parent,
908 be32_to_cpu(cur_p->phys),
909 skb_frag_size(frag),
910 DMA_TO_DEVICE);
911 if (--lp->tx_bd_tail < 0)
912 lp->tx_bd_tail = lp->tx_bd_num - 1;
913 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
914 }
915 dma_unmap_single(ndev->dev.parent,
916 be32_to_cpu(cur_p->phys),
917 skb_headlen(skb), DMA_TO_DEVICE);
918 dev_kfree_skb_any(skb);
919 ndev->stats.tx_dropped++;
920 return NETDEV_TX_OK;
921 }
922 cur_p->phys = cpu_to_be32(skb_dma_addr);
923 cur_p->len = cpu_to_be32(skb_frag_size(frag));
924 cur_p->app0 = 0;
925 frag++;
926 }
927 cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_EOP);
928
929 /* Mark last fragment with skb address, so it can be consumed
930 * in temac_start_xmit_done()
931 */
932 ptr_to_txbd((void *)skb, cur_p);
933
934 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
935 lp->tx_bd_tail++;
936 if (lp->tx_bd_tail >= lp->tx_bd_num)
937 lp->tx_bd_tail = 0;
938
939 skb_tx_timestamp(skb);
940
941 /* Kick off the transfer */
942 wmb();
943 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
944
945 if (temac_check_tx_bd_space(lp, MAX_SKB_FRAGS + 1))
946 netif_stop_queue(ndev);
947
948 return NETDEV_TX_OK;
949}
950
951static int ll_temac_recv_buffers_available(struct temac_local *lp)
952{
953 int available;
954
955 if (!lp->rx_skb[lp->rx_bd_ci])
956 return 0;
957 available = 1 + lp->rx_bd_tail - lp->rx_bd_ci;
958 if (available <= 0)
959 available += lp->rx_bd_num;
960 return available;
961}
962
963static void ll_temac_recv(struct net_device *ndev)
964{
965 struct temac_local *lp = netdev_priv(ndev);
966 unsigned long flags;
967 int rx_bd;
968 bool update_tail = false;
969
970 spin_lock_irqsave(&lp->rx_lock, flags);
971
972 /* Process all received buffers, passing them on network
973 * stack. After this, the buffer descriptors will be in an
974 * un-allocated stage, where no skb is allocated for it, and
975 * they are therefore not available for TEMAC/DMA.
976 */
977 do {
978 struct cdmac_bd *bd = &lp->rx_bd_v[lp->rx_bd_ci];
979 struct sk_buff *skb = lp->rx_skb[lp->rx_bd_ci];
980 unsigned int bdstat = be32_to_cpu(bd->app0);
981 int length;
982
983 /* While this should not normally happen, we can end
984 * here when GFP_ATOMIC allocations fail, and we
985 * therefore have un-allocated buffers.
986 */
987 if (!skb)
988 break;
989
990 /* Loop over all completed buffer descriptors */
991 if (!(bdstat & STS_CTRL_APP0_CMPLT))
992 break;
993
994 dma_unmap_single(ndev->dev.parent, be32_to_cpu(bd->phys),
995 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
996 /* The buffer is not valid for DMA anymore */
997 bd->phys = 0;
998 bd->len = 0;
999
1000 length = be32_to_cpu(bd->app4) & 0x3FFF;
1001 skb_put(skb, length);
1002 skb->protocol = eth_type_trans(skb, ndev);
1003 skb_checksum_none_assert(skb);
1004
1005 /* if we're doing rx csum offload, set it up */
1006 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
1007 (skb->protocol == htons(ETH_P_IP)) &&
1008 (skb->len > 64)) {
1009
1010 /* Convert from device endianness (be32) to cpu
1011 * endiannes, and if necessary swap the bytes
1012 * (back) for proper IP checksum byte order
1013 * (be16).
1014 */
1015 skb->csum = htons(be32_to_cpu(bd->app3) & 0xFFFF);
1016 skb->ip_summed = CHECKSUM_COMPLETE;
1017 }
1018
1019 if (!skb_defer_rx_timestamp(skb))
1020 netif_rx(skb);
1021 /* The skb buffer is now owned by network stack above */
1022 lp->rx_skb[lp->rx_bd_ci] = NULL;
1023
1024 ndev->stats.rx_packets++;
1025 ndev->stats.rx_bytes += length;
1026
1027 rx_bd = lp->rx_bd_ci;
1028 if (++lp->rx_bd_ci >= lp->rx_bd_num)
1029 lp->rx_bd_ci = 0;
1030 } while (rx_bd != lp->rx_bd_tail);
1031
1032 /* DMA operations will halt when the last buffer descriptor is
1033 * processed (ie. the one pointed to by RX_TAILDESC_PTR).
1034 * When that happens, no more interrupt events will be
1035 * generated. No IRQ_COAL or IRQ_DLY, and not even an
1036 * IRQ_ERR. To avoid stalling, we schedule a delayed work
1037 * when there is a potential risk of that happening. The work
1038 * will call this function, and thus re-schedule itself until
1039 * enough buffers are available again.
1040 */
1041 if (ll_temac_recv_buffers_available(lp) < lp->coalesce_count_rx)
1042 schedule_delayed_work(&lp->restart_work, HZ / 1000);
1043
1044 /* Allocate new buffers for those buffer descriptors that were
1045 * passed to network stack. Note that GFP_ATOMIC allocations
1046 * can fail (e.g. when a larger burst of GFP_ATOMIC
1047 * allocations occurs), so while we try to allocate all
1048 * buffers in the same interrupt where they were processed, we
1049 * continue with what we could get in case of allocation
1050 * failure. Allocation of remaining buffers will be retried
1051 * in following calls.
1052 */
1053 while (1) {
1054 struct sk_buff *skb;
1055 struct cdmac_bd *bd;
1056 dma_addr_t skb_dma_addr;
1057
1058 rx_bd = lp->rx_bd_tail + 1;
1059 if (rx_bd >= lp->rx_bd_num)
1060 rx_bd = 0;
1061 bd = &lp->rx_bd_v[rx_bd];
1062
1063 if (bd->phys)
1064 break; /* All skb's allocated */
1065
1066 skb = netdev_alloc_skb_ip_align(ndev, XTE_MAX_JUMBO_FRAME_SIZE);
1067 if (!skb) {
1068 dev_warn(&ndev->dev, "skb alloc failed\n");
1069 break;
1070 }
1071
1072 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
1073 XTE_MAX_JUMBO_FRAME_SIZE,
1074 DMA_FROM_DEVICE);
1075 if (WARN_ON_ONCE(dma_mapping_error(ndev->dev.parent,
1076 skb_dma_addr))) {
1077 dev_kfree_skb_any(skb);
1078 break;
1079 }
1080
1081 bd->phys = cpu_to_be32(skb_dma_addr);
1082 bd->len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
1083 bd->app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
1084 lp->rx_skb[rx_bd] = skb;
1085
1086 lp->rx_bd_tail = rx_bd;
1087 update_tail = true;
1088 }
1089
1090 /* Move tail pointer when buffers have been allocated */
1091 if (update_tail) {
1092 lp->dma_out(lp, RX_TAILDESC_PTR,
1093 lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_tail);
1094 }
1095
1096 spin_unlock_irqrestore(&lp->rx_lock, flags);
1097}
1098
1099/* Function scheduled to ensure a restart in case of DMA halt
1100 * condition caused by running out of buffer descriptors.
1101 */
1102static void ll_temac_restart_work_func(struct work_struct *work)
1103{
1104 struct temac_local *lp = container_of(work, struct temac_local,
1105 restart_work.work);
1106 struct net_device *ndev = lp->ndev;
1107
1108 ll_temac_recv(ndev);
1109}
1110
1111static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
1112{
1113 struct net_device *ndev = _ndev;
1114 struct temac_local *lp = netdev_priv(ndev);
1115 unsigned int status;
1116
1117 status = lp->dma_in(lp, TX_IRQ_REG);
1118 lp->dma_out(lp, TX_IRQ_REG, status);
1119
1120 if (status & (IRQ_COAL | IRQ_DLY))
1121 temac_start_xmit_done(lp->ndev);
1122 if (status & (IRQ_ERR | IRQ_DMAERR))
1123 dev_err_ratelimited(&ndev->dev,
1124 "TX error 0x%x TX_CHNL_STS=0x%08x\n",
1125 status, lp->dma_in(lp, TX_CHNL_STS));
1126
1127 return IRQ_HANDLED;
1128}
1129
1130static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
1131{
1132 struct net_device *ndev = _ndev;
1133 struct temac_local *lp = netdev_priv(ndev);
1134 unsigned int status;
1135
1136 /* Read and clear the status registers */
1137 status = lp->dma_in(lp, RX_IRQ_REG);
1138 lp->dma_out(lp, RX_IRQ_REG, status);
1139
1140 if (status & (IRQ_COAL | IRQ_DLY))
1141 ll_temac_recv(lp->ndev);
1142 if (status & (IRQ_ERR | IRQ_DMAERR))
1143 dev_err_ratelimited(&ndev->dev,
1144 "RX error 0x%x RX_CHNL_STS=0x%08x\n",
1145 status, lp->dma_in(lp, RX_CHNL_STS));
1146
1147 return IRQ_HANDLED;
1148}
1149
1150static int temac_open(struct net_device *ndev)
1151{
1152 struct temac_local *lp = netdev_priv(ndev);
1153 struct phy_device *phydev = NULL;
1154 int rc;
1155
1156 dev_dbg(&ndev->dev, "temac_open()\n");
1157
1158 if (lp->phy_node) {
1159 phydev = of_phy_connect(lp->ndev, lp->phy_node,
1160 temac_adjust_link, 0, 0);
1161 if (!phydev) {
1162 dev_err(lp->dev, "of_phy_connect() failed\n");
1163 return -ENODEV;
1164 }
1165 phy_start(phydev);
1166 } else if (strlen(lp->phy_name) > 0) {
1167 phydev = phy_connect(lp->ndev, lp->phy_name, temac_adjust_link,
1168 lp->phy_interface);
1169 if (IS_ERR(phydev)) {
1170 dev_err(lp->dev, "phy_connect() failed\n");
1171 return PTR_ERR(phydev);
1172 }
1173 phy_start(phydev);
1174 }
1175
1176 temac_device_reset(ndev);
1177
1178 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
1179 if (rc)
1180 goto err_tx_irq;
1181 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
1182 if (rc)
1183 goto err_rx_irq;
1184
1185 return 0;
1186
1187 err_rx_irq:
1188 free_irq(lp->tx_irq, ndev);
1189 err_tx_irq:
1190 if (phydev)
1191 phy_disconnect(phydev);
1192 dev_err(lp->dev, "request_irq() failed\n");
1193 return rc;
1194}
1195
1196static int temac_stop(struct net_device *ndev)
1197{
1198 struct temac_local *lp = netdev_priv(ndev);
1199 struct phy_device *phydev = ndev->phydev;
1200
1201 dev_dbg(&ndev->dev, "temac_close()\n");
1202
1203 cancel_delayed_work_sync(&lp->restart_work);
1204
1205 free_irq(lp->tx_irq, ndev);
1206 free_irq(lp->rx_irq, ndev);
1207
1208 if (phydev)
1209 phy_disconnect(phydev);
1210
1211 temac_dma_bd_release(ndev);
1212
1213 return 0;
1214}
1215
1216#ifdef CONFIG_NET_POLL_CONTROLLER
1217static void
1218temac_poll_controller(struct net_device *ndev)
1219{
1220 struct temac_local *lp = netdev_priv(ndev);
1221
1222 disable_irq(lp->tx_irq);
1223 disable_irq(lp->rx_irq);
1224
1225 ll_temac_rx_irq(lp->tx_irq, ndev);
1226 ll_temac_tx_irq(lp->rx_irq, ndev);
1227
1228 enable_irq(lp->tx_irq);
1229 enable_irq(lp->rx_irq);
1230}
1231#endif
1232
1233static const struct net_device_ops temac_netdev_ops = {
1234 .ndo_open = temac_open,
1235 .ndo_stop = temac_stop,
1236 .ndo_start_xmit = temac_start_xmit,
1237 .ndo_set_rx_mode = temac_set_multicast_list,
1238 .ndo_set_mac_address = temac_set_mac_address,
1239 .ndo_validate_addr = eth_validate_addr,
1240 .ndo_do_ioctl = phy_do_ioctl_running,
1241#ifdef CONFIG_NET_POLL_CONTROLLER
1242 .ndo_poll_controller = temac_poll_controller,
1243#endif
1244};
1245
1246/* ---------------------------------------------------------------------
1247 * SYSFS device attributes
1248 */
1249static ssize_t temac_show_llink_regs(struct device *dev,
1250 struct device_attribute *attr, char *buf)
1251{
1252 struct net_device *ndev = dev_get_drvdata(dev);
1253 struct temac_local *lp = netdev_priv(ndev);
1254 int i, len = 0;
1255
1256 for (i = 0; i < 0x11; i++)
1257 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
1258 (i % 8) == 7 ? "\n" : " ");
1259 len += sprintf(buf + len, "\n");
1260
1261 return len;
1262}
1263
1264static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
1265
1266static struct attribute *temac_device_attrs[] = {
1267 &dev_attr_llink_regs.attr,
1268 NULL,
1269};
1270
1271static const struct attribute_group temac_attr_group = {
1272 .attrs = temac_device_attrs,
1273};
1274
1275/* ---------------------------------------------------------------------
1276 * ethtool support
1277 */
1278
1279static void ll_temac_ethtools_get_ringparam(struct net_device *ndev,
1280 struct ethtool_ringparam *ering)
1281{
1282 struct temac_local *lp = netdev_priv(ndev);
1283
1284 ering->rx_max_pending = RX_BD_NUM_MAX;
1285 ering->rx_mini_max_pending = 0;
1286 ering->rx_jumbo_max_pending = 0;
1287 ering->tx_max_pending = TX_BD_NUM_MAX;
1288 ering->rx_pending = lp->rx_bd_num;
1289 ering->rx_mini_pending = 0;
1290 ering->rx_jumbo_pending = 0;
1291 ering->tx_pending = lp->tx_bd_num;
1292}
1293
1294static int ll_temac_ethtools_set_ringparam(struct net_device *ndev,
1295 struct ethtool_ringparam *ering)
1296{
1297 struct temac_local *lp = netdev_priv(ndev);
1298
1299 if (ering->rx_pending > RX_BD_NUM_MAX ||
1300 ering->rx_mini_pending ||
1301 ering->rx_jumbo_pending ||
1302 ering->rx_pending > TX_BD_NUM_MAX)
1303 return -EINVAL;
1304
1305 if (netif_running(ndev))
1306 return -EBUSY;
1307
1308 lp->rx_bd_num = ering->rx_pending;
1309 lp->tx_bd_num = ering->tx_pending;
1310 return 0;
1311}
1312
1313static int ll_temac_ethtools_get_coalesce(struct net_device *ndev,
1314 struct ethtool_coalesce *ec)
1315{
1316 struct temac_local *lp = netdev_priv(ndev);
1317
1318 ec->rx_max_coalesced_frames = lp->coalesce_count_rx;
1319 ec->tx_max_coalesced_frames = lp->coalesce_count_tx;
1320 ec->rx_coalesce_usecs = (lp->coalesce_delay_rx * 512) / 100;
1321 ec->tx_coalesce_usecs = (lp->coalesce_delay_tx * 512) / 100;
1322 return 0;
1323}
1324
1325static int ll_temac_ethtools_set_coalesce(struct net_device *ndev,
1326 struct ethtool_coalesce *ec)
1327{
1328 struct temac_local *lp = netdev_priv(ndev);
1329
1330 if (netif_running(ndev)) {
1331 netdev_err(ndev,
1332 "Please stop netif before applying configuration\n");
1333 return -EFAULT;
1334 }
1335
1336 if (ec->rx_max_coalesced_frames)
1337 lp->coalesce_count_rx = ec->rx_max_coalesced_frames;
1338 if (ec->tx_max_coalesced_frames)
1339 lp->coalesce_count_tx = ec->tx_max_coalesced_frames;
1340 /* With typical LocalLink clock speed of 200 MHz and
1341 * C_PRESCALAR=1023, each delay count corresponds to 5.12 us.
1342 */
1343 if (ec->rx_coalesce_usecs)
1344 lp->coalesce_delay_rx =
1345 min(255U, (ec->rx_coalesce_usecs * 100) / 512);
1346 if (ec->tx_coalesce_usecs)
1347 lp->coalesce_delay_tx =
1348 min(255U, (ec->tx_coalesce_usecs * 100) / 512);
1349
1350 return 0;
1351}
1352
1353static const struct ethtool_ops temac_ethtool_ops = {
1354 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1355 ETHTOOL_COALESCE_MAX_FRAMES,
1356 .nway_reset = phy_ethtool_nway_reset,
1357 .get_link = ethtool_op_get_link,
1358 .get_ts_info = ethtool_op_get_ts_info,
1359 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1360 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1361 .get_ringparam = ll_temac_ethtools_get_ringparam,
1362 .set_ringparam = ll_temac_ethtools_set_ringparam,
1363 .get_coalesce = ll_temac_ethtools_get_coalesce,
1364 .set_coalesce = ll_temac_ethtools_set_coalesce,
1365};
1366
1367static int temac_probe(struct platform_device *pdev)
1368{
1369 struct ll_temac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1370 struct device_node *temac_np = dev_of_node(&pdev->dev), *dma_np;
1371 struct temac_local *lp;
1372 struct net_device *ndev;
1373 u8 addr[ETH_ALEN];
1374 __be32 *p;
1375 bool little_endian;
1376 int rc = 0;
1377
1378 /* Init network device structure */
1379 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*lp));
1380 if (!ndev)
1381 return -ENOMEM;
1382
1383 platform_set_drvdata(pdev, ndev);
1384 SET_NETDEV_DEV(ndev, &pdev->dev);
1385 ndev->features = NETIF_F_SG;
1386 ndev->netdev_ops = &temac_netdev_ops;
1387 ndev->ethtool_ops = &temac_ethtool_ops;
1388#if 0
1389 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1390 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1391 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1392 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1393 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1394 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1395 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
1396 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1397 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1398 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1399 ndev->features |= NETIF_F_LRO; /* large receive offload */
1400#endif
1401
1402 /* setup temac private info structure */
1403 lp = netdev_priv(ndev);
1404 lp->ndev = ndev;
1405 lp->dev = &pdev->dev;
1406 lp->options = XTE_OPTION_DEFAULTS;
1407 lp->rx_bd_num = RX_BD_NUM_DEFAULT;
1408 lp->tx_bd_num = TX_BD_NUM_DEFAULT;
1409 spin_lock_init(&lp->rx_lock);
1410 INIT_DELAYED_WORK(&lp->restart_work, ll_temac_restart_work_func);
1411
1412 /* Setup mutex for synchronization of indirect register access */
1413 if (pdata) {
1414 if (!pdata->indirect_lock) {
1415 dev_err(&pdev->dev,
1416 "indirect_lock missing in platform_data\n");
1417 return -EINVAL;
1418 }
1419 lp->indirect_lock = pdata->indirect_lock;
1420 } else {
1421 lp->indirect_lock = devm_kmalloc(&pdev->dev,
1422 sizeof(*lp->indirect_lock),
1423 GFP_KERNEL);
1424 spin_lock_init(lp->indirect_lock);
1425 }
1426
1427 /* map device registers */
1428 lp->regs = devm_platform_ioremap_resource_byname(pdev, 0);
1429 if (IS_ERR(lp->regs)) {
1430 dev_err(&pdev->dev, "could not map TEMAC registers\n");
1431 return -ENOMEM;
1432 }
1433
1434 /* Select register access functions with the specified
1435 * endianness mode. Default for OF devices is big-endian.
1436 */
1437 little_endian = false;
1438 if (temac_np) {
1439 if (of_get_property(temac_np, "little-endian", NULL))
1440 little_endian = true;
1441 } else if (pdata) {
1442 little_endian = pdata->reg_little_endian;
1443 }
1444 if (little_endian) {
1445 lp->temac_ior = _temac_ior_le;
1446 lp->temac_iow = _temac_iow_le;
1447 } else {
1448 lp->temac_ior = _temac_ior_be;
1449 lp->temac_iow = _temac_iow_be;
1450 }
1451
1452 /* Setup checksum offload, but default to off if not specified */
1453 lp->temac_features = 0;
1454 if (temac_np) {
1455 p = (__be32 *)of_get_property(temac_np, "xlnx,txcsum", NULL);
1456 if (p && be32_to_cpu(*p))
1457 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1458 p = (__be32 *)of_get_property(temac_np, "xlnx,rxcsum", NULL);
1459 if (p && be32_to_cpu(*p))
1460 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1461 } else if (pdata) {
1462 if (pdata->txcsum)
1463 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1464 if (pdata->rxcsum)
1465 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1466 }
1467 if (lp->temac_features & TEMAC_FEATURE_TX_CSUM)
1468 /* Can checksum TCP/UDP over IPv4. */
1469 ndev->features |= NETIF_F_IP_CSUM;
1470
1471 /* Defaults for IRQ delay/coalescing setup. These are
1472 * configuration values, so does not belong in device-tree.
1473 */
1474 lp->coalesce_delay_tx = 0x10;
1475 lp->coalesce_count_tx = 0x22;
1476 lp->coalesce_delay_rx = 0xff;
1477 lp->coalesce_count_rx = 0x07;
1478
1479 /* Setup LocalLink DMA */
1480 if (temac_np) {
1481 /* Find the DMA node, map the DMA registers, and
1482 * decode the DMA IRQs.
1483 */
1484 dma_np = of_parse_phandle(temac_np, "llink-connected", 0);
1485 if (!dma_np) {
1486 dev_err(&pdev->dev, "could not find DMA node\n");
1487 return -ENODEV;
1488 }
1489
1490 /* Setup the DMA register accesses, could be DCR or
1491 * memory mapped.
1492 */
1493 if (temac_dcr_setup(lp, pdev, dma_np)) {
1494 /* no DCR in the device tree, try non-DCR */
1495 lp->sdma_regs = devm_of_iomap(&pdev->dev, dma_np, 0,
1496 NULL);
1497 if (IS_ERR(lp->sdma_regs)) {
1498 dev_err(&pdev->dev,
1499 "unable to map DMA registers\n");
1500 of_node_put(dma_np);
1501 return PTR_ERR(lp->sdma_regs);
1502 }
1503 if (of_get_property(dma_np, "little-endian", NULL)) {
1504 lp->dma_in = temac_dma_in32_le;
1505 lp->dma_out = temac_dma_out32_le;
1506 } else {
1507 lp->dma_in = temac_dma_in32_be;
1508 lp->dma_out = temac_dma_out32_be;
1509 }
1510 dev_dbg(&pdev->dev, "MEM base: %p\n", lp->sdma_regs);
1511 }
1512
1513 /* Get DMA RX and TX interrupts */
1514 lp->rx_irq = irq_of_parse_and_map(dma_np, 0);
1515 lp->tx_irq = irq_of_parse_and_map(dma_np, 1);
1516
1517 /* Finished with the DMA node; drop the reference */
1518 of_node_put(dma_np);
1519 } else if (pdata) {
1520 /* 2nd memory resource specifies DMA registers */
1521 lp->sdma_regs = devm_platform_ioremap_resource(pdev, 1);
1522 if (IS_ERR(lp->sdma_regs)) {
1523 dev_err(&pdev->dev,
1524 "could not map DMA registers\n");
1525 return PTR_ERR(lp->sdma_regs);
1526 }
1527 if (pdata->dma_little_endian) {
1528 lp->dma_in = temac_dma_in32_le;
1529 lp->dma_out = temac_dma_out32_le;
1530 } else {
1531 lp->dma_in = temac_dma_in32_be;
1532 lp->dma_out = temac_dma_out32_be;
1533 }
1534
1535 /* Get DMA RX and TX interrupts */
1536 lp->rx_irq = platform_get_irq(pdev, 0);
1537 lp->tx_irq = platform_get_irq(pdev, 1);
1538
1539 /* IRQ delay/coalescing setup */
1540 if (pdata->tx_irq_timeout || pdata->tx_irq_count) {
1541 lp->coalesce_delay_tx = pdata->tx_irq_timeout;
1542 lp->coalesce_count_tx = pdata->tx_irq_count;
1543 }
1544 if (pdata->rx_irq_timeout || pdata->rx_irq_count) {
1545 lp->coalesce_delay_rx = pdata->rx_irq_timeout;
1546 lp->coalesce_count_rx = pdata->rx_irq_count;
1547 }
1548 }
1549
1550 /* Error handle returned DMA RX and TX interrupts */
1551 if (lp->rx_irq < 0) {
1552 if (lp->rx_irq != -EPROBE_DEFER)
1553 dev_err(&pdev->dev, "could not get DMA RX irq\n");
1554 return lp->rx_irq;
1555 }
1556 if (lp->tx_irq < 0) {
1557 if (lp->tx_irq != -EPROBE_DEFER)
1558 dev_err(&pdev->dev, "could not get DMA TX irq\n");
1559 return lp->tx_irq;
1560 }
1561
1562 if (temac_np) {
1563 /* Retrieve the MAC address */
1564 rc = of_get_mac_address(temac_np, addr);
1565 if (rc) {
1566 dev_err(&pdev->dev, "could not find MAC address\n");
1567 return -ENODEV;
1568 }
1569 temac_init_mac_address(ndev, addr);
1570 } else if (pdata) {
1571 temac_init_mac_address(ndev, pdata->mac_addr);
1572 }
1573
1574 rc = temac_mdio_setup(lp, pdev);
1575 if (rc)
1576 dev_warn(&pdev->dev, "error registering MDIO bus\n");
1577
1578 if (temac_np) {
1579 lp->phy_node = of_parse_phandle(temac_np, "phy-handle", 0);
1580 if (lp->phy_node)
1581 dev_dbg(lp->dev, "using PHY node %pOF\n", temac_np);
1582 } else if (pdata) {
1583 snprintf(lp->phy_name, sizeof(lp->phy_name),
1584 PHY_ID_FMT, lp->mii_bus->id, pdata->phy_addr);
1585 lp->phy_interface = pdata->phy_interface;
1586 }
1587
1588 /* Add the device attributes */
1589 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1590 if (rc) {
1591 dev_err(lp->dev, "Error creating sysfs files\n");
1592 goto err_sysfs_create;
1593 }
1594
1595 rc = register_netdev(lp->ndev);
1596 if (rc) {
1597 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1598 goto err_register_ndev;
1599 }
1600
1601 return 0;
1602
1603err_register_ndev:
1604 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1605err_sysfs_create:
1606 if (lp->phy_node)
1607 of_node_put(lp->phy_node);
1608 temac_mdio_teardown(lp);
1609 return rc;
1610}
1611
1612static int temac_remove(struct platform_device *pdev)
1613{
1614 struct net_device *ndev = platform_get_drvdata(pdev);
1615 struct temac_local *lp = netdev_priv(ndev);
1616
1617 unregister_netdev(ndev);
1618 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1619 if (lp->phy_node)
1620 of_node_put(lp->phy_node);
1621 temac_mdio_teardown(lp);
1622 return 0;
1623}
1624
1625static const struct of_device_id temac_of_match[] = {
1626 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1627 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1628 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1629 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1630 {},
1631};
1632MODULE_DEVICE_TABLE(of, temac_of_match);
1633
1634static struct platform_driver temac_driver = {
1635 .probe = temac_probe,
1636 .remove = temac_remove,
1637 .driver = {
1638 .name = "xilinx_temac",
1639 .of_match_table = temac_of_match,
1640 },
1641};
1642
1643module_platform_driver(temac_driver);
1644
1645MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1646MODULE_AUTHOR("Yoshio Kashiwagi");
1647MODULE_LICENSE("GPL");