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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26
27#include "vega10_processpptables.h"
28#include "ppatomfwctrl.h"
29#include "atomfirmware.h"
30#include "pp_debug.h"
31#include "cgs_common.h"
32#include "vega10_pptable.h"
33
34#define NUM_DSPCLK_LEVELS 8
35
36static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
37 enum phm_platform_caps cap)
38{
39 if (enable)
40 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
41 else
42 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
43}
44
45static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
46{
47 int index = GetIndexIntoMasterDataTable(powerplayinfo);
48
49 u16 size;
50 u8 frev, crev;
51 const void *table_address = hwmgr->soft_pp_table;
52
53 if (!table_address) {
54 table_address = (ATOM_Vega10_POWERPLAYTABLE *)
55 cgs_atom_get_data_table(hwmgr->device, index,
56 &size, &frev, &crev);
57
58 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/
59 hwmgr->soft_pp_table_size = size;
60 }
61
62 return table_address;
63}
64
65static int check_powerplay_tables(
66 struct pp_hwmgr *hwmgr,
67 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
68{
69 const ATOM_Vega10_State_Array *state_arrays;
70
71 state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)powerplay_table) +
72 le16_to_cpu(powerplay_table->usStateArrayOffset));
73
74 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
75 ATOM_Vega10_TABLE_REVISION_VEGA10),
76 "Unsupported PPTable format!", return -1);
77 PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset,
78 "State table is not set!", return -1);
79 PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
80 "Invalid PowerPlay Table!", return -1);
81 PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
82 "Invalid PowerPlay Table!", return -1);
83
84 return 0;
85}
86
87static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
88{
89 set_hw_cap(
90 hwmgr,
91 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY),
92 PHM_PlatformCaps_PowerPlaySupport);
93
94 set_hw_cap(
95 hwmgr,
96 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
97 PHM_PlatformCaps_BiosPowerSourceControl);
98
99 set_hw_cap(
100 hwmgr,
101 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC),
102 PHM_PlatformCaps_AutomaticDCTransition);
103
104 set_hw_cap(
105 hwmgr,
106 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_BACO),
107 PHM_PlatformCaps_BACO);
108
109 set_hw_cap(
110 hwmgr,
111 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL),
112 PHM_PlatformCaps_CombinePCCWithThermalSignal);
113
114 return 0;
115}
116
117static int init_thermal_controller(
118 struct pp_hwmgr *hwmgr,
119 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
120{
121 const ATOM_Vega10_Thermal_Controller *thermal_controller;
122 const Vega10_PPTable_Generic_SubTable_Header *header;
123 const ATOM_Vega10_Fan_Table *fan_table_v1;
124 const ATOM_Vega10_Fan_Table_V2 *fan_table_v2;
125
126 thermal_controller = (ATOM_Vega10_Thermal_Controller *)
127 (((unsigned long)powerplay_table) +
128 le16_to_cpu(powerplay_table->usThermalControllerOffset));
129
130 PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),
131 "Thermal controller table not set!", return -EINVAL);
132
133 hwmgr->thermal_controller.ucType = thermal_controller->ucType;
134 hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
135 hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;
136
137 hwmgr->thermal_controller.fanInfo.bNoFan =
138 (0 != (thermal_controller->ucFanParameters &
139 ATOM_VEGA10_PP_FANPARAMETERS_NOFAN));
140
141 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
142 thermal_controller->ucFanParameters &
143 ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
144
145 hwmgr->thermal_controller.fanInfo.ulMinRPM =
146 thermal_controller->ucFanMinRPM * 100UL;
147 hwmgr->thermal_controller.fanInfo.ulMaxRPM =
148 thermal_controller->ucFanMaxRPM * 100UL;
149
150 hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
151 = 100000;
152
153 set_hw_cap(
154 hwmgr,
155 ATOM_VEGA10_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
156 PHM_PlatformCaps_ThermalController);
157
158 if (!powerplay_table->usFanTableOffset)
159 return 0;
160
161 header = (const Vega10_PPTable_Generic_SubTable_Header *)
162 (((unsigned long)powerplay_table) +
163 le16_to_cpu(powerplay_table->usFanTableOffset));
164
165 if (header->ucRevId == 10) {
166 fan_table_v1 = (ATOM_Vega10_Fan_Table *)header;
167
168 PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8),
169 "Invalid Input Fan Table!", return -EINVAL);
170
171 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
172 PHM_PlatformCaps_MicrocodeFanControl);
173
174 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
175 le16_to_cpu(fan_table_v1->usFanOutputSensitivity);
176 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
177 le16_to_cpu(fan_table_v1->usFanRPMMax);
178 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
179 le16_to_cpu(fan_table_v1->usThrottlingRPM);
180 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
181 le16_to_cpu(fan_table_v1->usFanAcousticLimit);
182 hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
183 le16_to_cpu(fan_table_v1->usTargetTemperature);
184 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
185 le16_to_cpu(fan_table_v1->usMinimumPWMLimit);
186 hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
187 le16_to_cpu(fan_table_v1->usTargetGfxClk);
188 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
189 le16_to_cpu(fan_table_v1->usFanGainEdge);
190 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
191 le16_to_cpu(fan_table_v1->usFanGainHotspot);
192 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
193 le16_to_cpu(fan_table_v1->usFanGainLiquid);
194 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
195 le16_to_cpu(fan_table_v1->usFanGainVrVddc);
196 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
197 le16_to_cpu(fan_table_v1->usFanGainVrMvdd);
198 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
199 le16_to_cpu(fan_table_v1->usFanGainPlx);
200 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
201 le16_to_cpu(fan_table_v1->usFanGainHbm);
202
203 hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
204 fan_table_v1->ucEnableZeroRPM;
205 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
206 le16_to_cpu(fan_table_v1->usFanStopTemperature);
207 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
208 le16_to_cpu(fan_table_v1->usFanStartTemperature);
209 } else if (header->ucRevId > 10) {
210 fan_table_v2 = (ATOM_Vega10_Fan_Table_V2 *)header;
211
212 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
213 fan_table_v2->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
214 hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v2->ucFanMinRPM * 100UL;
215 hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v2->ucFanMaxRPM * 100UL;
216 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_MicrocodeFanControl);
218 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
219 le16_to_cpu(fan_table_v2->usFanOutputSensitivity);
220 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
221 fan_table_v2->ucFanMaxRPM * 100UL;
222 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
223 le16_to_cpu(fan_table_v2->usThrottlingRPM);
224 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
225 le16_to_cpu(fan_table_v2->usFanAcousticLimitRpm);
226 hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
227 le16_to_cpu(fan_table_v2->usTargetTemperature);
228 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
229 le16_to_cpu(fan_table_v2->usMinimumPWMLimit);
230 hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
231 le16_to_cpu(fan_table_v2->usTargetGfxClk);
232 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
233 le16_to_cpu(fan_table_v2->usFanGainEdge);
234 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
235 le16_to_cpu(fan_table_v2->usFanGainHotspot);
236 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
237 le16_to_cpu(fan_table_v2->usFanGainLiquid);
238 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
239 le16_to_cpu(fan_table_v2->usFanGainVrVddc);
240 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
241 le16_to_cpu(fan_table_v2->usFanGainVrMvdd);
242 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
243 le16_to_cpu(fan_table_v2->usFanGainPlx);
244 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
245 le16_to_cpu(fan_table_v2->usFanGainHbm);
246
247 hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
248 fan_table_v2->ucEnableZeroRPM;
249 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
250 le16_to_cpu(fan_table_v2->usFanStopTemperature);
251 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
252 le16_to_cpu(fan_table_v2->usFanStartTemperature);
253 }
254 return 0;
255}
256
257static int init_over_drive_limits(
258 struct pp_hwmgr *hwmgr,
259 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
260{
261 hwmgr->platform_descriptor.overdriveLimit.engineClock =
262 le32_to_cpu(powerplay_table->ulMaxODEngineClock);
263 hwmgr->platform_descriptor.overdriveLimit.memoryClock =
264 le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
265
266 hwmgr->platform_descriptor.minOverdriveVDDC = 0;
267 hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
268 hwmgr->platform_descriptor.overdriveVDDCStep = 0;
269
270 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0 ||
271 hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) {
272 hwmgr->od_enabled = false;
273 pr_debug("OverDrive feature not support by VBIOS\n");
274 }
275
276 return 0;
277}
278
279static int get_mm_clock_voltage_table(
280 struct pp_hwmgr *hwmgr,
281 phm_ppt_v1_mm_clock_voltage_dependency_table **vega10_mm_table,
282 const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table)
283{
284 uint32_t table_size, i;
285 const ATOM_Vega10_MM_Dependency_Record *mm_dependency_record;
286 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table;
287
288 PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0),
289 "Invalid PowerPlay Table!", return -1);
290
291 table_size = sizeof(uint32_t) +
292 sizeof(phm_ppt_v1_mm_clock_voltage_dependency_record) *
293 mm_dependency_table->ucNumEntries;
294 mm_table = kzalloc(table_size, GFP_KERNEL);
295
296 if (!mm_table)
297 return -ENOMEM;
298
299 mm_table->count = mm_dependency_table->ucNumEntries;
300
301 for (i = 0; i < mm_dependency_table->ucNumEntries; i++) {
302 mm_dependency_record = &mm_dependency_table->entries[i];
303 mm_table->entries[i].vddcInd = mm_dependency_record->ucVddcInd;
304 mm_table->entries[i].samclock =
305 le32_to_cpu(mm_dependency_record->ulPSPClk);
306 mm_table->entries[i].eclk = le32_to_cpu(mm_dependency_record->ulEClk);
307 mm_table->entries[i].vclk = le32_to_cpu(mm_dependency_record->ulVClk);
308 mm_table->entries[i].dclk = le32_to_cpu(mm_dependency_record->ulDClk);
309 }
310
311 *vega10_mm_table = mm_table;
312
313 return 0;
314}
315
316static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
317{
318 switch(line){
319 case Vega10_I2CLineID_DDC1:
320 *scl = Vega10_I2C_DDC1CLK;
321 *sda = Vega10_I2C_DDC1DATA;
322 break;
323 case Vega10_I2CLineID_DDC2:
324 *scl = Vega10_I2C_DDC2CLK;
325 *sda = Vega10_I2C_DDC2DATA;
326 break;
327 case Vega10_I2CLineID_DDC3:
328 *scl = Vega10_I2C_DDC3CLK;
329 *sda = Vega10_I2C_DDC3DATA;
330 break;
331 case Vega10_I2CLineID_DDC4:
332 *scl = Vega10_I2C_DDC4CLK;
333 *sda = Vega10_I2C_DDC4DATA;
334 break;
335 case Vega10_I2CLineID_DDC5:
336 *scl = Vega10_I2C_DDC5CLK;
337 *sda = Vega10_I2C_DDC5DATA;
338 break;
339 case Vega10_I2CLineID_DDC6:
340 *scl = Vega10_I2C_DDC6CLK;
341 *sda = Vega10_I2C_DDC6DATA;
342 break;
343 case Vega10_I2CLineID_SCLSDA:
344 *scl = Vega10_I2C_SCL;
345 *sda = Vega10_I2C_SDA;
346 break;
347 case Vega10_I2CLineID_DDCVGA:
348 *scl = Vega10_I2C_DDCVGACLK;
349 *sda = Vega10_I2C_DDCVGADATA;
350 break;
351 default:
352 *scl = 0;
353 *sda = 0;
354 break;
355 }
356}
357
358static int get_tdp_table(
359 struct pp_hwmgr *hwmgr,
360 struct phm_tdp_table **info_tdp_table,
361 const Vega10_PPTable_Generic_SubTable_Header *table)
362{
363 uint32_t table_size;
364 struct phm_tdp_table *tdp_table;
365 uint8_t scl;
366 uint8_t sda;
367 const ATOM_Vega10_PowerTune_Table *power_tune_table;
368 const ATOM_Vega10_PowerTune_Table_V2 *power_tune_table_v2;
369 const ATOM_Vega10_PowerTune_Table_V3 *power_tune_table_v3;
370
371 table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table);
372
373 tdp_table = kzalloc(table_size, GFP_KERNEL);
374
375 if (!tdp_table)
376 return -ENOMEM;
377
378 if (table->ucRevId == 5) {
379 power_tune_table = (ATOM_Vega10_PowerTune_Table *)table;
380 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table->usSocketPowerLimit);
381 tdp_table->usTDC = le16_to_cpu(power_tune_table->usTdcLimit);
382 tdp_table->usEDCLimit = le16_to_cpu(power_tune_table->usEdcLimit);
383 tdp_table->usSoftwareShutdownTemp =
384 le16_to_cpu(power_tune_table->usSoftwareShutdownTemp);
385 tdp_table->usTemperatureLimitTedge =
386 le16_to_cpu(power_tune_table->usTemperatureLimitTedge);
387 tdp_table->usTemperatureLimitHotspot =
388 le16_to_cpu(power_tune_table->usTemperatureLimitHotSpot);
389 tdp_table->usTemperatureLimitLiquid1 =
390 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid1);
391 tdp_table->usTemperatureLimitLiquid2 =
392 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid2);
393 tdp_table->usTemperatureLimitHBM =
394 le16_to_cpu(power_tune_table->usTemperatureLimitHBM);
395 tdp_table->usTemperatureLimitVrVddc =
396 le16_to_cpu(power_tune_table->usTemperatureLimitVrSoc);
397 tdp_table->usTemperatureLimitVrMvdd =
398 le16_to_cpu(power_tune_table->usTemperatureLimitVrMem);
399 tdp_table->usTemperatureLimitPlx =
400 le16_to_cpu(power_tune_table->usTemperatureLimitPlx);
401 tdp_table->ucLiquid1_I2C_address = power_tune_table->ucLiquid1_I2C_address;
402 tdp_table->ucLiquid2_I2C_address = power_tune_table->ucLiquid2_I2C_address;
403 tdp_table->ucLiquid_I2C_Line = power_tune_table->ucLiquid_I2C_LineSCL;
404 tdp_table->ucLiquid_I2C_LineSDA = power_tune_table->ucLiquid_I2C_LineSDA;
405 tdp_table->ucVr_I2C_address = power_tune_table->ucVr_I2C_address;
406 tdp_table->ucVr_I2C_Line = power_tune_table->ucVr_I2C_LineSCL;
407 tdp_table->ucVr_I2C_LineSDA = power_tune_table->ucVr_I2C_LineSDA;
408 tdp_table->ucPlx_I2C_address = power_tune_table->ucPlx_I2C_address;
409 tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL;
410 tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA;
411 hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table->usLoadLineResistance);
412 } else if (table->ucRevId == 6) {
413 power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table;
414 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit);
415 tdp_table->usTDC = le16_to_cpu(power_tune_table_v2->usTdcLimit);
416 tdp_table->usEDCLimit = le16_to_cpu(power_tune_table_v2->usEdcLimit);
417 tdp_table->usSoftwareShutdownTemp =
418 le16_to_cpu(power_tune_table_v2->usSoftwareShutdownTemp);
419 tdp_table->usTemperatureLimitTedge =
420 le16_to_cpu(power_tune_table_v2->usTemperatureLimitTedge);
421 tdp_table->usTemperatureLimitHotspot =
422 le16_to_cpu(power_tune_table_v2->usTemperatureLimitHotSpot);
423 tdp_table->usTemperatureLimitLiquid1 =
424 le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid1);
425 tdp_table->usTemperatureLimitLiquid2 =
426 le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid2);
427 tdp_table->usTemperatureLimitHBM =
428 le16_to_cpu(power_tune_table_v2->usTemperatureLimitHBM);
429 tdp_table->usTemperatureLimitVrVddc =
430 le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrSoc);
431 tdp_table->usTemperatureLimitVrMvdd =
432 le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrMem);
433 tdp_table->usTemperatureLimitPlx =
434 le16_to_cpu(power_tune_table_v2->usTemperatureLimitPlx);
435 tdp_table->ucLiquid1_I2C_address = power_tune_table_v2->ucLiquid1_I2C_address;
436 tdp_table->ucLiquid2_I2C_address = power_tune_table_v2->ucLiquid2_I2C_address;
437
438 get_scl_sda_value(power_tune_table_v2->ucLiquid_I2C_Line, &scl, &sda);
439
440 tdp_table->ucLiquid_I2C_Line = scl;
441 tdp_table->ucLiquid_I2C_LineSDA = sda;
442
443 tdp_table->ucVr_I2C_address = power_tune_table_v2->ucVr_I2C_address;
444
445 get_scl_sda_value(power_tune_table_v2->ucVr_I2C_Line, &scl, &sda);
446
447 tdp_table->ucVr_I2C_Line = scl;
448 tdp_table->ucVr_I2C_LineSDA = sda;
449 tdp_table->ucPlx_I2C_address = power_tune_table_v2->ucPlx_I2C_address;
450
451 get_scl_sda_value(power_tune_table_v2->ucPlx_I2C_Line, &scl, &sda);
452
453 tdp_table->ucPlx_I2C_Line = scl;
454 tdp_table->ucPlx_I2C_LineSDA = sda;
455
456 hwmgr->platform_descriptor.LoadLineSlope =
457 le16_to_cpu(power_tune_table_v2->usLoadLineResistance);
458 } else {
459 power_tune_table_v3 = (ATOM_Vega10_PowerTune_Table_V3 *)table;
460 tdp_table->usMaximumPowerDeliveryLimit = power_tune_table_v3->usSocketPowerLimit;
461 tdp_table->usTDC = power_tune_table_v3->usTdcLimit;
462 tdp_table->usEDCLimit = power_tune_table_v3->usEdcLimit;
463 tdp_table->usSoftwareShutdownTemp = power_tune_table_v3->usSoftwareShutdownTemp;
464 tdp_table->usTemperatureLimitTedge = power_tune_table_v3->usTemperatureLimitTedge;
465 tdp_table->usTemperatureLimitHotspot = power_tune_table_v3->usTemperatureLimitHotSpot;
466 tdp_table->usTemperatureLimitLiquid1 = power_tune_table_v3->usTemperatureLimitLiquid1;
467 tdp_table->usTemperatureLimitLiquid2 = power_tune_table_v3->usTemperatureLimitLiquid2;
468 tdp_table->usTemperatureLimitHBM = power_tune_table_v3->usTemperatureLimitHBM;
469 tdp_table->usTemperatureLimitVrVddc = power_tune_table_v3->usTemperatureLimitVrSoc;
470 tdp_table->usTemperatureLimitVrMvdd = power_tune_table_v3->usTemperatureLimitVrMem;
471 tdp_table->usTemperatureLimitPlx = power_tune_table_v3->usTemperatureLimitPlx;
472 tdp_table->ucLiquid1_I2C_address = power_tune_table_v3->ucLiquid1_I2C_address;
473 tdp_table->ucLiquid2_I2C_address = power_tune_table_v3->ucLiquid2_I2C_address;
474 tdp_table->usBoostStartTemperature = power_tune_table_v3->usBoostStartTemperature;
475 tdp_table->usBoostStopTemperature = power_tune_table_v3->usBoostStopTemperature;
476 tdp_table->ulBoostClock = power_tune_table_v3->ulBoostClock;
477
478 get_scl_sda_value(power_tune_table_v3->ucLiquid_I2C_Line, &scl, &sda);
479
480 tdp_table->ucLiquid_I2C_Line = scl;
481 tdp_table->ucLiquid_I2C_LineSDA = sda;
482
483 tdp_table->ucVr_I2C_address = power_tune_table_v3->ucVr_I2C_address;
484
485 get_scl_sda_value(power_tune_table_v3->ucVr_I2C_Line, &scl, &sda);
486
487 tdp_table->ucVr_I2C_Line = scl;
488 tdp_table->ucVr_I2C_LineSDA = sda;
489
490 tdp_table->ucPlx_I2C_address = power_tune_table_v3->ucPlx_I2C_address;
491
492 get_scl_sda_value(power_tune_table_v3->ucPlx_I2C_Line, &scl, &sda);
493
494 tdp_table->ucPlx_I2C_Line = scl;
495 tdp_table->ucPlx_I2C_LineSDA = sda;
496
497 hwmgr->platform_descriptor.LoadLineSlope =
498 le16_to_cpu(power_tune_table_v3->usLoadLineResistance);
499 }
500
501 *info_tdp_table = tdp_table;
502
503 return 0;
504}
505
506static int get_socclk_voltage_dependency_table(
507 struct pp_hwmgr *hwmgr,
508 phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_clk_dep_table,
509 const ATOM_Vega10_SOCCLK_Dependency_Table *clk_dep_table)
510{
511 uint32_t table_size, i;
512 phm_ppt_v1_clock_voltage_dependency_table *clk_table;
513
514 PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries,
515 "Invalid PowerPlay Table!", return -1);
516
517 table_size = sizeof(uint32_t) +
518 sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
519 clk_dep_table->ucNumEntries;
520
521 clk_table = kzalloc(table_size, GFP_KERNEL);
522
523 if (!clk_table)
524 return -ENOMEM;
525
526 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries;
527
528 for (i = 0; i < clk_dep_table->ucNumEntries; i++) {
529 clk_table->entries[i].vddInd =
530 clk_dep_table->entries[i].ucVddInd;
531 clk_table->entries[i].clk =
532 le32_to_cpu(clk_dep_table->entries[i].ulClk);
533 }
534
535 *pp_vega10_clk_dep_table = clk_table;
536
537 return 0;
538}
539
540static int get_mclk_voltage_dependency_table(
541 struct pp_hwmgr *hwmgr,
542 phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_mclk_dep_table,
543 const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table)
544{
545 uint32_t table_size, i;
546 phm_ppt_v1_clock_voltage_dependency_table *mclk_table;
547
548 PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries,
549 "Invalid PowerPlay Table!", return -1);
550
551 table_size = sizeof(uint32_t) +
552 sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
553 mclk_dep_table->ucNumEntries;
554
555 mclk_table = kzalloc(table_size, GFP_KERNEL);
556
557 if (!mclk_table)
558 return -ENOMEM;
559
560 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
561
562 for (i = 0; i < mclk_dep_table->ucNumEntries; i++) {
563 mclk_table->entries[i].vddInd =
564 mclk_dep_table->entries[i].ucVddInd;
565 mclk_table->entries[i].vddciInd =
566 mclk_dep_table->entries[i].ucVddciInd;
567 mclk_table->entries[i].mvddInd =
568 mclk_dep_table->entries[i].ucVddMemInd;
569 mclk_table->entries[i].clk =
570 le32_to_cpu(mclk_dep_table->entries[i].ulMemClk);
571 }
572
573 *pp_vega10_mclk_dep_table = mclk_table;
574
575 return 0;
576}
577
578static int get_gfxclk_voltage_dependency_table(
579 struct pp_hwmgr *hwmgr,
580 struct phm_ppt_v1_clock_voltage_dependency_table
581 **pp_vega10_clk_dep_table,
582 const ATOM_Vega10_GFXCLK_Dependency_Table *clk_dep_table)
583{
584 uint32_t table_size, i;
585 struct phm_ppt_v1_clock_voltage_dependency_table
586 *clk_table;
587 ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;
588
589 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
590 "Invalid PowerPlay Table!", return -1);
591
592 table_size = sizeof(uint32_t) +
593 sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
594 clk_dep_table->ucNumEntries;
595
596 clk_table = kzalloc(table_size, GFP_KERNEL);
597
598 if (!clk_table)
599 return -ENOMEM;
600
601 clk_table->count = clk_dep_table->ucNumEntries;
602
603 if (clk_dep_table->ucRevId == 0) {
604 for (i = 0; i < clk_table->count; i++) {
605 clk_table->entries[i].vddInd =
606 clk_dep_table->entries[i].ucVddInd;
607 clk_table->entries[i].clk =
608 le32_to_cpu(clk_dep_table->entries[i].ulClk);
609 clk_table->entries[i].cks_enable =
610 (((le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x8000)
611 >> 15) == 0) ? 1 : 0;
612 clk_table->entries[i].cks_voffset =
613 le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x7F;
614 clk_table->entries[i].sclk_offset =
615 le16_to_cpu(clk_dep_table->entries[i].usAVFSOffset);
616 }
617 } else if (clk_dep_table->ucRevId == 1) {
618 patom_record_v2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)clk_dep_table->entries;
619 for (i = 0; i < clk_table->count; i++) {
620 clk_table->entries[i].vddInd =
621 patom_record_v2->ucVddInd;
622 clk_table->entries[i].clk =
623 le32_to_cpu(patom_record_v2->ulClk);
624 clk_table->entries[i].cks_enable =
625 (((le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x8000)
626 >> 15) == 0) ? 1 : 0;
627 clk_table->entries[i].cks_voffset =
628 le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x7F;
629 clk_table->entries[i].sclk_offset =
630 le16_to_cpu(patom_record_v2->usAVFSOffset);
631 patom_record_v2++;
632 }
633 } else {
634 kfree(clk_table);
635 PP_ASSERT_WITH_CODE(false,
636 "Unsupported GFXClockDependencyTable Revision!",
637 return -EINVAL);
638 }
639
640 *pp_vega10_clk_dep_table = clk_table;
641
642 return 0;
643}
644
645static int get_pix_clk_voltage_dependency_table(
646 struct pp_hwmgr *hwmgr,
647 struct phm_ppt_v1_clock_voltage_dependency_table
648 **pp_vega10_clk_dep_table,
649 const ATOM_Vega10_PIXCLK_Dependency_Table *clk_dep_table)
650{
651 uint32_t table_size, i;
652 struct phm_ppt_v1_clock_voltage_dependency_table
653 *clk_table;
654
655 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
656 "Invalid PowerPlay Table!", return -1);
657
658 table_size = sizeof(uint32_t) +
659 sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
660 clk_dep_table->ucNumEntries;
661
662 clk_table = kzalloc(table_size, GFP_KERNEL);
663
664 if (!clk_table)
665 return -ENOMEM;
666
667 clk_table->count = clk_dep_table->ucNumEntries;
668
669 for (i = 0; i < clk_table->count; i++) {
670 clk_table->entries[i].vddInd =
671 clk_dep_table->entries[i].ucVddInd;
672 clk_table->entries[i].clk =
673 le32_to_cpu(clk_dep_table->entries[i].ulClk);
674 }
675
676 *pp_vega10_clk_dep_table = clk_table;
677
678 return 0;
679}
680
681static int get_dcefclk_voltage_dependency_table(
682 struct pp_hwmgr *hwmgr,
683 struct phm_ppt_v1_clock_voltage_dependency_table
684 **pp_vega10_clk_dep_table,
685 const ATOM_Vega10_DCEFCLK_Dependency_Table *clk_dep_table)
686{
687 uint32_t table_size, i;
688 uint8_t num_entries;
689 struct phm_ppt_v1_clock_voltage_dependency_table
690 *clk_table;
691 uint32_t dev_id;
692 uint32_t rev_id;
693 struct amdgpu_device *adev = hwmgr->adev;
694
695 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
696 "Invalid PowerPlay Table!", return -1);
697
698/*
699 * workaround needed to add another DPM level for pioneer cards
700 * as VBIOS is locked down.
701 * This DPM level was added to support 3DPM monitors @ 4K120Hz
702 *
703 */
704 dev_id = adev->pdev->device;
705 rev_id = adev->pdev->revision;
706
707 if (dev_id == 0x6863 && rev_id == 0 &&
708 clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000)
709 num_entries = clk_dep_table->ucNumEntries + 1 > NUM_DSPCLK_LEVELS ?
710 NUM_DSPCLK_LEVELS : clk_dep_table->ucNumEntries + 1;
711 else
712 num_entries = clk_dep_table->ucNumEntries;
713
714
715 table_size = sizeof(uint32_t) +
716 sizeof(phm_ppt_v1_clock_voltage_dependency_record) *
717 num_entries;
718
719 clk_table = kzalloc(table_size, GFP_KERNEL);
720
721 if (!clk_table)
722 return -ENOMEM;
723
724 clk_table->count = (uint32_t)num_entries;
725
726 for (i = 0; i < clk_dep_table->ucNumEntries; i++) {
727 clk_table->entries[i].vddInd =
728 clk_dep_table->entries[i].ucVddInd;
729 clk_table->entries[i].clk =
730 le32_to_cpu(clk_dep_table->entries[i].ulClk);
731 }
732
733 if (i < num_entries) {
734 clk_table->entries[i].vddInd = clk_dep_table->entries[i-1].ucVddInd;
735 clk_table->entries[i].clk = 90000;
736 }
737
738 *pp_vega10_clk_dep_table = clk_table;
739
740 return 0;
741}
742
743static int get_pcie_table(struct pp_hwmgr *hwmgr,
744 struct phm_ppt_v1_pcie_table **vega10_pcie_table,
745 const Vega10_PPTable_Generic_SubTable_Header *table)
746{
747 uint32_t table_size, i, pcie_count;
748 struct phm_ppt_v1_pcie_table *pcie_table;
749 struct phm_ppt_v2_information *table_info =
750 (struct phm_ppt_v2_information *)(hwmgr->pptable);
751 const ATOM_Vega10_PCIE_Table *atom_pcie_table =
752 (ATOM_Vega10_PCIE_Table *)table;
753
754 PP_ASSERT_WITH_CODE(atom_pcie_table->ucNumEntries,
755 "Invalid PowerPlay Table!",
756 return 0);
757
758 table_size = sizeof(uint32_t) +
759 sizeof(struct phm_ppt_v1_pcie_record) *
760 atom_pcie_table->ucNumEntries;
761
762 pcie_table = kzalloc(table_size, GFP_KERNEL);
763
764 if (!pcie_table)
765 return -ENOMEM;
766
767 pcie_count = table_info->vdd_dep_on_sclk->count;
768 if (atom_pcie_table->ucNumEntries <= pcie_count)
769 pcie_count = atom_pcie_table->ucNumEntries;
770 else
771 pr_info("Number of Pcie Entries exceed the number of"
772 " GFXCLK Dpm Levels!"
773 " Disregarding the excess entries...\n");
774
775 pcie_table->count = pcie_count;
776
777 for (i = 0; i < pcie_count; i++) {
778 pcie_table->entries[i].gen_speed =
779 atom_pcie_table->entries[i].ucPCIEGenSpeed;
780 pcie_table->entries[i].lane_width =
781 atom_pcie_table->entries[i].ucPCIELaneWidth;
782 pcie_table->entries[i].pcie_sclk =
783 atom_pcie_table->entries[i].ulLCLK;
784 }
785
786 *vega10_pcie_table = pcie_table;
787
788 return 0;
789}
790
791static int get_hard_limits(
792 struct pp_hwmgr *hwmgr,
793 struct phm_clock_and_voltage_limits *limits,
794 const ATOM_Vega10_Hard_Limit_Table *limit_table)
795{
796 PP_ASSERT_WITH_CODE(limit_table->ucNumEntries,
797 "Invalid PowerPlay Table!", return -1);
798
799 /* currently we always take entries[0] parameters */
800 limits->sclk = le32_to_cpu(limit_table->entries[0].ulSOCCLKLimit);
801 limits->mclk = le32_to_cpu(limit_table->entries[0].ulMCLKLimit);
802 limits->gfxclk = le32_to_cpu(limit_table->entries[0].ulGFXCLKLimit);
803 limits->vddc = le16_to_cpu(limit_table->entries[0].usVddcLimit);
804 limits->vddci = le16_to_cpu(limit_table->entries[0].usVddciLimit);
805 limits->vddmem = le16_to_cpu(limit_table->entries[0].usVddMemLimit);
806
807 return 0;
808}
809
810static int get_valid_clk(
811 struct pp_hwmgr *hwmgr,
812 struct phm_clock_array **clk_table,
813 const phm_ppt_v1_clock_voltage_dependency_table *clk_volt_pp_table)
814{
815 uint32_t table_size, i;
816 struct phm_clock_array *table;
817
818 PP_ASSERT_WITH_CODE(clk_volt_pp_table->count,
819 "Invalid PowerPlay Table!", return -1);
820
821 table_size = sizeof(uint32_t) +
822 sizeof(uint32_t) * clk_volt_pp_table->count;
823
824 table = kzalloc(table_size, GFP_KERNEL);
825
826 if (!table)
827 return -ENOMEM;
828
829 table->count = (uint32_t)clk_volt_pp_table->count;
830
831 for (i = 0; i < table->count; i++)
832 table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk;
833
834 *clk_table = table;
835
836 return 0;
837}
838
839static int init_powerplay_extended_tables(
840 struct pp_hwmgr *hwmgr,
841 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
842{
843 int result = 0;
844 struct phm_ppt_v2_information *pp_table_info =
845 (struct phm_ppt_v2_information *)(hwmgr->pptable);
846
847 const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table =
848 (const ATOM_Vega10_MM_Dependency_Table *)
849 (((unsigned long) powerplay_table) +
850 le16_to_cpu(powerplay_table->usMMDependencyTableOffset));
851 const Vega10_PPTable_Generic_SubTable_Header *power_tune_table =
852 (const Vega10_PPTable_Generic_SubTable_Header *)
853 (((unsigned long) powerplay_table) +
854 le16_to_cpu(powerplay_table->usPowerTuneTableOffset));
855 const ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
856 (const ATOM_Vega10_SOCCLK_Dependency_Table *)
857 (((unsigned long) powerplay_table) +
858 le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
859 const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
860 (const ATOM_Vega10_GFXCLK_Dependency_Table *)
861 (((unsigned long) powerplay_table) +
862 le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
863 const ATOM_Vega10_DCEFCLK_Dependency_Table *dcefclk_dep_table =
864 (const ATOM_Vega10_DCEFCLK_Dependency_Table *)
865 (((unsigned long) powerplay_table) +
866 le16_to_cpu(powerplay_table->usDcefclkDependencyTableOffset));
867 const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
868 (const ATOM_Vega10_MCLK_Dependency_Table *)
869 (((unsigned long) powerplay_table) +
870 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
871 const ATOM_Vega10_Hard_Limit_Table *hard_limits =
872 (const ATOM_Vega10_Hard_Limit_Table *)
873 (((unsigned long) powerplay_table) +
874 le16_to_cpu(powerplay_table->usHardLimitTableOffset));
875 const Vega10_PPTable_Generic_SubTable_Header *pcie_table =
876 (const Vega10_PPTable_Generic_SubTable_Header *)
877 (((unsigned long) powerplay_table) +
878 le16_to_cpu(powerplay_table->usPCIETableOffset));
879 const ATOM_Vega10_PIXCLK_Dependency_Table *pixclk_dep_table =
880 (const ATOM_Vega10_PIXCLK_Dependency_Table *)
881 (((unsigned long) powerplay_table) +
882 le16_to_cpu(powerplay_table->usPixclkDependencyTableOffset));
883 const ATOM_Vega10_PHYCLK_Dependency_Table *phyclk_dep_table =
884 (const ATOM_Vega10_PHYCLK_Dependency_Table *)
885 (((unsigned long) powerplay_table) +
886 le16_to_cpu(powerplay_table->usPhyClkDependencyTableOffset));
887 const ATOM_Vega10_DISPCLK_Dependency_Table *dispclk_dep_table =
888 (const ATOM_Vega10_DISPCLK_Dependency_Table *)
889 (((unsigned long) powerplay_table) +
890 le16_to_cpu(powerplay_table->usDispClkDependencyTableOffset));
891
892 pp_table_info->vdd_dep_on_socclk = NULL;
893 pp_table_info->vdd_dep_on_sclk = NULL;
894 pp_table_info->vdd_dep_on_mclk = NULL;
895 pp_table_info->vdd_dep_on_dcefclk = NULL;
896 pp_table_info->mm_dep_table = NULL;
897 pp_table_info->tdp_table = NULL;
898 pp_table_info->vdd_dep_on_pixclk = NULL;
899 pp_table_info->vdd_dep_on_phyclk = NULL;
900 pp_table_info->vdd_dep_on_dispclk = NULL;
901
902 if (powerplay_table->usMMDependencyTableOffset)
903 result = get_mm_clock_voltage_table(hwmgr,
904 &pp_table_info->mm_dep_table,
905 mm_dependency_table);
906
907 if (!result && powerplay_table->usPowerTuneTableOffset)
908 result = get_tdp_table(hwmgr,
909 &pp_table_info->tdp_table,
910 power_tune_table);
911
912 if (!result && powerplay_table->usSocclkDependencyTableOffset)
913 result = get_socclk_voltage_dependency_table(hwmgr,
914 &pp_table_info->vdd_dep_on_socclk,
915 socclk_dep_table);
916
917 if (!result && powerplay_table->usGfxclkDependencyTableOffset)
918 result = get_gfxclk_voltage_dependency_table(hwmgr,
919 &pp_table_info->vdd_dep_on_sclk,
920 gfxclk_dep_table);
921
922 if (!result && powerplay_table->usPixclkDependencyTableOffset)
923 result = get_pix_clk_voltage_dependency_table(hwmgr,
924 &pp_table_info->vdd_dep_on_pixclk,
925 (const ATOM_Vega10_PIXCLK_Dependency_Table*)
926 pixclk_dep_table);
927
928 if (!result && powerplay_table->usPhyClkDependencyTableOffset)
929 result = get_pix_clk_voltage_dependency_table(hwmgr,
930 &pp_table_info->vdd_dep_on_phyclk,
931 (const ATOM_Vega10_PIXCLK_Dependency_Table *)
932 phyclk_dep_table);
933
934 if (!result && powerplay_table->usDispClkDependencyTableOffset)
935 result = get_pix_clk_voltage_dependency_table(hwmgr,
936 &pp_table_info->vdd_dep_on_dispclk,
937 (const ATOM_Vega10_PIXCLK_Dependency_Table *)
938 dispclk_dep_table);
939
940 if (!result && powerplay_table->usDcefclkDependencyTableOffset)
941 result = get_dcefclk_voltage_dependency_table(hwmgr,
942 &pp_table_info->vdd_dep_on_dcefclk,
943 dcefclk_dep_table);
944
945 if (!result && powerplay_table->usMclkDependencyTableOffset)
946 result = get_mclk_voltage_dependency_table(hwmgr,
947 &pp_table_info->vdd_dep_on_mclk,
948 mclk_dep_table);
949
950 if (!result && powerplay_table->usPCIETableOffset)
951 result = get_pcie_table(hwmgr,
952 &pp_table_info->pcie_table,
953 pcie_table);
954
955 if (!result && powerplay_table->usHardLimitTableOffset)
956 result = get_hard_limits(hwmgr,
957 &pp_table_info->max_clock_voltage_on_dc,
958 hard_limits);
959
960 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
961 pp_table_info->max_clock_voltage_on_dc.sclk;
962 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
963 pp_table_info->max_clock_voltage_on_dc.mclk;
964 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
965 pp_table_info->max_clock_voltage_on_dc.vddc;
966 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
967 pp_table_info->max_clock_voltage_on_dc.vddci;
968
969 if (!result &&
970 pp_table_info->vdd_dep_on_socclk &&
971 pp_table_info->vdd_dep_on_socclk->count)
972 result = get_valid_clk(hwmgr,
973 &pp_table_info->valid_socclk_values,
974 pp_table_info->vdd_dep_on_socclk);
975
976 if (!result &&
977 pp_table_info->vdd_dep_on_sclk &&
978 pp_table_info->vdd_dep_on_sclk->count)
979 result = get_valid_clk(hwmgr,
980 &pp_table_info->valid_sclk_values,
981 pp_table_info->vdd_dep_on_sclk);
982
983 if (!result &&
984 pp_table_info->vdd_dep_on_dcefclk &&
985 pp_table_info->vdd_dep_on_dcefclk->count)
986 result = get_valid_clk(hwmgr,
987 &pp_table_info->valid_dcefclk_values,
988 pp_table_info->vdd_dep_on_dcefclk);
989
990 if (!result &&
991 pp_table_info->vdd_dep_on_mclk &&
992 pp_table_info->vdd_dep_on_mclk->count)
993 result = get_valid_clk(hwmgr,
994 &pp_table_info->valid_mclk_values,
995 pp_table_info->vdd_dep_on_mclk);
996
997 return result;
998}
999
1000static int get_vddc_lookup_table(
1001 struct pp_hwmgr *hwmgr,
1002 phm_ppt_v1_voltage_lookup_table **lookup_table,
1003 const ATOM_Vega10_Voltage_Lookup_Table *vddc_lookup_pp_tables,
1004 uint32_t max_levels)
1005{
1006 uint32_t table_size, i;
1007 phm_ppt_v1_voltage_lookup_table *table;
1008
1009 PP_ASSERT_WITH_CODE((vddc_lookup_pp_tables->ucNumEntries != 0),
1010 "Invalid SOC_VDDD Lookup Table!", return 1);
1011
1012 table_size = sizeof(uint32_t) +
1013 sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels;
1014
1015 table = kzalloc(table_size, GFP_KERNEL);
1016
1017 if (table == NULL)
1018 return -ENOMEM;
1019
1020 table->count = vddc_lookup_pp_tables->ucNumEntries;
1021
1022 for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++)
1023 table->entries[i].us_vdd =
1024 le16_to_cpu(vddc_lookup_pp_tables->entries[i].usVdd);
1025
1026 *lookup_table = table;
1027
1028 return 0;
1029}
1030
1031static int init_dpm_2_parameters(
1032 struct pp_hwmgr *hwmgr,
1033 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
1034{
1035 int result = 0;
1036 struct phm_ppt_v2_information *pp_table_info =
1037 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1038 uint32_t disable_power_control = 0;
1039
1040 pp_table_info->us_ulv_voltage_offset =
1041 le16_to_cpu(powerplay_table->usUlvVoltageOffset);
1042
1043 pp_table_info->us_ulv_smnclk_did =
1044 le16_to_cpu(powerplay_table->usUlvSmnclkDid);
1045 pp_table_info->us_ulv_mp1clk_did =
1046 le16_to_cpu(powerplay_table->usUlvMp1clkDid);
1047 pp_table_info->us_ulv_gfxclk_bypass =
1048 le16_to_cpu(powerplay_table->usUlvGfxclkBypass);
1049 pp_table_info->us_gfxclk_slew_rate =
1050 le16_to_cpu(powerplay_table->usGfxclkSlewRate);
1051 pp_table_info->uc_gfx_dpm_voltage_mode =
1052 le16_to_cpu(powerplay_table->ucGfxVoltageMode);
1053 pp_table_info->uc_soc_dpm_voltage_mode =
1054 le16_to_cpu(powerplay_table->ucSocVoltageMode);
1055 pp_table_info->uc_uclk_dpm_voltage_mode =
1056 le16_to_cpu(powerplay_table->ucUclkVoltageMode);
1057 pp_table_info->uc_uvd_dpm_voltage_mode =
1058 le16_to_cpu(powerplay_table->ucUvdVoltageMode);
1059 pp_table_info->uc_vce_dpm_voltage_mode =
1060 le16_to_cpu(powerplay_table->ucVceVoltageMode);
1061 pp_table_info->uc_mp0_dpm_voltage_mode =
1062 le16_to_cpu(powerplay_table->ucMp0VoltageMode);
1063 pp_table_info->uc_dcef_dpm_voltage_mode =
1064 le16_to_cpu(powerplay_table->ucDcefVoltageMode);
1065
1066 pp_table_info->ppm_parameter_table = NULL;
1067 pp_table_info->vddc_lookup_table = NULL;
1068 pp_table_info->vddmem_lookup_table = NULL;
1069 pp_table_info->vddci_lookup_table = NULL;
1070
1071 /* TDP limits */
1072 hwmgr->platform_descriptor.TDPODLimit =
1073 le16_to_cpu(powerplay_table->usPowerControlLimit);
1074 hwmgr->platform_descriptor.TDPAdjustment = 0;
1075 hwmgr->platform_descriptor.VidAdjustment = 0;
1076 hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
1077 hwmgr->platform_descriptor.VidMinLimit = 0;
1078 hwmgr->platform_descriptor.VidMaxLimit = 1500000;
1079 hwmgr->platform_descriptor.VidStep = 6250;
1080
1081 disable_power_control = 0;
1082 if (!disable_power_control) {
1083 /* enable TDP overdrive (PowerControl) feature as well if supported */
1084 if (hwmgr->platform_descriptor.TDPODLimit)
1085 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1086 PHM_PlatformCaps_PowerControl);
1087 }
1088
1089 if (powerplay_table->usVddcLookupTableOffset) {
1090 const ATOM_Vega10_Voltage_Lookup_Table *vddc_table =
1091 (ATOM_Vega10_Voltage_Lookup_Table *)
1092 (((unsigned long)powerplay_table) +
1093 le16_to_cpu(powerplay_table->usVddcLookupTableOffset));
1094 result = get_vddc_lookup_table(hwmgr,
1095 &pp_table_info->vddc_lookup_table, vddc_table, 8);
1096 }
1097
1098 if (powerplay_table->usVddmemLookupTableOffset) {
1099 const ATOM_Vega10_Voltage_Lookup_Table *vdd_mem_table =
1100 (ATOM_Vega10_Voltage_Lookup_Table *)
1101 (((unsigned long)powerplay_table) +
1102 le16_to_cpu(powerplay_table->usVddmemLookupTableOffset));
1103 result = get_vddc_lookup_table(hwmgr,
1104 &pp_table_info->vddmem_lookup_table, vdd_mem_table, 4);
1105 }
1106
1107 if (powerplay_table->usVddciLookupTableOffset) {
1108 const ATOM_Vega10_Voltage_Lookup_Table *vddci_table =
1109 (ATOM_Vega10_Voltage_Lookup_Table *)
1110 (((unsigned long)powerplay_table) +
1111 le16_to_cpu(powerplay_table->usVddciLookupTableOffset));
1112 result = get_vddc_lookup_table(hwmgr,
1113 &pp_table_info->vddci_lookup_table, vddci_table, 4);
1114 }
1115
1116 return result;
1117}
1118
1119int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
1120{
1121 int result = 0;
1122 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
1123
1124 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL);
1125
1126 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
1127 "Failed to allocate hwmgr->pptable!", return -ENOMEM);
1128
1129 powerplay_table = get_powerplay_table(hwmgr);
1130
1131 PP_ASSERT_WITH_CODE((powerplay_table != NULL),
1132 "Missing PowerPlay Table!", return -1);
1133
1134 result = check_powerplay_tables(hwmgr, powerplay_table);
1135
1136 PP_ASSERT_WITH_CODE((result == 0),
1137 "check_powerplay_tables failed", return result);
1138
1139 result = set_platform_caps(hwmgr,
1140 le32_to_cpu(powerplay_table->ulPlatformCaps));
1141
1142 PP_ASSERT_WITH_CODE((result == 0),
1143 "set_platform_caps failed", return result);
1144
1145 result = init_thermal_controller(hwmgr, powerplay_table);
1146
1147 PP_ASSERT_WITH_CODE((result == 0),
1148 "init_thermal_controller failed", return result);
1149
1150 result = init_over_drive_limits(hwmgr, powerplay_table);
1151
1152 PP_ASSERT_WITH_CODE((result == 0),
1153 "init_over_drive_limits failed", return result);
1154
1155 result = init_powerplay_extended_tables(hwmgr, powerplay_table);
1156
1157 PP_ASSERT_WITH_CODE((result == 0),
1158 "init_powerplay_extended_tables failed", return result);
1159
1160 result = init_dpm_2_parameters(hwmgr, powerplay_table);
1161
1162 PP_ASSERT_WITH_CODE((result == 0),
1163 "init_dpm_2_parameters failed", return result);
1164
1165 return result;
1166}
1167
1168static int vega10_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
1169{
1170 struct phm_ppt_v2_information *pp_table_info =
1171 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1172
1173 kfree(pp_table_info->vdd_dep_on_sclk);
1174 pp_table_info->vdd_dep_on_sclk = NULL;
1175
1176 kfree(pp_table_info->vdd_dep_on_mclk);
1177 pp_table_info->vdd_dep_on_mclk = NULL;
1178
1179 kfree(pp_table_info->valid_mclk_values);
1180 pp_table_info->valid_mclk_values = NULL;
1181
1182 kfree(pp_table_info->valid_sclk_values);
1183 pp_table_info->valid_sclk_values = NULL;
1184
1185 kfree(pp_table_info->vddc_lookup_table);
1186 pp_table_info->vddc_lookup_table = NULL;
1187
1188 kfree(pp_table_info->vddmem_lookup_table);
1189 pp_table_info->vddmem_lookup_table = NULL;
1190
1191 kfree(pp_table_info->vddci_lookup_table);
1192 pp_table_info->vddci_lookup_table = NULL;
1193
1194 kfree(pp_table_info->ppm_parameter_table);
1195 pp_table_info->ppm_parameter_table = NULL;
1196
1197 kfree(pp_table_info->mm_dep_table);
1198 pp_table_info->mm_dep_table = NULL;
1199
1200 kfree(pp_table_info->cac_dtp_table);
1201 pp_table_info->cac_dtp_table = NULL;
1202
1203 kfree(hwmgr->dyn_state.cac_dtp_table);
1204 hwmgr->dyn_state.cac_dtp_table = NULL;
1205
1206 kfree(pp_table_info->tdp_table);
1207 pp_table_info->tdp_table = NULL;
1208
1209 kfree(hwmgr->pptable);
1210 hwmgr->pptable = NULL;
1211
1212 return 0;
1213}
1214
1215const struct pp_table_func vega10_pptable_funcs = {
1216 .pptable_init = vega10_pp_tables_initialize,
1217 .pptable_fini = vega10_pp_tables_uninitialize,
1218};
1219
1220int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
1221{
1222 const ATOM_Vega10_State_Array *state_arrays;
1223 const ATOM_Vega10_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
1224
1225 PP_ASSERT_WITH_CODE((pp_table != NULL),
1226 "Missing PowerPlay Table!", return -1);
1227 PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >=
1228 ATOM_Vega10_TABLE_REVISION_VEGA10),
1229 "Incorrect PowerPlay table revision!", return -1);
1230
1231 state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)pp_table) +
1232 le16_to_cpu(pp_table->usStateArrayOffset));
1233
1234 return (uint32_t)(state_arrays->ucNumEntries);
1235}
1236
1237static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
1238 uint16_t classification, uint16_t classification2)
1239{
1240 uint32_t result = 0;
1241
1242 if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
1243 result |= PP_StateClassificationFlag_Boot;
1244
1245 if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1246 result |= PP_StateClassificationFlag_Thermal;
1247
1248 if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
1249 result |= PP_StateClassificationFlag_LimitedPowerSource;
1250
1251 if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
1252 result |= PP_StateClassificationFlag_Rest;
1253
1254 if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
1255 result |= PP_StateClassificationFlag_Forced;
1256
1257 if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
1258 result |= PP_StateClassificationFlag_ACPI;
1259
1260 if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
1261 result |= PP_StateClassificationFlag_LimitedPowerSource_2;
1262
1263 return result;
1264}
1265
1266int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
1267 uint32_t entry_index, struct pp_power_state *power_state,
1268 int (*call_back_func)(struct pp_hwmgr *, void *,
1269 struct pp_power_state *, void *, uint32_t))
1270{
1271 int result = 0;
1272 const ATOM_Vega10_State_Array *state_arrays;
1273 const ATOM_Vega10_State *state_entry;
1274 const ATOM_Vega10_POWERPLAYTABLE *pp_table =
1275 get_powerplay_table(hwmgr);
1276
1277 PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
1278 return -1;);
1279 power_state->classification.bios_index = entry_index;
1280
1281 if (pp_table->sHeader.format_revision >=
1282 ATOM_Vega10_TABLE_REVISION_VEGA10) {
1283 state_arrays = (ATOM_Vega10_State_Array *)
1284 (((unsigned long)pp_table) +
1285 le16_to_cpu(pp_table->usStateArrayOffset));
1286
1287 PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
1288 "Invalid PowerPlay Table State Array Offset.",
1289 return -1);
1290 PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
1291 "Invalid PowerPlay Table State Array.",
1292 return -1);
1293 PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
1294 "Invalid PowerPlay Table State Array Entry.",
1295 return -1);
1296
1297 state_entry = &(state_arrays->states[entry_index]);
1298
1299 result = call_back_func(hwmgr, (void *)state_entry, power_state,
1300 (void *)pp_table,
1301 make_classification_flags(hwmgr,
1302 le16_to_cpu(state_entry->usClassification),
1303 le16_to_cpu(state_entry->usClassification2)));
1304 }
1305
1306 if (!result && (power_state->classification.flags &
1307 PP_StateClassificationFlag_Boot))
1308 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
1309
1310 return result;
1311}