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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/firmware.h>
24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/reboot.h>
27
28#define SMU_11_0_PARTIAL_PPTABLE
29#define SWSMU_CODE_LAYER_L3
30
31#include "amdgpu.h"
32#include "amdgpu_smu.h"
33#include "atomfirmware.h"
34#include "amdgpu_atomfirmware.h"
35#include "amdgpu_atombios.h"
36#include "smu_v11_0.h"
37#include "soc15_common.h"
38#include "atom.h"
39#include "amdgpu_ras.h"
40#include "smu_cmn.h"
41
42#include "asic_reg/thm/thm_11_0_2_offset.h"
43#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44#include "asic_reg/mp/mp_11_0_offset.h"
45#include "asic_reg/mp/mp_11_0_sh_mask.h"
46#include "asic_reg/smuio/smuio_11_0_0_offset.h"
47#include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
48
49/*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54#undef pr_err
55#undef pr_warn
56#undef pr_info
57#undef pr_debug
58
59MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
66MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
67
68#define SMU11_VOLTAGE_SCALE 4
69
70#define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
71
72#define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
73#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
74#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
75#define smnPCIE_LC_SPEED_CNTL 0x11140290
76#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
77#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
78
79#define mmTHM_BACO_CNTL_ARCT 0xA7
80#define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
81
82int smu_v11_0_init_microcode(struct smu_context *smu)
83{
84 struct amdgpu_device *adev = smu->adev;
85 const char *chip_name;
86 char fw_name[SMU_FW_NAME_LEN];
87 int err = 0;
88 const struct smc_firmware_header_v1_0 *hdr;
89 const struct common_firmware_header *header;
90 struct amdgpu_firmware_info *ucode = NULL;
91
92 if (amdgpu_sriov_vf(adev) &&
93 ((adev->asic_type == CHIP_NAVI12) ||
94 (adev->asic_type == CHIP_SIENNA_CICHLID)))
95 return 0;
96
97 switch (adev->asic_type) {
98 case CHIP_ARCTURUS:
99 chip_name = "arcturus";
100 break;
101 case CHIP_NAVI10:
102 chip_name = "navi10";
103 break;
104 case CHIP_NAVI14:
105 chip_name = "navi14";
106 break;
107 case CHIP_NAVI12:
108 chip_name = "navi12";
109 break;
110 case CHIP_SIENNA_CICHLID:
111 chip_name = "sienna_cichlid";
112 break;
113 case CHIP_NAVY_FLOUNDER:
114 chip_name = "navy_flounder";
115 break;
116 case CHIP_DIMGREY_CAVEFISH:
117 chip_name = "dimgrey_cavefish";
118 break;
119 case CHIP_BEIGE_GOBY:
120 chip_name = "beige_goby";
121 break;
122 default:
123 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
124 return -EINVAL;
125 }
126
127 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
128
129 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
130 if (err)
131 goto out;
132 err = amdgpu_ucode_validate(adev->pm.fw);
133 if (err)
134 goto out;
135
136 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
137 amdgpu_ucode_print_smc_hdr(&hdr->header);
138 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
139
140 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
141 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
142 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
143 ucode->fw = adev->pm.fw;
144 header = (const struct common_firmware_header *)ucode->fw->data;
145 adev->firmware.fw_size +=
146 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
147 }
148
149out:
150 if (err) {
151 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
152 fw_name);
153 release_firmware(adev->pm.fw);
154 adev->pm.fw = NULL;
155 }
156 return err;
157}
158
159void smu_v11_0_fini_microcode(struct smu_context *smu)
160{
161 struct amdgpu_device *adev = smu->adev;
162
163 release_firmware(adev->pm.fw);
164 adev->pm.fw = NULL;
165 adev->pm.fw_version = 0;
166}
167
168int smu_v11_0_load_microcode(struct smu_context *smu)
169{
170 struct amdgpu_device *adev = smu->adev;
171 const uint32_t *src;
172 const struct smc_firmware_header_v1_0 *hdr;
173 uint32_t addr_start = MP1_SRAM;
174 uint32_t i;
175 uint32_t smc_fw_size;
176 uint32_t mp1_fw_flags;
177
178 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
179 src = (const uint32_t *)(adev->pm.fw->data +
180 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
181 smc_fw_size = hdr->header.ucode_size_bytes;
182
183 for (i = 1; i < smc_fw_size/4 - 1; i++) {
184 WREG32_PCIE(addr_start, src[i]);
185 addr_start += 4;
186 }
187
188 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
189 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
190 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
191 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
192
193 for (i = 0; i < adev->usec_timeout; i++) {
194 mp1_fw_flags = RREG32_PCIE(MP1_Public |
195 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
196 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
197 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
198 break;
199 udelay(1);
200 }
201
202 if (i == adev->usec_timeout)
203 return -ETIME;
204
205 return 0;
206}
207
208int smu_v11_0_check_fw_status(struct smu_context *smu)
209{
210 struct amdgpu_device *adev = smu->adev;
211 uint32_t mp1_fw_flags;
212
213 mp1_fw_flags = RREG32_PCIE(MP1_Public |
214 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
215
216 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
217 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
218 return 0;
219
220 return -EIO;
221}
222
223int smu_v11_0_check_fw_version(struct smu_context *smu)
224{
225 struct amdgpu_device *adev = smu->adev;
226 uint32_t if_version = 0xff, smu_version = 0xff;
227 uint16_t smu_major;
228 uint8_t smu_minor, smu_debug;
229 int ret = 0;
230
231 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
232 if (ret)
233 return ret;
234
235 smu_major = (smu_version >> 16) & 0xffff;
236 smu_minor = (smu_version >> 8) & 0xff;
237 smu_debug = (smu_version >> 0) & 0xff;
238 if (smu->is_apu)
239 adev->pm.fw_version = smu_version;
240
241 switch (smu->adev->asic_type) {
242 case CHIP_ARCTURUS:
243 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
244 break;
245 case CHIP_NAVI10:
246 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
247 break;
248 case CHIP_NAVI12:
249 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
250 break;
251 case CHIP_NAVI14:
252 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
253 break;
254 case CHIP_SIENNA_CICHLID:
255 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
256 break;
257 case CHIP_NAVY_FLOUNDER:
258 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
259 break;
260 case CHIP_VANGOGH:
261 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
262 break;
263 case CHIP_DIMGREY_CAVEFISH:
264 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
265 break;
266 case CHIP_BEIGE_GOBY:
267 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
268 break;
269 default:
270 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
271 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
272 break;
273 }
274
275 /*
276 * 1. if_version mismatch is not critical as our fw is designed
277 * to be backward compatible.
278 * 2. New fw usually brings some optimizations. But that's visible
279 * only on the paired driver.
280 * Considering above, we just leave user a warning message instead
281 * of halt driver loading.
282 */
283 if (if_version != smu->smc_driver_if_version) {
284 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
285 "smu fw version = 0x%08x (%d.%d.%d)\n",
286 smu->smc_driver_if_version, if_version,
287 smu_version, smu_major, smu_minor, smu_debug);
288 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
289 }
290
291 return ret;
292}
293
294static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
295{
296 struct amdgpu_device *adev = smu->adev;
297 uint32_t ppt_offset_bytes;
298 const struct smc_firmware_header_v2_0 *v2;
299
300 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
301
302 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
303 *size = le32_to_cpu(v2->ppt_size_bytes);
304 *table = (uint8_t *)v2 + ppt_offset_bytes;
305
306 return 0;
307}
308
309static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
310 uint32_t *size, uint32_t pptable_id)
311{
312 struct amdgpu_device *adev = smu->adev;
313 const struct smc_firmware_header_v2_1 *v2_1;
314 struct smc_soft_pptable_entry *entries;
315 uint32_t pptable_count = 0;
316 int i = 0;
317
318 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
319 entries = (struct smc_soft_pptable_entry *)
320 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
321 pptable_count = le32_to_cpu(v2_1->pptable_count);
322 for (i = 0; i < pptable_count; i++) {
323 if (le32_to_cpu(entries[i].id) == pptable_id) {
324 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
325 *size = le32_to_cpu(entries[i].ppt_size_bytes);
326 break;
327 }
328 }
329
330 if (i == pptable_count)
331 return -EINVAL;
332
333 return 0;
334}
335
336int smu_v11_0_setup_pptable(struct smu_context *smu)
337{
338 struct amdgpu_device *adev = smu->adev;
339 const struct smc_firmware_header_v1_0 *hdr;
340 int ret, index;
341 uint32_t size = 0;
342 uint16_t atom_table_size;
343 uint8_t frev, crev;
344 void *table;
345 uint16_t version_major, version_minor;
346
347 if (!amdgpu_sriov_vf(adev)) {
348 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
349 version_major = le16_to_cpu(hdr->header.header_version_major);
350 version_minor = le16_to_cpu(hdr->header.header_version_minor);
351 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
352 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
353 switch (version_minor) {
354 case 0:
355 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
356 break;
357 case 1:
358 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
359 smu->smu_table.boot_values.pp_table_id);
360 break;
361 default:
362 ret = -EINVAL;
363 break;
364 }
365 if (ret)
366 return ret;
367 goto out;
368 }
369 }
370
371 dev_info(adev->dev, "use vbios provided pptable\n");
372 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
373 powerplayinfo);
374
375 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
376 (uint8_t **)&table);
377 if (ret)
378 return ret;
379 size = atom_table_size;
380
381out:
382 if (!smu->smu_table.power_play_table)
383 smu->smu_table.power_play_table = table;
384 if (!smu->smu_table.power_play_table_size)
385 smu->smu_table.power_play_table_size = size;
386
387 return 0;
388}
389
390int smu_v11_0_init_smc_tables(struct smu_context *smu)
391{
392 struct smu_table_context *smu_table = &smu->smu_table;
393 struct smu_table *tables = smu_table->tables;
394 int ret = 0;
395
396 smu_table->driver_pptable =
397 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
398 if (!smu_table->driver_pptable) {
399 ret = -ENOMEM;
400 goto err0_out;
401 }
402
403 smu_table->max_sustainable_clocks =
404 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
405 if (!smu_table->max_sustainable_clocks) {
406 ret = -ENOMEM;
407 goto err1_out;
408 }
409
410 /* Arcturus does not support OVERDRIVE */
411 if (tables[SMU_TABLE_OVERDRIVE].size) {
412 smu_table->overdrive_table =
413 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
414 if (!smu_table->overdrive_table) {
415 ret = -ENOMEM;
416 goto err2_out;
417 }
418
419 smu_table->boot_overdrive_table =
420 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
421 if (!smu_table->boot_overdrive_table) {
422 ret = -ENOMEM;
423 goto err3_out;
424 }
425 }
426
427 return 0;
428
429err3_out:
430 kfree(smu_table->overdrive_table);
431err2_out:
432 kfree(smu_table->max_sustainable_clocks);
433err1_out:
434 kfree(smu_table->driver_pptable);
435err0_out:
436 return ret;
437}
438
439int smu_v11_0_fini_smc_tables(struct smu_context *smu)
440{
441 struct smu_table_context *smu_table = &smu->smu_table;
442 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
443
444 kfree(smu_table->gpu_metrics_table);
445 kfree(smu_table->boot_overdrive_table);
446 kfree(smu_table->overdrive_table);
447 kfree(smu_table->max_sustainable_clocks);
448 kfree(smu_table->driver_pptable);
449 kfree(smu_table->clocks_table);
450 smu_table->gpu_metrics_table = NULL;
451 smu_table->boot_overdrive_table = NULL;
452 smu_table->overdrive_table = NULL;
453 smu_table->max_sustainable_clocks = NULL;
454 smu_table->driver_pptable = NULL;
455 smu_table->clocks_table = NULL;
456 kfree(smu_table->hardcode_pptable);
457 smu_table->hardcode_pptable = NULL;
458
459 kfree(smu_table->metrics_table);
460 kfree(smu_table->watermarks_table);
461 smu_table->metrics_table = NULL;
462 smu_table->watermarks_table = NULL;
463 smu_table->metrics_time = 0;
464
465 kfree(smu_dpm->dpm_context);
466 kfree(smu_dpm->golden_dpm_context);
467 kfree(smu_dpm->dpm_current_power_state);
468 kfree(smu_dpm->dpm_request_power_state);
469 smu_dpm->dpm_context = NULL;
470 smu_dpm->golden_dpm_context = NULL;
471 smu_dpm->dpm_context_size = 0;
472 smu_dpm->dpm_current_power_state = NULL;
473 smu_dpm->dpm_request_power_state = NULL;
474
475 return 0;
476}
477
478int smu_v11_0_init_power(struct smu_context *smu)
479{
480 struct smu_power_context *smu_power = &smu->smu_power;
481 size_t size = smu->adev->asic_type == CHIP_VANGOGH ?
482 sizeof(struct smu_11_5_power_context) :
483 sizeof(struct smu_11_0_power_context);
484
485 smu_power->power_context = kzalloc(size, GFP_KERNEL);
486 if (!smu_power->power_context)
487 return -ENOMEM;
488 smu_power->power_context_size = size;
489
490 return 0;
491}
492
493int smu_v11_0_fini_power(struct smu_context *smu)
494{
495 struct smu_power_context *smu_power = &smu->smu_power;
496
497 kfree(smu_power->power_context);
498 smu_power->power_context = NULL;
499 smu_power->power_context_size = 0;
500
501 return 0;
502}
503
504static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
505 uint8_t clk_id,
506 uint8_t syspll_id,
507 uint32_t *clk_freq)
508{
509 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
510 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
511 int ret, index;
512
513 input.clk_id = clk_id;
514 input.syspll_id = syspll_id;
515 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
516 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
517 getsmuclockinfo);
518
519 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
520 (uint32_t *)&input);
521 if (ret)
522 return -EINVAL;
523
524 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
525 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
526
527 return 0;
528}
529
530int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
531{
532 int ret, index;
533 uint16_t size;
534 uint8_t frev, crev;
535 struct atom_common_table_header *header;
536 struct atom_firmware_info_v3_3 *v_3_3;
537 struct atom_firmware_info_v3_1 *v_3_1;
538
539 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
540 firmwareinfo);
541
542 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
543 (uint8_t **)&header);
544 if (ret)
545 return ret;
546
547 if (header->format_revision != 3) {
548 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
549 return -EINVAL;
550 }
551
552 switch (header->content_revision) {
553 case 0:
554 case 1:
555 case 2:
556 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
557 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
558 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
559 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
560 smu->smu_table.boot_values.socclk = 0;
561 smu->smu_table.boot_values.dcefclk = 0;
562 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
563 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
564 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
565 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
566 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
567 smu->smu_table.boot_values.pp_table_id = 0;
568 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
569 break;
570 case 3:
571 case 4:
572 default:
573 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
574 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
575 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
576 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
577 smu->smu_table.boot_values.socclk = 0;
578 smu->smu_table.boot_values.dcefclk = 0;
579 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
580 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
581 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
582 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
583 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
584 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
585 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
586 }
587
588 smu->smu_table.boot_values.format_revision = header->format_revision;
589 smu->smu_table.boot_values.content_revision = header->content_revision;
590
591 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
592 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
593 (uint8_t)0,
594 &smu->smu_table.boot_values.socclk);
595
596 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
597 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
598 (uint8_t)0,
599 &smu->smu_table.boot_values.dcefclk);
600
601 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
602 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
603 (uint8_t)0,
604 &smu->smu_table.boot_values.eclk);
605
606 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
607 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
608 (uint8_t)0,
609 &smu->smu_table.boot_values.vclk);
610
611 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
612 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
613 (uint8_t)0,
614 &smu->smu_table.boot_values.dclk);
615
616 if ((smu->smu_table.boot_values.format_revision == 3) &&
617 (smu->smu_table.boot_values.content_revision >= 2))
618 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
619 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
620 (uint8_t)SMU11_SYSPLL1_2_ID,
621 &smu->smu_table.boot_values.fclk);
622
623 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
624 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
625 (uint8_t)SMU11_SYSPLL3_1_ID,
626 &smu->smu_table.boot_values.lclk);
627
628 return 0;
629}
630
631int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
632{
633 struct smu_table_context *smu_table = &smu->smu_table;
634 struct smu_table *memory_pool = &smu_table->memory_pool;
635 int ret = 0;
636 uint64_t address;
637 uint32_t address_low, address_high;
638
639 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
640 return ret;
641
642 address = (uintptr_t)memory_pool->cpu_addr;
643 address_high = (uint32_t)upper_32_bits(address);
644 address_low = (uint32_t)lower_32_bits(address);
645
646 ret = smu_cmn_send_smc_msg_with_param(smu,
647 SMU_MSG_SetSystemVirtualDramAddrHigh,
648 address_high,
649 NULL);
650 if (ret)
651 return ret;
652 ret = smu_cmn_send_smc_msg_with_param(smu,
653 SMU_MSG_SetSystemVirtualDramAddrLow,
654 address_low,
655 NULL);
656 if (ret)
657 return ret;
658
659 address = memory_pool->mc_address;
660 address_high = (uint32_t)upper_32_bits(address);
661 address_low = (uint32_t)lower_32_bits(address);
662
663 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
664 address_high, NULL);
665 if (ret)
666 return ret;
667 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
668 address_low, NULL);
669 if (ret)
670 return ret;
671 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
672 (uint32_t)memory_pool->size, NULL);
673 if (ret)
674 return ret;
675
676 return ret;
677}
678
679int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
680{
681 int ret;
682
683 ret = smu_cmn_send_smc_msg_with_param(smu,
684 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
685 if (ret)
686 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
687
688 return ret;
689}
690
691int smu_v11_0_set_driver_table_location(struct smu_context *smu)
692{
693 struct smu_table *driver_table = &smu->smu_table.driver_table;
694 int ret = 0;
695
696 if (driver_table->mc_address) {
697 ret = smu_cmn_send_smc_msg_with_param(smu,
698 SMU_MSG_SetDriverDramAddrHigh,
699 upper_32_bits(driver_table->mc_address),
700 NULL);
701 if (!ret)
702 ret = smu_cmn_send_smc_msg_with_param(smu,
703 SMU_MSG_SetDriverDramAddrLow,
704 lower_32_bits(driver_table->mc_address),
705 NULL);
706 }
707
708 return ret;
709}
710
711int smu_v11_0_set_tool_table_location(struct smu_context *smu)
712{
713 int ret = 0;
714 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
715
716 if (tool_table->mc_address) {
717 ret = smu_cmn_send_smc_msg_with_param(smu,
718 SMU_MSG_SetToolsDramAddrHigh,
719 upper_32_bits(tool_table->mc_address),
720 NULL);
721 if (!ret)
722 ret = smu_cmn_send_smc_msg_with_param(smu,
723 SMU_MSG_SetToolsDramAddrLow,
724 lower_32_bits(tool_table->mc_address),
725 NULL);
726 }
727
728 return ret;
729}
730
731int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
732{
733 struct amdgpu_device *adev = smu->adev;
734
735 /* Navy_Flounder/Dimgrey_Cavefish do not support to change
736 * display num currently
737 */
738 if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
739 adev->asic_type <= CHIP_BEIGE_GOBY)
740 return 0;
741
742 return smu_cmn_send_smc_msg_with_param(smu,
743 SMU_MSG_NumOfDisplays,
744 count,
745 NULL);
746}
747
748
749int smu_v11_0_set_allowed_mask(struct smu_context *smu)
750{
751 struct smu_feature *feature = &smu->smu_feature;
752 int ret = 0;
753 uint32_t feature_mask[2];
754
755 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) {
756 ret = -EINVAL;
757 goto failed;
758 }
759
760 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
761
762 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
763 feature_mask[1], NULL);
764 if (ret)
765 goto failed;
766
767 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
768 feature_mask[0], NULL);
769 if (ret)
770 goto failed;
771
772failed:
773 return ret;
774}
775
776int smu_v11_0_system_features_control(struct smu_context *smu,
777 bool en)
778{
779 struct smu_feature *feature = &smu->smu_feature;
780 uint32_t feature_mask[2];
781 int ret = 0;
782
783 ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
784 SMU_MSG_DisableAllSmuFeatures), NULL);
785 if (ret)
786 return ret;
787
788 bitmap_zero(feature->enabled, feature->feature_num);
789 bitmap_zero(feature->supported, feature->feature_num);
790
791 if (en) {
792 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
793 if (ret)
794 return ret;
795
796 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
797 feature->feature_num);
798 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
799 feature->feature_num);
800 }
801
802 return ret;
803}
804
805int smu_v11_0_notify_display_change(struct smu_context *smu)
806{
807 int ret = 0;
808
809 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
810 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
811 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
812
813 return ret;
814}
815
816static int
817smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
818 enum smu_clk_type clock_select)
819{
820 int ret = 0;
821 int clk_id;
822
823 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
824 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
825 return 0;
826
827 clk_id = smu_cmn_to_asic_specific_index(smu,
828 CMN2ASIC_MAPPING_CLK,
829 clock_select);
830 if (clk_id < 0)
831 return -EINVAL;
832
833 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
834 clk_id << 16, clock);
835 if (ret) {
836 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
837 return ret;
838 }
839
840 if (*clock != 0)
841 return 0;
842
843 /* if DC limit is zero, return AC limit */
844 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
845 clk_id << 16, clock);
846 if (ret) {
847 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
848 return ret;
849 }
850
851 return 0;
852}
853
854int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
855{
856 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
857 smu->smu_table.max_sustainable_clocks;
858 int ret = 0;
859
860 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
861 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
862 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
863 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
864 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
865 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
866
867 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
868 ret = smu_v11_0_get_max_sustainable_clock(smu,
869 &(max_sustainable_clocks->uclock),
870 SMU_UCLK);
871 if (ret) {
872 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
873 __func__);
874 return ret;
875 }
876 }
877
878 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
879 ret = smu_v11_0_get_max_sustainable_clock(smu,
880 &(max_sustainable_clocks->soc_clock),
881 SMU_SOCCLK);
882 if (ret) {
883 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
884 __func__);
885 return ret;
886 }
887 }
888
889 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
890 ret = smu_v11_0_get_max_sustainable_clock(smu,
891 &(max_sustainable_clocks->dcef_clock),
892 SMU_DCEFCLK);
893 if (ret) {
894 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
895 __func__);
896 return ret;
897 }
898
899 ret = smu_v11_0_get_max_sustainable_clock(smu,
900 &(max_sustainable_clocks->display_clock),
901 SMU_DISPCLK);
902 if (ret) {
903 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
904 __func__);
905 return ret;
906 }
907 ret = smu_v11_0_get_max_sustainable_clock(smu,
908 &(max_sustainable_clocks->phy_clock),
909 SMU_PHYCLK);
910 if (ret) {
911 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
912 __func__);
913 return ret;
914 }
915 ret = smu_v11_0_get_max_sustainable_clock(smu,
916 &(max_sustainable_clocks->pixel_clock),
917 SMU_PIXCLK);
918 if (ret) {
919 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
920 __func__);
921 return ret;
922 }
923 }
924
925 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
926 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
927
928 return 0;
929}
930
931int smu_v11_0_get_current_power_limit(struct smu_context *smu,
932 uint32_t *power_limit)
933{
934 int power_src;
935 int ret = 0;
936
937 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
938 return -EINVAL;
939
940 power_src = smu_cmn_to_asic_specific_index(smu,
941 CMN2ASIC_MAPPING_PWR,
942 smu->adev->pm.ac_power ?
943 SMU_POWER_SOURCE_AC :
944 SMU_POWER_SOURCE_DC);
945 if (power_src < 0)
946 return -EINVAL;
947
948 /*
949 * BIT 24-31: ControllerId (only PPT0 is supported for now)
950 * BIT 16-23: PowerSource
951 */
952 ret = smu_cmn_send_smc_msg_with_param(smu,
953 SMU_MSG_GetPptLimit,
954 (0 << 24) | (power_src << 16),
955 power_limit);
956 if (ret)
957 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
958
959 return ret;
960}
961
962int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
963{
964 int power_src;
965 int ret = 0;
966
967 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
968 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
969 return -EOPNOTSUPP;
970 }
971
972 power_src = smu_cmn_to_asic_specific_index(smu,
973 CMN2ASIC_MAPPING_PWR,
974 smu->adev->pm.ac_power ?
975 SMU_POWER_SOURCE_AC :
976 SMU_POWER_SOURCE_DC);
977 if (power_src < 0)
978 return -EINVAL;
979
980 /*
981 * BIT 24-31: ControllerId (only PPT0 is supported for now)
982 * BIT 16-23: PowerSource
983 * BIT 0-15: PowerLimit
984 */
985 n &= 0xFFFF;
986 n |= 0 << 24;
987 n |= (power_src) << 16;
988 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
989 if (ret) {
990 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
991 return ret;
992 }
993
994 smu->current_power_limit = n;
995
996 return 0;
997}
998
999static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
1000{
1001 return smu_cmn_send_smc_msg(smu,
1002 SMU_MSG_ReenableAcDcInterrupt,
1003 NULL);
1004}
1005
1006static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
1007{
1008 int ret = 0;
1009
1010 if (smu->dc_controlled_by_gpio &&
1011 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1012 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
1013
1014 return ret;
1015}
1016
1017void smu_v11_0_interrupt_work(struct smu_context *smu)
1018{
1019 if (smu_v11_0_ack_ac_dc_interrupt(smu))
1020 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
1021}
1022
1023int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1024{
1025 int ret = 0;
1026
1027 if (smu->smu_table.thermal_controller_type) {
1028 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1029 if (ret)
1030 return ret;
1031 }
1032
1033 /*
1034 * After init there might have been missed interrupts triggered
1035 * before driver registers for interrupt (Ex. AC/DC).
1036 */
1037 return smu_v11_0_process_pending_interrupt(smu);
1038}
1039
1040int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1041{
1042 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1043}
1044
1045static uint16_t convert_to_vddc(uint8_t vid)
1046{
1047 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1048}
1049
1050int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1051{
1052 struct amdgpu_device *adev = smu->adev;
1053 uint32_t vdd = 0, val_vid = 0;
1054
1055 if (!value)
1056 return -EINVAL;
1057 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1058 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1059 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1060
1061 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1062
1063 *value = vdd;
1064
1065 return 0;
1066
1067}
1068
1069int
1070smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1071 struct pp_display_clock_request
1072 *clock_req)
1073{
1074 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1075 int ret = 0;
1076 enum smu_clk_type clk_select = 0;
1077 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1078
1079 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1080 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1081 switch (clk_type) {
1082 case amd_pp_dcef_clock:
1083 clk_select = SMU_DCEFCLK;
1084 break;
1085 case amd_pp_disp_clock:
1086 clk_select = SMU_DISPCLK;
1087 break;
1088 case amd_pp_pixel_clock:
1089 clk_select = SMU_PIXCLK;
1090 break;
1091 case amd_pp_phy_clock:
1092 clk_select = SMU_PHYCLK;
1093 break;
1094 case amd_pp_mem_clock:
1095 clk_select = SMU_UCLK;
1096 break;
1097 default:
1098 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1099 ret = -EINVAL;
1100 break;
1101 }
1102
1103 if (ret)
1104 goto failed;
1105
1106 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1107 return 0;
1108
1109 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1110
1111 if(clk_select == SMU_UCLK)
1112 smu->hard_min_uclk_req_from_dal = clk_freq;
1113 }
1114
1115failed:
1116 return ret;
1117}
1118
1119int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1120{
1121 int ret = 0;
1122 struct amdgpu_device *adev = smu->adev;
1123
1124 switch (adev->asic_type) {
1125 case CHIP_NAVI10:
1126 case CHIP_NAVI14:
1127 case CHIP_NAVI12:
1128 case CHIP_SIENNA_CICHLID:
1129 case CHIP_NAVY_FLOUNDER:
1130 case CHIP_DIMGREY_CAVEFISH:
1131 case CHIP_BEIGE_GOBY:
1132 case CHIP_VANGOGH:
1133 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1134 return 0;
1135 if (enable)
1136 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1137 else
1138 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1139 break;
1140 default:
1141 break;
1142 }
1143
1144 return ret;
1145}
1146
1147uint32_t
1148smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1149{
1150 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1151 return AMD_FAN_CTRL_AUTO;
1152 else
1153 return smu->user_dpm_profile.fan_mode;
1154}
1155
1156static int
1157smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1158{
1159 int ret = 0;
1160
1161 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1162 return 0;
1163
1164 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1165 if (ret)
1166 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1167 __func__, (auto_fan_control ? "Start" : "Stop"));
1168
1169 return ret;
1170}
1171
1172static int
1173smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1174{
1175 struct amdgpu_device *adev = smu->adev;
1176
1177 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1178 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1179 CG_FDO_CTRL2, TMIN, 0));
1180 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1181 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1182 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1183
1184 return 0;
1185}
1186
1187int
1188smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1189{
1190 struct amdgpu_device *adev = smu->adev;
1191 uint32_t duty100, duty;
1192 uint64_t tmp64;
1193
1194 if (speed > 100)
1195 speed = 100;
1196
1197 if (smu_v11_0_auto_fan_control(smu, 0))
1198 return -EINVAL;
1199
1200 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1201 CG_FDO_CTRL1, FMAX_DUTY100);
1202 if (!duty100)
1203 return -EINVAL;
1204
1205 tmp64 = (uint64_t)speed * duty100;
1206 do_div(tmp64, 100);
1207 duty = (uint32_t)tmp64;
1208
1209 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1210 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1211 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1212
1213 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1214}
1215
1216int
1217smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1218 uint32_t mode)
1219{
1220 int ret = 0;
1221
1222 switch (mode) {
1223 case AMD_FAN_CTRL_NONE:
1224 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1225 break;
1226 case AMD_FAN_CTRL_MANUAL:
1227 ret = smu_v11_0_auto_fan_control(smu, 0);
1228 break;
1229 case AMD_FAN_CTRL_AUTO:
1230 ret = smu_v11_0_auto_fan_control(smu, 1);
1231 break;
1232 default:
1233 break;
1234 }
1235
1236 if (ret) {
1237 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1238 return -EINVAL;
1239 }
1240
1241 return ret;
1242}
1243
1244int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1245 uint32_t pstate)
1246{
1247 return smu_cmn_send_smc_msg_with_param(smu,
1248 SMU_MSG_SetXgmiMode,
1249 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1250 NULL);
1251}
1252
1253static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1254 struct amdgpu_irq_src *source,
1255 unsigned tyep,
1256 enum amdgpu_interrupt_state state)
1257{
1258 struct smu_context *smu = &adev->smu;
1259 uint32_t low, high;
1260 uint32_t val = 0;
1261
1262 switch (state) {
1263 case AMDGPU_IRQ_STATE_DISABLE:
1264 /* For THM irqs */
1265 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1266 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1267 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1268 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1269
1270 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1271
1272 /* For MP1 SW irqs */
1273 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1274 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1275 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1276
1277 break;
1278 case AMDGPU_IRQ_STATE_ENABLE:
1279 /* For THM irqs */
1280 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1281 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1282 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1283 smu->thermal_range.software_shutdown_temp);
1284
1285 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1286 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1287 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1288 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1289 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1290 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1291 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1292 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1293 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1294
1295 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1296 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1297 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1298 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1299
1300 /* For MP1 SW irqs */
1301 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1302 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1303 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1304 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1305
1306 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1307 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1308 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1309
1310 break;
1311 default:
1312 break;
1313 }
1314
1315 return 0;
1316}
1317
1318#define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1319#define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1320
1321#define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1322
1323static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1324 struct amdgpu_irq_src *source,
1325 struct amdgpu_iv_entry *entry)
1326{
1327 struct smu_context *smu = &adev->smu;
1328 uint32_t client_id = entry->client_id;
1329 uint32_t src_id = entry->src_id;
1330 /*
1331 * ctxid is used to distinguish different
1332 * events for SMCToHost interrupt.
1333 */
1334 uint32_t ctxid = entry->src_data[0];
1335 uint32_t data;
1336
1337 if (client_id == SOC15_IH_CLIENTID_THM) {
1338 switch (src_id) {
1339 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1340 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1341 /*
1342 * SW CTF just occurred.
1343 * Try to do a graceful shutdown to prevent further damage.
1344 */
1345 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1346 orderly_poweroff(true);
1347 break;
1348 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1349 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1350 break;
1351 default:
1352 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1353 src_id);
1354 break;
1355 }
1356 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1357 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1358 /*
1359 * HW CTF just occurred. Shutdown to prevent further damage.
1360 */
1361 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1362 orderly_poweroff(true);
1363 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1364 if (src_id == 0xfe) {
1365 /* ACK SMUToHost interrupt */
1366 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1367 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1368 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1369
1370 switch (ctxid) {
1371 case 0x3:
1372 dev_dbg(adev->dev, "Switched to AC mode!\n");
1373 schedule_work(&smu->interrupt_work);
1374 break;
1375 case 0x4:
1376 dev_dbg(adev->dev, "Switched to DC mode!\n");
1377 schedule_work(&smu->interrupt_work);
1378 break;
1379 case 0x7:
1380 /*
1381 * Increment the throttle interrupt counter
1382 */
1383 atomic64_inc(&smu->throttle_int_counter);
1384
1385 if (!atomic_read(&adev->throttling_logging_enabled))
1386 return 0;
1387
1388 if (__ratelimit(&adev->throttling_logging_rs))
1389 schedule_work(&smu->throttling_logging_work);
1390
1391 break;
1392 }
1393 }
1394 }
1395
1396 return 0;
1397}
1398
1399static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1400{
1401 .set = smu_v11_0_set_irq_state,
1402 .process = smu_v11_0_irq_process,
1403};
1404
1405int smu_v11_0_register_irq_handler(struct smu_context *smu)
1406{
1407 struct amdgpu_device *adev = smu->adev;
1408 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1409 int ret = 0;
1410
1411 irq_src->num_types = 1;
1412 irq_src->funcs = &smu_v11_0_irq_funcs;
1413
1414 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1415 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1416 irq_src);
1417 if (ret)
1418 return ret;
1419
1420 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1421 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1422 irq_src);
1423 if (ret)
1424 return ret;
1425
1426 /* Register CTF(GPIO_19) interrupt */
1427 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1428 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1429 irq_src);
1430 if (ret)
1431 return ret;
1432
1433 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1434 0xfe,
1435 irq_src);
1436 if (ret)
1437 return ret;
1438
1439 return ret;
1440}
1441
1442int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1443 struct pp_smu_nv_clock_table *max_clocks)
1444{
1445 struct smu_table_context *table_context = &smu->smu_table;
1446 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1447
1448 if (!max_clocks || !table_context->max_sustainable_clocks)
1449 return -EINVAL;
1450
1451 sustainable_clocks = table_context->max_sustainable_clocks;
1452
1453 max_clocks->dcfClockInKhz =
1454 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1455 max_clocks->displayClockInKhz =
1456 (unsigned int) sustainable_clocks->display_clock * 1000;
1457 max_clocks->phyClockInKhz =
1458 (unsigned int) sustainable_clocks->phy_clock * 1000;
1459 max_clocks->pixelClockInKhz =
1460 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1461 max_clocks->uClockInKhz =
1462 (unsigned int) sustainable_clocks->uclock * 1000;
1463 max_clocks->socClockInKhz =
1464 (unsigned int) sustainable_clocks->soc_clock * 1000;
1465 max_clocks->dscClockInKhz = 0;
1466 max_clocks->dppClockInKhz = 0;
1467 max_clocks->fabricClockInKhz = 0;
1468
1469 return 0;
1470}
1471
1472int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1473{
1474 return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1475}
1476
1477int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
1478 enum smu_v11_0_baco_seq baco_seq)
1479{
1480 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1481}
1482
1483bool smu_v11_0_baco_is_support(struct smu_context *smu)
1484{
1485 struct smu_baco_context *smu_baco = &smu->smu_baco;
1486
1487 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
1488 return false;
1489
1490 /* Arcturus does not support this bit mask */
1491 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1492 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1493 return false;
1494
1495 return true;
1496}
1497
1498enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1499{
1500 struct smu_baco_context *smu_baco = &smu->smu_baco;
1501 enum smu_baco_state baco_state;
1502
1503 mutex_lock(&smu_baco->mutex);
1504 baco_state = smu_baco->state;
1505 mutex_unlock(&smu_baco->mutex);
1506
1507 return baco_state;
1508}
1509
1510#define D3HOT_BACO_SEQUENCE 0
1511#define D3HOT_BAMACO_SEQUENCE 2
1512
1513int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1514{
1515 struct smu_baco_context *smu_baco = &smu->smu_baco;
1516 struct amdgpu_device *adev = smu->adev;
1517 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1518 uint32_t data;
1519 int ret = 0;
1520
1521 if (smu_v11_0_baco_get_state(smu) == state)
1522 return 0;
1523
1524 mutex_lock(&smu_baco->mutex);
1525
1526 if (state == SMU_BACO_STATE_ENTER) {
1527 switch (adev->asic_type) {
1528 case CHIP_SIENNA_CICHLID:
1529 case CHIP_NAVY_FLOUNDER:
1530 case CHIP_DIMGREY_CAVEFISH:
1531 case CHIP_BEIGE_GOBY:
1532 if (amdgpu_runtime_pm == 2)
1533 ret = smu_cmn_send_smc_msg_with_param(smu,
1534 SMU_MSG_EnterBaco,
1535 D3HOT_BAMACO_SEQUENCE,
1536 NULL);
1537 else
1538 ret = smu_cmn_send_smc_msg_with_param(smu,
1539 SMU_MSG_EnterBaco,
1540 D3HOT_BACO_SEQUENCE,
1541 NULL);
1542 break;
1543 default:
1544 if (!ras || !adev->ras_enabled ||
1545 adev->gmc.xgmi.pending_reset) {
1546 if (adev->asic_type == CHIP_ARCTURUS) {
1547 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
1548 data |= 0x80000000;
1549 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
1550 } else {
1551 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1552 data |= 0x80000000;
1553 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1554 }
1555
1556 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1557 } else {
1558 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1559 }
1560 break;
1561 }
1562
1563 } else {
1564 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1565 if (ret)
1566 goto out;
1567
1568 /* clear vbios scratch 6 and 7 for coming asic reinit */
1569 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1570 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1571 }
1572 if (ret)
1573 goto out;
1574
1575 smu_baco->state = state;
1576out:
1577 mutex_unlock(&smu_baco->mutex);
1578 return ret;
1579}
1580
1581int smu_v11_0_baco_enter(struct smu_context *smu)
1582{
1583 int ret = 0;
1584
1585 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1586 if (ret)
1587 return ret;
1588
1589 msleep(10);
1590
1591 return ret;
1592}
1593
1594int smu_v11_0_baco_exit(struct smu_context *smu)
1595{
1596 return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1597}
1598
1599int smu_v11_0_mode1_reset(struct smu_context *smu)
1600{
1601 int ret = 0;
1602
1603 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1604 if (!ret)
1605 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1606
1607 return ret;
1608}
1609
1610int smu_v11_0_set_light_sbr(struct smu_context *smu, bool enable)
1611{
1612 int ret = 0;
1613
1614 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL);
1615
1616 return ret;
1617}
1618
1619
1620int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1621 uint32_t *min, uint32_t *max)
1622{
1623 int ret = 0, clk_id = 0;
1624 uint32_t param = 0;
1625 uint32_t clock_limit;
1626
1627 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1628 switch (clk_type) {
1629 case SMU_MCLK:
1630 case SMU_UCLK:
1631 clock_limit = smu->smu_table.boot_values.uclk;
1632 break;
1633 case SMU_GFXCLK:
1634 case SMU_SCLK:
1635 clock_limit = smu->smu_table.boot_values.gfxclk;
1636 break;
1637 case SMU_SOCCLK:
1638 clock_limit = smu->smu_table.boot_values.socclk;
1639 break;
1640 default:
1641 clock_limit = 0;
1642 break;
1643 }
1644
1645 /* clock in Mhz unit */
1646 if (min)
1647 *min = clock_limit / 100;
1648 if (max)
1649 *max = clock_limit / 100;
1650
1651 return 0;
1652 }
1653
1654 clk_id = smu_cmn_to_asic_specific_index(smu,
1655 CMN2ASIC_MAPPING_CLK,
1656 clk_type);
1657 if (clk_id < 0) {
1658 ret = -EINVAL;
1659 goto failed;
1660 }
1661 param = (clk_id & 0xffff) << 16;
1662
1663 if (max) {
1664 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1665 if (ret)
1666 goto failed;
1667 }
1668
1669 if (min) {
1670 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1671 if (ret)
1672 goto failed;
1673 }
1674
1675failed:
1676 return ret;
1677}
1678
1679int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1680 enum smu_clk_type clk_type,
1681 uint32_t min,
1682 uint32_t max)
1683{
1684 struct amdgpu_device *adev = smu->adev;
1685 int ret = 0, clk_id = 0;
1686 uint32_t param;
1687
1688 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1689 return 0;
1690
1691 clk_id = smu_cmn_to_asic_specific_index(smu,
1692 CMN2ASIC_MAPPING_CLK,
1693 clk_type);
1694 if (clk_id < 0)
1695 return clk_id;
1696
1697 if (clk_type == SMU_GFXCLK)
1698 amdgpu_gfx_off_ctrl(adev, false);
1699
1700 if (max > 0) {
1701 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1702 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1703 param, NULL);
1704 if (ret)
1705 goto out;
1706 }
1707
1708 if (min > 0) {
1709 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1710 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1711 param, NULL);
1712 if (ret)
1713 goto out;
1714 }
1715
1716out:
1717 if (clk_type == SMU_GFXCLK)
1718 amdgpu_gfx_off_ctrl(adev, true);
1719
1720 return ret;
1721}
1722
1723int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1724 enum smu_clk_type clk_type,
1725 uint32_t min,
1726 uint32_t max)
1727{
1728 int ret = 0, clk_id = 0;
1729 uint32_t param;
1730
1731 if (min <= 0 && max <= 0)
1732 return -EINVAL;
1733
1734 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1735 return 0;
1736
1737 clk_id = smu_cmn_to_asic_specific_index(smu,
1738 CMN2ASIC_MAPPING_CLK,
1739 clk_type);
1740 if (clk_id < 0)
1741 return clk_id;
1742
1743 if (max > 0) {
1744 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1745 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1746 param, NULL);
1747 if (ret)
1748 return ret;
1749 }
1750
1751 if (min > 0) {
1752 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1753 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1754 param, NULL);
1755 if (ret)
1756 return ret;
1757 }
1758
1759 return ret;
1760}
1761
1762int smu_v11_0_set_performance_level(struct smu_context *smu,
1763 enum amd_dpm_forced_level level)
1764{
1765 struct smu_11_0_dpm_context *dpm_context =
1766 smu->smu_dpm.dpm_context;
1767 struct smu_11_0_dpm_table *gfx_table =
1768 &dpm_context->dpm_tables.gfx_table;
1769 struct smu_11_0_dpm_table *mem_table =
1770 &dpm_context->dpm_tables.uclk_table;
1771 struct smu_11_0_dpm_table *soc_table =
1772 &dpm_context->dpm_tables.soc_table;
1773 struct smu_umd_pstate_table *pstate_table =
1774 &smu->pstate_table;
1775 struct amdgpu_device *adev = smu->adev;
1776 uint32_t sclk_min = 0, sclk_max = 0;
1777 uint32_t mclk_min = 0, mclk_max = 0;
1778 uint32_t socclk_min = 0, socclk_max = 0;
1779 int ret = 0;
1780
1781 switch (level) {
1782 case AMD_DPM_FORCED_LEVEL_HIGH:
1783 sclk_min = sclk_max = gfx_table->max;
1784 mclk_min = mclk_max = mem_table->max;
1785 socclk_min = socclk_max = soc_table->max;
1786 break;
1787 case AMD_DPM_FORCED_LEVEL_LOW:
1788 sclk_min = sclk_max = gfx_table->min;
1789 mclk_min = mclk_max = mem_table->min;
1790 socclk_min = socclk_max = soc_table->min;
1791 break;
1792 case AMD_DPM_FORCED_LEVEL_AUTO:
1793 sclk_min = gfx_table->min;
1794 sclk_max = gfx_table->max;
1795 mclk_min = mem_table->min;
1796 mclk_max = mem_table->max;
1797 socclk_min = soc_table->min;
1798 socclk_max = soc_table->max;
1799 break;
1800 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1801 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1802 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1803 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1804 break;
1805 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1806 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1807 break;
1808 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1809 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1810 break;
1811 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1812 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1813 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1814 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1815 break;
1816 case AMD_DPM_FORCED_LEVEL_MANUAL:
1817 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1818 return 0;
1819 default:
1820 dev_err(adev->dev, "Invalid performance level %d\n", level);
1821 return -EINVAL;
1822 }
1823
1824 /*
1825 * Separate MCLK and SOCCLK soft min/max settings are not allowed
1826 * on Arcturus.
1827 */
1828 if (adev->asic_type == CHIP_ARCTURUS) {
1829 mclk_min = mclk_max = 0;
1830 socclk_min = socclk_max = 0;
1831 }
1832
1833 if (sclk_min && sclk_max) {
1834 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1835 SMU_GFXCLK,
1836 sclk_min,
1837 sclk_max);
1838 if (ret)
1839 return ret;
1840 }
1841
1842 if (mclk_min && mclk_max) {
1843 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1844 SMU_MCLK,
1845 mclk_min,
1846 mclk_max);
1847 if (ret)
1848 return ret;
1849 }
1850
1851 if (socclk_min && socclk_max) {
1852 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1853 SMU_SOCCLK,
1854 socclk_min,
1855 socclk_max);
1856 if (ret)
1857 return ret;
1858 }
1859
1860 return ret;
1861}
1862
1863int smu_v11_0_set_power_source(struct smu_context *smu,
1864 enum smu_power_src_type power_src)
1865{
1866 int pwr_source;
1867
1868 pwr_source = smu_cmn_to_asic_specific_index(smu,
1869 CMN2ASIC_MAPPING_PWR,
1870 (uint32_t)power_src);
1871 if (pwr_source < 0)
1872 return -EINVAL;
1873
1874 return smu_cmn_send_smc_msg_with_param(smu,
1875 SMU_MSG_NotifyPowerSource,
1876 pwr_source,
1877 NULL);
1878}
1879
1880int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1881 enum smu_clk_type clk_type,
1882 uint16_t level,
1883 uint32_t *value)
1884{
1885 int ret = 0, clk_id = 0;
1886 uint32_t param;
1887
1888 if (!value)
1889 return -EINVAL;
1890
1891 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1892 return 0;
1893
1894 clk_id = smu_cmn_to_asic_specific_index(smu,
1895 CMN2ASIC_MAPPING_CLK,
1896 clk_type);
1897 if (clk_id < 0)
1898 return clk_id;
1899
1900 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1901
1902 ret = smu_cmn_send_smc_msg_with_param(smu,
1903 SMU_MSG_GetDpmFreqByIndex,
1904 param,
1905 value);
1906 if (ret)
1907 return ret;
1908
1909 /*
1910 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1911 * now, we un-support it
1912 */
1913 *value = *value & 0x7fffffff;
1914
1915 return ret;
1916}
1917
1918int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1919 enum smu_clk_type clk_type,
1920 uint32_t *value)
1921{
1922 return smu_v11_0_get_dpm_freq_by_index(smu,
1923 clk_type,
1924 0xff,
1925 value);
1926}
1927
1928int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1929 enum smu_clk_type clk_type,
1930 struct smu_11_0_dpm_table *single_dpm_table)
1931{
1932 int ret = 0;
1933 uint32_t clk;
1934 int i;
1935
1936 ret = smu_v11_0_get_dpm_level_count(smu,
1937 clk_type,
1938 &single_dpm_table->count);
1939 if (ret) {
1940 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1941 return ret;
1942 }
1943
1944 for (i = 0; i < single_dpm_table->count; i++) {
1945 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1946 clk_type,
1947 i,
1948 &clk);
1949 if (ret) {
1950 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1951 return ret;
1952 }
1953
1954 single_dpm_table->dpm_levels[i].value = clk;
1955 single_dpm_table->dpm_levels[i].enabled = true;
1956
1957 if (i == 0)
1958 single_dpm_table->min = clk;
1959 else if (i == single_dpm_table->count - 1)
1960 single_dpm_table->max = clk;
1961 }
1962
1963 return 0;
1964}
1965
1966int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
1967 enum smu_clk_type clk_type,
1968 uint32_t *min_value,
1969 uint32_t *max_value)
1970{
1971 uint32_t level_count = 0;
1972 int ret = 0;
1973
1974 if (!min_value && !max_value)
1975 return -EINVAL;
1976
1977 if (min_value) {
1978 /* by default, level 0 clock value as min value */
1979 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1980 clk_type,
1981 0,
1982 min_value);
1983 if (ret)
1984 return ret;
1985 }
1986
1987 if (max_value) {
1988 ret = smu_v11_0_get_dpm_level_count(smu,
1989 clk_type,
1990 &level_count);
1991 if (ret)
1992 return ret;
1993
1994 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1995 clk_type,
1996 level_count - 1,
1997 max_value);
1998 if (ret)
1999 return ret;
2000 }
2001
2002 return ret;
2003}
2004
2005int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
2006{
2007 struct amdgpu_device *adev = smu->adev;
2008
2009 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2010 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2011 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2012}
2013
2014uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2015{
2016 uint32_t width_level;
2017
2018 width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2019 if (width_level > LINK_WIDTH_MAX)
2020 width_level = 0;
2021
2022 return link_width[width_level];
2023}
2024
2025int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2026{
2027 struct amdgpu_device *adev = smu->adev;
2028
2029 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2030 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2031 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2032}
2033
2034uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2035{
2036 uint32_t speed_level;
2037
2038 speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2039 if (speed_level > LINK_SPEED_MAX)
2040 speed_level = 0;
2041
2042 return link_speed[speed_level];
2043}
2044
2045int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2046 bool enablement)
2047{
2048 int ret = 0;
2049
2050 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2051 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2052
2053 return ret;
2054}
2055
2056int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2057 bool enablement)
2058{
2059 struct amdgpu_device *adev = smu->adev;
2060 int ret = 0;
2061
2062 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2063 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2064 if (ret) {
2065 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2066 return ret;
2067 }
2068 }
2069
2070 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2071 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2072 if (ret) {
2073 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2074 return ret;
2075 }
2076 }
2077
2078 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2079 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2080 if (ret) {
2081 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2082 return ret;
2083 }
2084 }
2085
2086 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2087 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2088 if (ret) {
2089 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2090 return ret;
2091 }
2092 }
2093
2094 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2095 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2096 if (ret) {
2097 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2098 return ret;
2099 }
2100 }
2101
2102 return ret;
2103}