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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "mmhub_v1_0.h"
25
26#include "mmhub/mmhub_1_0_offset.h"
27#include "mmhub/mmhub_1_0_sh_mask.h"
28#include "mmhub/mmhub_1_0_default.h"
29#include "athub/athub_1_0_offset.h"
30#include "athub/athub_1_0_sh_mask.h"
31#include "vega10_enum.h"
32
33#include "soc15_common.h"
34
35#define mmDAGB0_CNTL_MISC2_RV 0x008f
36#define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
37
38u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
39{
40 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
41
42 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
43 base <<= 24;
44
45 return base;
46}
47
48static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
49{
50 uint64_t value;
51
52 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
53 value = adev->gart.table_addr - adev->gmc.vram_start +
54 adev->vm_manager.vram_base_offset;
55 value &= 0x0000FFFFFFFFF000ULL;
56 value |= 0x1; /* valid bit */
57
58 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
59 lower_32_bits(value));
60
61 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
62 upper_32_bits(value));
63}
64
65static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
66{
67 mmhub_v1_0_init_gart_pt_regs(adev);
68
69 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
70 (u32)(adev->gmc.gart_start >> 12));
71 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
72 (u32)(adev->gmc.gart_start >> 44));
73
74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
75 (u32)(adev->gmc.gart_end >> 12));
76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
77 (u32)(adev->gmc.gart_end >> 44));
78}
79
80static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
81{
82 uint64_t value;
83 uint32_t tmp;
84
85 /* Disable AGP. */
86 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
87 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
88 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF);
89
90 /* Program the system aperture low logical page number. */
91 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
92 adev->gmc.vram_start >> 18);
93 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
94 adev->gmc.vram_end >> 18);
95
96 /* Set default page address. */
97 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
98 adev->vm_manager.vram_base_offset;
99 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
100 (u32)(value >> 12));
101 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
102 (u32)(value >> 44));
103
104 /* Program "protection fault". */
105 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
106 (u32)(adev->dummy_page_addr >> 12));
107 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
108 (u32)((u64)adev->dummy_page_addr >> 44));
109
110 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
111 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
112 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
113 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
114}
115
116static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
117{
118 uint32_t tmp;
119
120 /* Setup TLB control */
121 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
122
123 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
124 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
125 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
126 ENABLE_ADVANCED_DRIVER_MODEL, 1);
127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
128 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
129 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
130 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
131 MTYPE, MTYPE_UC);/* XXX for emulation. */
132 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
133
134 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
135}
136
137static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
138{
139 uint32_t tmp;
140
141 /* Setup L2 cache */
142 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
143 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
144 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
145 /* XXX for emulation, Refer to closed source code.*/
146 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
147 0);
148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
149 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
150 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
151 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
152
153 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
154 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
155 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
156 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
157
158 if (adev->gmc.translate_further) {
159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
160 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
161 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
162 } else {
163 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
164 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
165 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
166 }
167
168 tmp = mmVM_L2_CNTL4_DEFAULT;
169 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
170 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
171 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
172}
173
174static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
175{
176 uint32_t tmp;
177
178 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
179 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
180 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
181 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
182}
183
184static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
185{
186 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
187 0XFFFFFFFF);
188 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
189 0x0000000F);
190
191 WREG32_SOC15(MMHUB, 0,
192 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
193 WREG32_SOC15(MMHUB, 0,
194 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
195
196 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
197 0);
198 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
199 0);
200}
201
202static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
203{
204 unsigned num_level, block_size;
205 uint32_t tmp;
206 int i;
207
208 num_level = adev->vm_manager.num_level;
209 block_size = adev->vm_manager.block_size;
210 if (adev->gmc.translate_further)
211 num_level -= 1;
212 else
213 block_size -= 9;
214
215 for (i = 0; i <= 14; i++) {
216 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
217 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
218 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
219 num_level);
220 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
221 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
222 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
223 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
224 1);
225 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
226 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
227 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
228 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
229 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
230 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
231 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
232 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
233 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
234 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
235 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
236 PAGE_TABLE_BLOCK_SIZE,
237 block_size);
238 /* Send no-retry XNACK on fault to suppress VM fault storm. */
239 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
240 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
241 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp);
242 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
243 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
244 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2,
245 lower_32_bits(adev->vm_manager.max_pfn - 1));
246 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
247 upper_32_bits(adev->vm_manager.max_pfn - 1));
248 }
249}
250
251static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
252{
253 unsigned i;
254
255 for (i = 0; i < 18; ++i) {
256 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
257 2 * i, 0xffffffff);
258 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
259 2 * i, 0x1f);
260 }
261}
262
263struct pctl_data {
264 uint32_t index;
265 uint32_t data;
266};
267
268static const struct pctl_data pctl0_data[] = {
269 {0x0, 0x7a640},
270 {0x9, 0x2a64a},
271 {0xd, 0x2a680},
272 {0x11, 0x6a684},
273 {0x19, 0xea68e},
274 {0x29, 0xa69e},
275 {0x2b, 0x0010a6c0},
276 {0x3d, 0x83a707},
277 {0xc2, 0x8a7a4},
278 {0xcc, 0x1a7b8},
279 {0xcf, 0xfa7cc},
280 {0xe0, 0x17a7dd},
281 {0xf9, 0xa7dc},
282 {0xfb, 0x12a7f5},
283 {0x10f, 0xa808},
284 {0x111, 0x12a810},
285 {0x125, 0x7a82c}
286};
287#define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data))
288
289#define PCTL0_RENG_EXEC_END_PTR 0x12d
290#define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640
291#define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
292
293static const struct pctl_data pctl1_data[] = {
294 {0x0, 0x39a000},
295 {0x3b, 0x44a040},
296 {0x81, 0x2a08d},
297 {0x85, 0x6ba094},
298 {0xf2, 0x18a100},
299 {0x10c, 0x4a132},
300 {0x112, 0xca141},
301 {0x120, 0x2fa158},
302 {0x151, 0x17a1d0},
303 {0x16a, 0x1a1e9},
304 {0x16d, 0x13a1ec},
305 {0x182, 0x7a201},
306 {0x18b, 0x3a20a},
307 {0x190, 0x7a580},
308 {0x199, 0xa590},
309 {0x19b, 0x4a594},
310 {0x1a1, 0x1a59c},
311 {0x1a4, 0x7a82c},
312 {0x1ad, 0xfa7cc},
313 {0x1be, 0x17a7dd},
314 {0x1d7, 0x12a810},
315 {0x1eb, 0x4000a7e1},
316 {0x1ec, 0x5000a7f5},
317 {0x1ed, 0x4000a7e2},
318 {0x1ee, 0x5000a7dc},
319 {0x1ef, 0x4000a7e3},
320 {0x1f0, 0x5000a7f6},
321 {0x1f1, 0x5000a7e4}
322};
323#define PCTL1_DATA_LEN (ARRAY_SIZE(pctl1_data))
324
325#define PCTL1_RENG_EXEC_END_PTR 0x1f1
326#define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000
327#define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d
328#define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE 0xa580
329#define PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT 0xa59d
330#define PCTL1_STCTRL_REG_SAVE_RANGE2_BASE 0xa82c
331#define PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT 0xa833
332
333static void mmhub_v1_0_power_gating_write_save_ranges(struct amdgpu_device *adev)
334{
335 uint32_t tmp = 0;
336
337 /* PCTL0_STCTRL_REGISTER_SAVE_RANGE0 */
338 tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
339 STCTRL_REGISTER_SAVE_BASE,
340 PCTL0_STCTRL_REG_SAVE_RANGE0_BASE);
341 tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0,
342 STCTRL_REGISTER_SAVE_LIMIT,
343 PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT);
344 WREG32_SOC15(MMHUB, 0, mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0, tmp);
345
346 /* PCTL1_STCTRL_REGISTER_SAVE_RANGE0 */
347 tmp = 0;
348 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
349 STCTRL_REGISTER_SAVE_BASE,
350 PCTL1_STCTRL_REG_SAVE_RANGE0_BASE);
351 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0,
352 STCTRL_REGISTER_SAVE_LIMIT,
353 PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT);
354 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0, tmp);
355
356 /* PCTL1_STCTRL_REGISTER_SAVE_RANGE1 */
357 tmp = 0;
358 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
359 STCTRL_REGISTER_SAVE_BASE,
360 PCTL1_STCTRL_REG_SAVE_RANGE1_BASE);
361 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1,
362 STCTRL_REGISTER_SAVE_LIMIT,
363 PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT);
364 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1, tmp);
365
366 /* PCTL1_STCTRL_REGISTER_SAVE_RANGE2 */
367 tmp = 0;
368 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2,
369 STCTRL_REGISTER_SAVE_BASE,
370 PCTL1_STCTRL_REG_SAVE_RANGE2_BASE);
371 tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2,
372 STCTRL_REGISTER_SAVE_LIMIT,
373 PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT);
374 WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2, tmp);
375}
376
377void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev)
378{
379 uint32_t pctl0_misc = 0;
380 uint32_t pctl0_reng_execute = 0;
381 uint32_t pctl1_misc = 0;
382 uint32_t pctl1_reng_execute = 0;
383 int i = 0;
384
385 if (amdgpu_sriov_vf(adev))
386 return;
387
388 /****************** pctl0 **********************/
389 pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC);
390 pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
391
392 /* Light sleep must be disabled before writing to pctl0 registers */
393 pctl0_misc &= ~PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
394 WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
395
396 /* Write data used to access ram of register engine */
397 for (i = 0; i < PCTL0_DATA_LEN; i++) {
398 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_INDEX,
399 pctl0_data[i].index);
400 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_DATA,
401 pctl0_data[i].data);
402 }
403
404 /* Re-enable light sleep */
405 pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK;
406 WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc);
407
408 /****************** pctl1 **********************/
409 pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC);
410 pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
411
412 /* Light sleep must be disabled before writing to pctl1 registers */
413 pctl1_misc &= ~PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
414 WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
415
416 /* Write data used to access ram of register engine */
417 for (i = 0; i < PCTL1_DATA_LEN; i++) {
418 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_INDEX,
419 pctl1_data[i].index);
420 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_DATA,
421 pctl1_data[i].data);
422 }
423
424 /* Re-enable light sleep */
425 pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK;
426 WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc);
427
428 mmhub_v1_0_power_gating_write_save_ranges(adev);
429
430 /* Set the reng execute end ptr for pctl0 */
431 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
432 PCTL0_RENG_EXECUTE,
433 RENG_EXECUTE_END_PTR,
434 PCTL0_RENG_EXEC_END_PTR);
435 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
436
437 /* Set the reng execute end ptr for pctl1 */
438 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
439 PCTL1_RENG_EXECUTE,
440 RENG_EXECUTE_END_PTR,
441 PCTL1_RENG_EXEC_END_PTR);
442 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
443}
444
445void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
446 bool enable)
447{
448 uint32_t pctl0_reng_execute = 0;
449 uint32_t pctl1_reng_execute = 0;
450
451 if (amdgpu_sriov_vf(adev))
452 return;
453
454 pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE);
455 pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE);
456
457 if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
458 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
459 PCTL0_RENG_EXECUTE,
460 RENG_EXECUTE_ON_PWR_UP, 1);
461 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
462 PCTL0_RENG_EXECUTE,
463 RENG_EXECUTE_ON_REG_UPDATE, 1);
464 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
465
466 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
467 PCTL1_RENG_EXECUTE,
468 RENG_EXECUTE_ON_PWR_UP, 1);
469 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
470 PCTL1_RENG_EXECUTE,
471 RENG_EXECUTE_ON_REG_UPDATE, 1);
472 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
473
474 if (adev->powerplay.pp_funcs->set_mmhub_powergating_by_smu)
475 amdgpu_dpm_set_mmhub_powergating_by_smu(adev);
476
477 } else {
478 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
479 PCTL0_RENG_EXECUTE,
480 RENG_EXECUTE_ON_PWR_UP, 0);
481 pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
482 PCTL0_RENG_EXECUTE,
483 RENG_EXECUTE_ON_REG_UPDATE, 0);
484 WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute);
485
486 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
487 PCTL1_RENG_EXECUTE,
488 RENG_EXECUTE_ON_PWR_UP, 0);
489 pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute,
490 PCTL1_RENG_EXECUTE,
491 RENG_EXECUTE_ON_REG_UPDATE, 0);
492 WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
493 }
494}
495
496int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
497{
498 if (amdgpu_sriov_vf(adev)) {
499 /*
500 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
501 * VF copy registers so vbios post doesn't program them, for
502 * SRIOV driver need to program them
503 */
504 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,
505 adev->gmc.vram_start >> 24);
506 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,
507 adev->gmc.vram_end >> 24);
508 }
509
510 /* GART Enable. */
511 mmhub_v1_0_init_gart_aperture_regs(adev);
512 mmhub_v1_0_init_system_aperture_regs(adev);
513 mmhub_v1_0_init_tlb_regs(adev);
514 mmhub_v1_0_init_cache_regs(adev);
515
516 mmhub_v1_0_enable_system_domain(adev);
517 mmhub_v1_0_disable_identity_aperture(adev);
518 mmhub_v1_0_setup_vmid_config(adev);
519 mmhub_v1_0_program_invalidation(adev);
520
521 return 0;
522}
523
524void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
525{
526 u32 tmp;
527 u32 i;
528
529 /* Disable all tables */
530 for (i = 0; i < 16; i++)
531 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0);
532
533 /* Setup TLB control */
534 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
535 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
536 tmp = REG_SET_FIELD(tmp,
537 MC_VM_MX_L1_TLB_CNTL,
538 ENABLE_ADVANCED_DRIVER_MODEL,
539 0);
540 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
541
542 /* Setup L2 cache */
543 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
544 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
545 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
546 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);
547}
548
549/**
550 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
551 *
552 * @adev: amdgpu_device pointer
553 * @value: true redirects VM faults to the default page
554 */
555void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
556{
557 u32 tmp;
558 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
559 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
560 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
561 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
562 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
563 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
564 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
565 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
566 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
567 tmp = REG_SET_FIELD(tmp,
568 VM_L2_PROTECTION_FAULT_CNTL,
569 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
570 value);
571 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
572 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
573 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
574 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
575 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
576 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
577 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
578 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
579 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
580 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
581 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
582 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
583 if (!value) {
584 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
585 CRASH_ON_NO_RETRY_FAULT, 1);
586 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
587 CRASH_ON_RETRY_FAULT, 1);
588 }
589
590 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
591}
592
593void mmhub_v1_0_init(struct amdgpu_device *adev)
594{
595 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB];
596
597 hub->ctx0_ptb_addr_lo32 =
598 SOC15_REG_OFFSET(MMHUB, 0,
599 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
600 hub->ctx0_ptb_addr_hi32 =
601 SOC15_REG_OFFSET(MMHUB, 0,
602 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
603 hub->vm_inv_eng0_req =
604 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
605 hub->vm_inv_eng0_ack =
606 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
607 hub->vm_context0_cntl =
608 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
609 hub->vm_l2_pro_fault_status =
610 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
611 hub->vm_l2_pro_fault_cntl =
612 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
613
614}
615
616static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
617 bool enable)
618{
619 uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
620
621 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
622
623 if (adev->asic_type != CHIP_RAVEN) {
624 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
625 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);
626 } else
627 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);
628
629 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
630 data |= ATC_L2_MISC_CG__ENABLE_MASK;
631
632 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
633 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
634 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
635 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
636 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
637 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
638
639 if (adev->asic_type != CHIP_RAVEN)
640 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
641 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
642 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
643 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
644 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
645 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
646 } else {
647 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
648
649 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
650 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
651 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
652 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
653 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
654 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
655
656 if (adev->asic_type != CHIP_RAVEN)
657 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
658 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
659 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
660 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
661 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
662 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
663 }
664
665 if (def != data)
666 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
667
668 if (def1 != data1) {
669 if (adev->asic_type != CHIP_RAVEN)
670 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
671 else
672 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
673 }
674
675 if (adev->asic_type != CHIP_RAVEN && def2 != data2)
676 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
677}
678
679static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
680 bool enable)
681{
682 uint32_t def, data;
683
684 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
685
686 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
687 data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
688 else
689 data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
690
691 if (def != data)
692 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
693}
694
695static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
696 bool enable)
697{
698 uint32_t def, data;
699
700 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
701
702 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
703 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
704 else
705 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
706
707 if (def != data)
708 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
709}
710
711static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
712 bool enable)
713{
714 uint32_t def, data;
715
716 def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
717
718 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
719 (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
720 data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
721 else
722 data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
723
724 if(def != data)
725 WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
726}
727
728int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
729 enum amd_clockgating_state state)
730{
731 if (amdgpu_sriov_vf(adev))
732 return 0;
733
734 switch (adev->asic_type) {
735 case CHIP_VEGA10:
736 case CHIP_VEGA12:
737 case CHIP_RAVEN:
738 mmhub_v1_0_update_medium_grain_clock_gating(adev,
739 state == AMD_CG_STATE_GATE ? true : false);
740 athub_update_medium_grain_clock_gating(adev,
741 state == AMD_CG_STATE_GATE ? true : false);
742 mmhub_v1_0_update_medium_grain_light_sleep(adev,
743 state == AMD_CG_STATE_GATE ? true : false);
744 athub_update_medium_grain_light_sleep(adev,
745 state == AMD_CG_STATE_GATE ? true : false);
746 break;
747 default:
748 break;
749 }
750
751 return 0;
752}
753
754void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
755{
756 int data;
757
758 if (amdgpu_sriov_vf(adev))
759 *flags = 0;
760
761 /* AMD_CG_SUPPORT_MC_MGCG */
762 data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
763 if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
764 *flags |= AMD_CG_SUPPORT_MC_MGCG;
765
766 /* AMD_CG_SUPPORT_MC_LS */
767 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
768 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
769 *flags |= AMD_CG_SUPPORT_MC_LS;
770}
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_ras.h"
25#include "mmhub_v1_0.h"
26
27#include "mmhub/mmhub_1_0_offset.h"
28#include "mmhub/mmhub_1_0_sh_mask.h"
29#include "mmhub/mmhub_1_0_default.h"
30#include "vega10_enum.h"
31#include "soc15.h"
32#include "soc15_common.h"
33
34#define mmDAGB0_CNTL_MISC2_RV 0x008f
35#define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0
36
37static u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
38{
39 u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE);
40 u64 top = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP);
41
42 base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
43 base <<= 24;
44
45 top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
46 top <<= 24;
47
48 adev->gmc.fb_start = base;
49 adev->gmc.fb_end = top;
50
51 return base;
52}
53
54static void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
55 uint64_t page_table_base)
56{
57 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
58
59 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
60 hub->ctx_addr_distance * vmid,
61 lower_32_bits(page_table_base));
62
63 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
64 hub->ctx_addr_distance * vmid,
65 upper_32_bits(page_table_base));
66}
67
68static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
69{
70 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
71
72 mmhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
73
74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
75 (u32)(adev->gmc.gart_start >> 12));
76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
77 (u32)(adev->gmc.gart_start >> 44));
78
79 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
80 (u32)(adev->gmc.gart_end >> 12));
81 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
82 (u32)(adev->gmc.gart_end >> 44));
83}
84
85static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
86{
87 uint64_t value;
88 uint32_t tmp;
89
90 /* Program the AGP BAR */
91 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
94
95 /* Program the system aperture low logical page number. */
96 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
97 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
98
99 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
100 /*
101 * Raven2 has a HW issue that it is unable to use the vram which
102 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
103 * workaround that increase system aperture high address (add 1)
104 * to get rid of the VM fault and hardware hang.
105 */
106 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
107 max((adev->gmc.fb_end >> 18) + 0x1,
108 adev->gmc.agp_end >> 18));
109 else
110 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
111 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
112
113 if (amdgpu_sriov_vf(adev))
114 return;
115
116 /* Set default page address. */
117 value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
118 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
119 (u32)(value >> 12));
120 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
121 (u32)(value >> 44));
122
123 /* Program "protection fault". */
124 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
125 (u32)(adev->dummy_page_addr >> 12));
126 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
127 (u32)((u64)adev->dummy_page_addr >> 44));
128
129 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2);
130 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
131 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
132 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp);
133}
134
135static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
136{
137 uint32_t tmp;
138
139 /* Setup TLB control */
140 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
141
142 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
143 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
144 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
145 ENABLE_ADVANCED_DRIVER_MODEL, 1);
146 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
147 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
148 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
149 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
150 MTYPE, MTYPE_UC);/* XXX for emulation. */
151 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
152
153 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
154}
155
156static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
157{
158 uint32_t tmp;
159
160 if (amdgpu_sriov_vf(adev))
161 return;
162
163 /* Setup L2 cache */
164 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
165 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
166 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
167 /* XXX for emulation, Refer to closed source code.*/
168 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
169 0);
170 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
171 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
172 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
173 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
174
175 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2);
176 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
177 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
178 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
179
180 if (adev->gmc.translate_further) {
181 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
182 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
183 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
184 } else {
185 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
186 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
187 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
188 }
189 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp);
190
191 tmp = mmVM_L2_CNTL4_DEFAULT;
192 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
193 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
194 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp);
195}
196
197static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
198{
199 uint32_t tmp;
200
201 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL);
202 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
203 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
204 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
205 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
206 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp);
207}
208
209static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
210{
211 if (amdgpu_sriov_vf(adev))
212 return;
213
214 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
215 0XFFFFFFFF);
216 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
217 0x0000000F);
218
219 WREG32_SOC15(MMHUB, 0,
220 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
221 WREG32_SOC15(MMHUB, 0,
222 mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
223
224 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
225 0);
226 WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
227 0);
228}
229
230static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
231{
232 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
233 unsigned num_level, block_size;
234 uint32_t tmp;
235 int i;
236
237 num_level = adev->vm_manager.num_level;
238 block_size = adev->vm_manager.block_size;
239 if (adev->gmc.translate_further)
240 num_level -= 1;
241 else
242 block_size -= 9;
243
244 for (i = 0; i <= 14; i++) {
245 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
246 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
247 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
248 num_level);
249 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
250 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
251 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
252 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
253 1);
254 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
255 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
256 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
257 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
258 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
259 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
260 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
261 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
262 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
263 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
264 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
265 PAGE_TABLE_BLOCK_SIZE,
266 block_size);
267 /* Send no-retry XNACK on fault to suppress VM fault storm. */
268 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
269 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
270 !adev->gmc.noretry);
271 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL,
272 i * hub->ctx_distance, tmp);
273 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
274 i * hub->ctx_addr_distance, 0);
275 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
276 i * hub->ctx_addr_distance, 0);
277 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
278 i * hub->ctx_addr_distance,
279 lower_32_bits(adev->vm_manager.max_pfn - 1));
280 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
281 i * hub->ctx_addr_distance,
282 upper_32_bits(adev->vm_manager.max_pfn - 1));
283 }
284}
285
286static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)
287{
288 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
289 unsigned i;
290
291 for (i = 0; i < 18; ++i) {
292 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
293 i * hub->eng_addr_distance, 0xffffffff);
294 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
295 i * hub->eng_addr_distance, 0x1f);
296 }
297}
298
299static void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
300 bool enable)
301{
302 if (amdgpu_sriov_vf(adev))
303 return;
304
305 if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) {
306 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GMC, true);
307
308 }
309}
310
311static int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
312{
313 if (amdgpu_sriov_vf(adev)) {
314 /*
315 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
316 * VF copy registers so vbios post doesn't program them, for
317 * SRIOV driver need to program them
318 */
319 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE,
320 adev->gmc.vram_start >> 24);
321 WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP,
322 adev->gmc.vram_end >> 24);
323 }
324
325 /* GART Enable. */
326 mmhub_v1_0_init_gart_aperture_regs(adev);
327 mmhub_v1_0_init_system_aperture_regs(adev);
328 mmhub_v1_0_init_tlb_regs(adev);
329 mmhub_v1_0_init_cache_regs(adev);
330
331 mmhub_v1_0_enable_system_domain(adev);
332 mmhub_v1_0_disable_identity_aperture(adev);
333 mmhub_v1_0_setup_vmid_config(adev);
334 mmhub_v1_0_program_invalidation(adev);
335
336 return 0;
337}
338
339static void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
340{
341 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
342 u32 tmp;
343 u32 i;
344
345 /* Disable all tables */
346 for (i = 0; i < AMDGPU_NUM_VMID; i++)
347 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL,
348 i * hub->ctx_distance, 0);
349
350 /* Setup TLB control */
351 tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL);
352 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
353 tmp = REG_SET_FIELD(tmp,
354 MC_VM_MX_L1_TLB_CNTL,
355 ENABLE_ADVANCED_DRIVER_MODEL,
356 0);
357 WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
358
359 if (!amdgpu_sriov_vf(adev)) {
360 /* Setup L2 cache */
361 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL);
362 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
363 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp);
364 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0);
365 }
366}
367
368/**
369 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
370 *
371 * @adev: amdgpu_device pointer
372 * @value: true redirects VM faults to the default page
373 */
374static void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
375{
376 u32 tmp;
377
378 if (amdgpu_sriov_vf(adev))
379 return;
380
381 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
382 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
383 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
384 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
385 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
386 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
387 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
388 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
389 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
390 tmp = REG_SET_FIELD(tmp,
391 VM_L2_PROTECTION_FAULT_CNTL,
392 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
393 value);
394 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
395 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
396 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
397 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
398 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
399 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
400 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
401 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
402 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
403 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
404 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
405 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
406 if (!value) {
407 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
408 CRASH_ON_NO_RETRY_FAULT, 1);
409 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
410 CRASH_ON_RETRY_FAULT, 1);
411 }
412
413 WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
414}
415
416static void mmhub_v1_0_init(struct amdgpu_device *adev)
417{
418 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
419
420 hub->ctx0_ptb_addr_lo32 =
421 SOC15_REG_OFFSET(MMHUB, 0,
422 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
423 hub->ctx0_ptb_addr_hi32 =
424 SOC15_REG_OFFSET(MMHUB, 0,
425 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
426 hub->vm_inv_eng0_sem =
427 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_SEM);
428 hub->vm_inv_eng0_req =
429 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ);
430 hub->vm_inv_eng0_ack =
431 SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK);
432 hub->vm_context0_cntl =
433 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL);
434 hub->vm_l2_pro_fault_status =
435 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
436 hub->vm_l2_pro_fault_cntl =
437 SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
438
439 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL;
440 hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
441 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
442 hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ;
443 hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
444 mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
445}
446
447static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
448 bool enable)
449{
450 uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
451
452 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
453
454 if (adev->asic_type != CHIP_RAVEN) {
455 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
456 def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);
457 } else
458 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV);
459
460 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
461 data |= ATC_L2_MISC_CG__ENABLE_MASK;
462
463 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
464 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
465 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
466 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
467 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
468 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
469
470 if (adev->asic_type != CHIP_RAVEN)
471 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
472 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
473 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
474 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
475 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
476 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
477 } else {
478 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
479
480 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
481 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
482 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
483 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
484 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
485 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
486
487 if (adev->asic_type != CHIP_RAVEN)
488 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
489 DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
490 DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
491 DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
492 DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
493 DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
494 }
495
496 if (def != data)
497 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
498
499 if (def1 != data1) {
500 if (adev->asic_type != CHIP_RAVEN)
501 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
502 else
503 WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
504 }
505
506 if (adev->asic_type != CHIP_RAVEN && def2 != data2)
507 WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
508}
509
510static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
511 bool enable)
512{
513 uint32_t def, data;
514
515 def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
516
517 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
518 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
519 else
520 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
521
522 if (def != data)
523 WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
524}
525
526static int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
527 enum amd_clockgating_state state)
528{
529 if (amdgpu_sriov_vf(adev))
530 return 0;
531
532 switch (adev->asic_type) {
533 case CHIP_VEGA10:
534 case CHIP_VEGA12:
535 case CHIP_VEGA20:
536 case CHIP_RAVEN:
537 case CHIP_RENOIR:
538 mmhub_v1_0_update_medium_grain_clock_gating(adev,
539 state == AMD_CG_STATE_GATE);
540 mmhub_v1_0_update_medium_grain_light_sleep(adev,
541 state == AMD_CG_STATE_GATE);
542 break;
543 default:
544 break;
545 }
546
547 return 0;
548}
549
550static void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
551{
552 int data, data1;
553
554 if (amdgpu_sriov_vf(adev))
555 *flags = 0;
556
557 data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
558
559 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
560
561 /* AMD_CG_SUPPORT_MC_MGCG */
562 if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
563 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
564 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
565 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
566 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
567 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
568 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
569 *flags |= AMD_CG_SUPPORT_MC_MGCG;
570
571 /* AMD_CG_SUPPORT_MC_LS */
572 if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
573 *flags |= AMD_CG_SUPPORT_MC_LS;
574}
575
576static const struct soc15_ras_field_entry mmhub_v1_0_ras_fields[] = {
577 { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
578 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT),
579 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT),
580 },
581 { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
582 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT),
583 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT),
584 },
585 { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
586 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT),
587 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT),
588 },
589 { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
590 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT),
591 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT),
592 },
593 { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
594 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT),
595 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT),
596 },
597 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
598 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT),
599 0, 0,
600 },
601 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
602 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT),
603 0, 0,
604 },
605 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
606 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT),
607 0, 0,
608 },
609 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
610 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT),
611 0, 0,
612 },
613 { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20),
614 SOC15_REG_FIELD(MMEA0_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT),
615 0, 0,
616 },
617 { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
618 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT),
619 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT),
620 },
621 { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
622 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT),
623 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT),
624 },
625 { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
626 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT),
627 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT),
628 },
629 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
630 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT),
631 0, 0,
632 },
633 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20),
634 SOC15_REG_FIELD(MMEA0_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT),
635 0, 0,
636 },
637 { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
638 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_SEC_COUNT),
639 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_CMDMEM_DED_COUNT),
640 },
641 { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
642 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_SEC_COUNT),
643 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_CMDMEM_DED_COUNT),
644 },
645 { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
646 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_SEC_COUNT),
647 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_DATAMEM_DED_COUNT),
648 },
649 { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
650 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_SEC_COUNT),
651 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, RRET_TAGMEM_DED_COUNT),
652 },
653 { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
654 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_SEC_COUNT),
655 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, WRET_TAGMEM_DED_COUNT),
656 },
657 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
658 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMRD_PAGEMEM_SED_COUNT),
659 0, 0,
660 },
661 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
662 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, DRAMWR_PAGEMEM_SED_COUNT),
663 0, 0,
664 },
665 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
666 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IORD_CMDMEM_SED_COUNT),
667 0, 0,
668 },
669 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
670 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_CMDMEM_SED_COUNT),
671 0, 0,
672 },
673 { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20),
674 SOC15_REG_FIELD(MMEA1_EDC_CNT_VG20, IOWR_DATAMEM_SED_COUNT),
675 0, 0,
676 },
677 { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
678 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_SEC_COUNT),
679 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_CMDMEM_DED_COUNT),
680 },
681 { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
682 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_SEC_COUNT),
683 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_CMDMEM_DED_COUNT),
684 },
685 { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
686 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_SEC_COUNT),
687 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_DATAMEM_DED_COUNT),
688 },
689 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
690 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIRD_PAGEMEM_SED_COUNT),
691 0, 0,
692 },
693 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20),
694 SOC15_REG_FIELD(MMEA1_EDC_CNT2_VG20, GMIWR_PAGEMEM_SED_COUNT),
695 0, 0,
696 }
697};
698
699static const struct soc15_reg_entry mmhub_v1_0_edc_cnt_regs[] = {
700 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT_VG20), 0, 0, 0},
701 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2_VG20), 0, 0, 0},
702 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT_VG20), 0, 0, 0},
703 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2_VG20), 0, 0, 0},
704};
705
706static int mmhub_v1_0_get_ras_error_count(struct amdgpu_device *adev,
707 const struct soc15_reg_entry *reg,
708 uint32_t value, uint32_t *sec_count, uint32_t *ded_count)
709{
710 uint32_t i;
711 uint32_t sec_cnt, ded_cnt;
712
713 for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_ras_fields); i++) {
714 if (mmhub_v1_0_ras_fields[i].reg_offset != reg->reg_offset)
715 continue;
716
717 sec_cnt = (value &
718 mmhub_v1_0_ras_fields[i].sec_count_mask) >>
719 mmhub_v1_0_ras_fields[i].sec_count_shift;
720 if (sec_cnt) {
721 dev_info(adev->dev,
722 "MMHUB SubBlock %s, SEC %d\n",
723 mmhub_v1_0_ras_fields[i].name,
724 sec_cnt);
725 *sec_count += sec_cnt;
726 }
727
728 ded_cnt = (value &
729 mmhub_v1_0_ras_fields[i].ded_count_mask) >>
730 mmhub_v1_0_ras_fields[i].ded_count_shift;
731 if (ded_cnt) {
732 dev_info(adev->dev,
733 "MMHUB SubBlock %s, DED %d\n",
734 mmhub_v1_0_ras_fields[i].name,
735 ded_cnt);
736 *ded_count += ded_cnt;
737 }
738 }
739
740 return 0;
741}
742
743static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
744 void *ras_error_status)
745{
746 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
747 uint32_t sec_count = 0, ded_count = 0;
748 uint32_t i;
749 uint32_t reg_value;
750
751 err_data->ue_count = 0;
752 err_data->ce_count = 0;
753
754 for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++) {
755 reg_value =
756 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));
757 if (reg_value)
758 mmhub_v1_0_get_ras_error_count(adev,
759 &mmhub_v1_0_edc_cnt_regs[i],
760 reg_value, &sec_count, &ded_count);
761 }
762
763 err_data->ce_count += sec_count;
764 err_data->ue_count += ded_count;
765}
766
767static void mmhub_v1_0_reset_ras_error_count(struct amdgpu_device *adev)
768{
769 uint32_t i;
770
771 /* read back edc counter registers to reset the counters to 0 */
772 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
773 for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++)
774 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));
775 }
776}
777
778const struct amdgpu_mmhub_ras_funcs mmhub_v1_0_ras_funcs = {
779 .ras_late_init = amdgpu_mmhub_ras_late_init,
780 .ras_fini = amdgpu_mmhub_ras_fini,
781 .query_ras_error_count = mmhub_v1_0_query_ras_error_count,
782 .reset_ras_error_count = mmhub_v1_0_reset_ras_error_count,
783};
784
785const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
786 .get_fb_location = mmhub_v1_0_get_fb_location,
787 .init = mmhub_v1_0_init,
788 .gart_enable = mmhub_v1_0_gart_enable,
789 .set_fault_enable_default = mmhub_v1_0_set_fault_enable_default,
790 .gart_disable = mmhub_v1_0_gart_disable,
791 .set_clockgating = mmhub_v1_0_set_clockgating,
792 .get_clockgating = mmhub_v1_0_get_clockgating,
793 .setup_vm_pt_regs = mmhub_v1_0_setup_vm_pt_regs,
794 .update_power_gating = mmhub_v1_0_update_power_gating,
795};