1/*
 2 * Copyright 2018 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_CTX_H__
24#define __AMDGPU_CTX_H__
25
26#include "amdgpu_ring.h"
27
28struct drm_device;
29struct drm_file;
30struct amdgpu_fpriv;
31
32#define AMDGPU_MAX_ENTITY_NUM 4
33#define AMDGPU_CTX_FENCE_USAGE_MIN_RATIO(max, total) ((max) > 16384ULL*(total))
34
35struct amdgpu_ctx_entity {
36	uint64_t		sequence;
37	struct drm_sched_entity	entity;
38	struct dma_fence	*fences[];
39};
40
41struct amdgpu_ctx {
42	struct kref			refcount;
43	struct amdgpu_device		*adev;
44	unsigned			reset_counter;
45	unsigned			reset_counter_query;
46	uint32_t			vram_lost_counter;
47	spinlock_t			ring_lock;
48	struct amdgpu_ctx_entity	*entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM];
49	bool				preamble_presented;
50	enum drm_sched_priority		init_priority;
51	enum drm_sched_priority		override_priority;
52	struct mutex			lock;
53	atomic_t			guilty;
54	unsigned long			ras_counter_ce;
55	unsigned long			ras_counter_ue;
56};
57
58struct amdgpu_ctx_mgr {
59	struct amdgpu_device	*adev;
60	struct mutex		lock;
61	/* protected by lock */
62	struct idr		ctx_handles;
63};
64
65extern const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM];
66
67struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
68int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
69
70int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance,
71			  u32 ring, struct drm_sched_entity **entity);
72void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx,
73			  struct drm_sched_entity *entity,
74			  struct dma_fence *fence, uint64_t *seq);
75struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
76				       struct drm_sched_entity *entity,
77				       uint64_t seq);
78void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
79				  enum drm_sched_priority priority);
80
81int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
82		     struct drm_file *filp);
83
84int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx,
85			       struct drm_sched_entity *entity);
86
87void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
88void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
89long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout);
90void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
91ktime_t amdgpu_ctx_mgr_fence_usage(struct amdgpu_ctx_mgr *mgr, uint32_t hwip,
92		uint32_t idx, uint64_t *elapsed);
93#endif