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1/*
2 * Copyright (C) 2011-2012 Avionic Design GmbH
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/gpio/driver.h>
10#include <linux/i2c.h>
11#include <linux/interrupt.h>
12#include <linux/module.h>
13#include <linux/of_irq.h>
14#include <linux/seq_file.h>
15#include <linux/slab.h>
16
17#define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
18#define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
19#define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
20#define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
21#define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
22
23struct adnp {
24 struct i2c_client *client;
25 struct gpio_chip gpio;
26 unsigned int reg_shift;
27
28 struct mutex i2c_lock;
29 struct mutex irq_lock;
30
31 u8 *irq_enable;
32 u8 *irq_level;
33 u8 *irq_rise;
34 u8 *irq_fall;
35 u8 *irq_high;
36 u8 *irq_low;
37};
38
39static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
40{
41 int err;
42
43 err = i2c_smbus_read_byte_data(adnp->client, offset);
44 if (err < 0) {
45 dev_err(adnp->gpio.parent, "%s failed: %d\n",
46 "i2c_smbus_read_byte_data()", err);
47 return err;
48 }
49
50 *value = err;
51 return 0;
52}
53
54static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
55{
56 int err;
57
58 err = i2c_smbus_write_byte_data(adnp->client, offset, value);
59 if (err < 0) {
60 dev_err(adnp->gpio.parent, "%s failed: %d\n",
61 "i2c_smbus_write_byte_data()", err);
62 return err;
63 }
64
65 return 0;
66}
67
68static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
69{
70 struct adnp *adnp = gpiochip_get_data(chip);
71 unsigned int reg = offset >> adnp->reg_shift;
72 unsigned int pos = offset & 7;
73 u8 value;
74 int err;
75
76 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
77 if (err < 0)
78 return err;
79
80 return (value & BIT(pos)) ? 1 : 0;
81}
82
83static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
84{
85 unsigned int reg = offset >> adnp->reg_shift;
86 unsigned int pos = offset & 7;
87 int err;
88 u8 val;
89
90 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
91 if (err < 0)
92 return;
93
94 if (value)
95 val |= BIT(pos);
96 else
97 val &= ~BIT(pos);
98
99 adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
100}
101
102static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
103{
104 struct adnp *adnp = gpiochip_get_data(chip);
105
106 mutex_lock(&adnp->i2c_lock);
107 __adnp_gpio_set(adnp, offset, value);
108 mutex_unlock(&adnp->i2c_lock);
109}
110
111static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
112{
113 struct adnp *adnp = gpiochip_get_data(chip);
114 unsigned int reg = offset >> adnp->reg_shift;
115 unsigned int pos = offset & 7;
116 u8 value;
117 int err;
118
119 mutex_lock(&adnp->i2c_lock);
120
121 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
122 if (err < 0)
123 goto out;
124
125 value &= ~BIT(pos);
126
127 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
128 if (err < 0)
129 goto out;
130
131 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
132 if (err < 0)
133 goto out;
134
135 if (err & BIT(pos))
136 err = -EACCES;
137
138 err = 0;
139
140out:
141 mutex_unlock(&adnp->i2c_lock);
142 return err;
143}
144
145static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
146 int value)
147{
148 struct adnp *adnp = gpiochip_get_data(chip);
149 unsigned int reg = offset >> adnp->reg_shift;
150 unsigned int pos = offset & 7;
151 int err;
152 u8 val;
153
154 mutex_lock(&adnp->i2c_lock);
155
156 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
157 if (err < 0)
158 goto out;
159
160 val |= BIT(pos);
161
162 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
163 if (err < 0)
164 goto out;
165
166 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
167 if (err < 0)
168 goto out;
169
170 if (!(val & BIT(pos))) {
171 err = -EPERM;
172 goto out;
173 }
174
175 __adnp_gpio_set(adnp, offset, value);
176 err = 0;
177
178out:
179 mutex_unlock(&adnp->i2c_lock);
180 return err;
181}
182
183static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
184{
185 struct adnp *adnp = gpiochip_get_data(chip);
186 unsigned int num_regs = 1 << adnp->reg_shift, i, j;
187 int err;
188
189 for (i = 0; i < num_regs; i++) {
190 u8 ddr, plr, ier, isr;
191
192 mutex_lock(&adnp->i2c_lock);
193
194 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
195 if (err < 0)
196 goto unlock;
197
198 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
199 if (err < 0)
200 goto unlock;
201
202 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
203 if (err < 0)
204 goto unlock;
205
206 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
207 if (err < 0)
208 goto unlock;
209
210 mutex_unlock(&adnp->i2c_lock);
211
212 for (j = 0; j < 8; j++) {
213 unsigned int bit = (i << adnp->reg_shift) + j;
214 const char *direction = "input ";
215 const char *level = "low ";
216 const char *interrupt = "disabled";
217 const char *pending = "";
218
219 if (ddr & BIT(j))
220 direction = "output";
221
222 if (plr & BIT(j))
223 level = "high";
224
225 if (ier & BIT(j))
226 interrupt = "enabled ";
227
228 if (isr & BIT(j))
229 pending = "pending";
230
231 seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
232 direction, level, interrupt, pending);
233 }
234 }
235
236 return;
237
238unlock:
239 mutex_unlock(&adnp->i2c_lock);
240}
241
242static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios)
243{
244 struct gpio_chip *chip = &adnp->gpio;
245 int err;
246
247 adnp->reg_shift = get_count_order(num_gpios) - 3;
248
249 chip->direction_input = adnp_gpio_direction_input;
250 chip->direction_output = adnp_gpio_direction_output;
251 chip->get = adnp_gpio_get;
252 chip->set = adnp_gpio_set;
253 chip->can_sleep = true;
254
255 if (IS_ENABLED(CONFIG_DEBUG_FS))
256 chip->dbg_show = adnp_gpio_dbg_show;
257
258 chip->base = -1;
259 chip->ngpio = num_gpios;
260 chip->label = adnp->client->name;
261 chip->parent = &adnp->client->dev;
262 chip->of_node = chip->parent->of_node;
263 chip->owner = THIS_MODULE;
264
265 err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp);
266 if (err)
267 return err;
268
269 return 0;
270}
271
272static irqreturn_t adnp_irq(int irq, void *data)
273{
274 struct adnp *adnp = data;
275 unsigned int num_regs, i;
276
277 num_regs = 1 << adnp->reg_shift;
278
279 for (i = 0; i < num_regs; i++) {
280 unsigned int base = i << adnp->reg_shift, bit;
281 u8 changed, level, isr, ier;
282 unsigned long pending;
283 int err;
284
285 mutex_lock(&adnp->i2c_lock);
286
287 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
288 if (err < 0) {
289 mutex_unlock(&adnp->i2c_lock);
290 continue;
291 }
292
293 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
294 if (err < 0) {
295 mutex_unlock(&adnp->i2c_lock);
296 continue;
297 }
298
299 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
300 if (err < 0) {
301 mutex_unlock(&adnp->i2c_lock);
302 continue;
303 }
304
305 mutex_unlock(&adnp->i2c_lock);
306
307 /* determine pins that changed levels */
308 changed = level ^ adnp->irq_level[i];
309
310 /* compute edge-triggered interrupts */
311 pending = changed & ((adnp->irq_fall[i] & ~level) |
312 (adnp->irq_rise[i] & level));
313
314 /* add in level-triggered interrupts */
315 pending |= (adnp->irq_high[i] & level) |
316 (adnp->irq_low[i] & ~level);
317
318 /* mask out non-pending and disabled interrupts */
319 pending &= isr & ier;
320
321 for_each_set_bit(bit, &pending, 8) {
322 unsigned int child_irq;
323 child_irq = irq_find_mapping(adnp->gpio.irq.domain,
324 base + bit);
325 handle_nested_irq(child_irq);
326 }
327 }
328
329 return IRQ_HANDLED;
330}
331
332static void adnp_irq_mask(struct irq_data *d)
333{
334 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
335 struct adnp *adnp = gpiochip_get_data(gc);
336 unsigned int reg = d->hwirq >> adnp->reg_shift;
337 unsigned int pos = d->hwirq & 7;
338
339 adnp->irq_enable[reg] &= ~BIT(pos);
340}
341
342static void adnp_irq_unmask(struct irq_data *d)
343{
344 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
345 struct adnp *adnp = gpiochip_get_data(gc);
346 unsigned int reg = d->hwirq >> adnp->reg_shift;
347 unsigned int pos = d->hwirq & 7;
348
349 adnp->irq_enable[reg] |= BIT(pos);
350}
351
352static int adnp_irq_set_type(struct irq_data *d, unsigned int type)
353{
354 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
355 struct adnp *adnp = gpiochip_get_data(gc);
356 unsigned int reg = d->hwirq >> adnp->reg_shift;
357 unsigned int pos = d->hwirq & 7;
358
359 if (type & IRQ_TYPE_EDGE_RISING)
360 adnp->irq_rise[reg] |= BIT(pos);
361 else
362 adnp->irq_rise[reg] &= ~BIT(pos);
363
364 if (type & IRQ_TYPE_EDGE_FALLING)
365 adnp->irq_fall[reg] |= BIT(pos);
366 else
367 adnp->irq_fall[reg] &= ~BIT(pos);
368
369 if (type & IRQ_TYPE_LEVEL_HIGH)
370 adnp->irq_high[reg] |= BIT(pos);
371 else
372 adnp->irq_high[reg] &= ~BIT(pos);
373
374 if (type & IRQ_TYPE_LEVEL_LOW)
375 adnp->irq_low[reg] |= BIT(pos);
376 else
377 adnp->irq_low[reg] &= ~BIT(pos);
378
379 return 0;
380}
381
382static void adnp_irq_bus_lock(struct irq_data *d)
383{
384 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
385 struct adnp *adnp = gpiochip_get_data(gc);
386
387 mutex_lock(&adnp->irq_lock);
388}
389
390static void adnp_irq_bus_unlock(struct irq_data *d)
391{
392 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
393 struct adnp *adnp = gpiochip_get_data(gc);
394 unsigned int num_regs = 1 << adnp->reg_shift, i;
395
396 mutex_lock(&adnp->i2c_lock);
397
398 for (i = 0; i < num_regs; i++)
399 adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
400
401 mutex_unlock(&adnp->i2c_lock);
402 mutex_unlock(&adnp->irq_lock);
403}
404
405static struct irq_chip adnp_irq_chip = {
406 .name = "gpio-adnp",
407 .irq_mask = adnp_irq_mask,
408 .irq_unmask = adnp_irq_unmask,
409 .irq_set_type = adnp_irq_set_type,
410 .irq_bus_lock = adnp_irq_bus_lock,
411 .irq_bus_sync_unlock = adnp_irq_bus_unlock,
412};
413
414static int adnp_irq_setup(struct adnp *adnp)
415{
416 unsigned int num_regs = 1 << adnp->reg_shift, i;
417 struct gpio_chip *chip = &adnp->gpio;
418 int err;
419
420 mutex_init(&adnp->irq_lock);
421
422 /*
423 * Allocate memory to keep track of the current level and trigger
424 * modes of the interrupts. To avoid multiple allocations, a single
425 * large buffer is allocated and pointers are setup to point at the
426 * corresponding offsets. For consistency, the layout of the buffer
427 * is chosen to match the register layout of the hardware in that
428 * each segment contains the corresponding bits for all interrupts.
429 */
430 adnp->irq_enable = devm_kzalloc(chip->parent, num_regs * 6,
431 GFP_KERNEL);
432 if (!adnp->irq_enable)
433 return -ENOMEM;
434
435 adnp->irq_level = adnp->irq_enable + (num_regs * 1);
436 adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
437 adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
438 adnp->irq_high = adnp->irq_enable + (num_regs * 4);
439 adnp->irq_low = adnp->irq_enable + (num_regs * 5);
440
441 for (i = 0; i < num_regs; i++) {
442 /*
443 * Read the initial level of all pins to allow the emulation
444 * of edge triggered interrupts.
445 */
446 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
447 if (err < 0)
448 return err;
449
450 /* disable all interrupts */
451 err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
452 if (err < 0)
453 return err;
454
455 adnp->irq_enable[i] = 0x00;
456 }
457
458 err = devm_request_threaded_irq(chip->parent, adnp->client->irq,
459 NULL, adnp_irq,
460 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
461 dev_name(chip->parent), adnp);
462 if (err != 0) {
463 dev_err(chip->parent, "can't request IRQ#%d: %d\n",
464 adnp->client->irq, err);
465 return err;
466 }
467
468 err = gpiochip_irqchip_add_nested(chip,
469 &adnp_irq_chip,
470 0,
471 handle_simple_irq,
472 IRQ_TYPE_NONE);
473 if (err) {
474 dev_err(chip->parent,
475 "could not connect irqchip to gpiochip\n");
476 return err;
477 }
478
479 gpiochip_set_nested_irqchip(chip, &adnp_irq_chip, adnp->client->irq);
480
481 return 0;
482}
483
484static int adnp_i2c_probe(struct i2c_client *client,
485 const struct i2c_device_id *id)
486{
487 struct device_node *np = client->dev.of_node;
488 struct adnp *adnp;
489 u32 num_gpios;
490 int err;
491
492 err = of_property_read_u32(np, "nr-gpios", &num_gpios);
493 if (err < 0)
494 return err;
495
496 client->irq = irq_of_parse_and_map(np, 0);
497 if (!client->irq)
498 return -EPROBE_DEFER;
499
500 adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
501 if (!adnp)
502 return -ENOMEM;
503
504 mutex_init(&adnp->i2c_lock);
505 adnp->client = client;
506
507 err = adnp_gpio_setup(adnp, num_gpios);
508 if (err)
509 return err;
510
511 if (of_find_property(np, "interrupt-controller", NULL)) {
512 err = adnp_irq_setup(adnp);
513 if (err)
514 return err;
515 }
516
517 i2c_set_clientdata(client, adnp);
518
519 return 0;
520}
521
522static const struct i2c_device_id adnp_i2c_id[] = {
523 { "gpio-adnp" },
524 { },
525};
526MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
527
528static const struct of_device_id adnp_of_match[] = {
529 { .compatible = "ad,gpio-adnp", },
530 { },
531};
532MODULE_DEVICE_TABLE(of, adnp_of_match);
533
534static struct i2c_driver adnp_i2c_driver = {
535 .driver = {
536 .name = "gpio-adnp",
537 .of_match_table = adnp_of_match,
538 },
539 .probe = adnp_i2c_probe,
540 .id_table = adnp_i2c_id,
541};
542module_i2c_driver(adnp_i2c_driver);
543
544MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
545MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
546MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2011-2012 Avionic Design GmbH
4 */
5
6#include <linux/gpio/driver.h>
7#include <linux/i2c.h>
8#include <linux/interrupt.h>
9#include <linux/module.h>
10#include <linux/of_irq.h>
11#include <linux/seq_file.h>
12#include <linux/slab.h>
13
14#define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
15#define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
16#define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
17#define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
18#define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
19
20struct adnp {
21 struct i2c_client *client;
22 struct gpio_chip gpio;
23 unsigned int reg_shift;
24
25 struct mutex i2c_lock;
26 struct mutex irq_lock;
27
28 u8 *irq_enable;
29 u8 *irq_level;
30 u8 *irq_rise;
31 u8 *irq_fall;
32 u8 *irq_high;
33 u8 *irq_low;
34};
35
36static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
37{
38 int err;
39
40 err = i2c_smbus_read_byte_data(adnp->client, offset);
41 if (err < 0) {
42 dev_err(adnp->gpio.parent, "%s failed: %d\n",
43 "i2c_smbus_read_byte_data()", err);
44 return err;
45 }
46
47 *value = err;
48 return 0;
49}
50
51static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
52{
53 int err;
54
55 err = i2c_smbus_write_byte_data(adnp->client, offset, value);
56 if (err < 0) {
57 dev_err(adnp->gpio.parent, "%s failed: %d\n",
58 "i2c_smbus_write_byte_data()", err);
59 return err;
60 }
61
62 return 0;
63}
64
65static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
66{
67 struct adnp *adnp = gpiochip_get_data(chip);
68 unsigned int reg = offset >> adnp->reg_shift;
69 unsigned int pos = offset & 7;
70 u8 value;
71 int err;
72
73 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
74 if (err < 0)
75 return err;
76
77 return (value & BIT(pos)) ? 1 : 0;
78}
79
80static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
81{
82 unsigned int reg = offset >> adnp->reg_shift;
83 unsigned int pos = offset & 7;
84 int err;
85 u8 val;
86
87 err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
88 if (err < 0)
89 return;
90
91 if (value)
92 val |= BIT(pos);
93 else
94 val &= ~BIT(pos);
95
96 adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
97}
98
99static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
100{
101 struct adnp *adnp = gpiochip_get_data(chip);
102
103 mutex_lock(&adnp->i2c_lock);
104 __adnp_gpio_set(adnp, offset, value);
105 mutex_unlock(&adnp->i2c_lock);
106}
107
108static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
109{
110 struct adnp *adnp = gpiochip_get_data(chip);
111 unsigned int reg = offset >> adnp->reg_shift;
112 unsigned int pos = offset & 7;
113 u8 value;
114 int err;
115
116 mutex_lock(&adnp->i2c_lock);
117
118 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
119 if (err < 0)
120 goto out;
121
122 value &= ~BIT(pos);
123
124 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
125 if (err < 0)
126 goto out;
127
128 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
129 if (err < 0)
130 goto out;
131
132 if (value & BIT(pos)) {
133 err = -EPERM;
134 goto out;
135 }
136
137 err = 0;
138
139out:
140 mutex_unlock(&adnp->i2c_lock);
141 return err;
142}
143
144static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
145 int value)
146{
147 struct adnp *adnp = gpiochip_get_data(chip);
148 unsigned int reg = offset >> adnp->reg_shift;
149 unsigned int pos = offset & 7;
150 int err;
151 u8 val;
152
153 mutex_lock(&adnp->i2c_lock);
154
155 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
156 if (err < 0)
157 goto out;
158
159 val |= BIT(pos);
160
161 err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
162 if (err < 0)
163 goto out;
164
165 err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
166 if (err < 0)
167 goto out;
168
169 if (!(val & BIT(pos))) {
170 err = -EPERM;
171 goto out;
172 }
173
174 __adnp_gpio_set(adnp, offset, value);
175 err = 0;
176
177out:
178 mutex_unlock(&adnp->i2c_lock);
179 return err;
180}
181
182static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
183{
184 struct adnp *adnp = gpiochip_get_data(chip);
185 unsigned int num_regs = 1 << adnp->reg_shift, i, j;
186 int err;
187
188 for (i = 0; i < num_regs; i++) {
189 u8 ddr, plr, ier, isr;
190
191 mutex_lock(&adnp->i2c_lock);
192
193 err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
194 if (err < 0)
195 goto unlock;
196
197 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
198 if (err < 0)
199 goto unlock;
200
201 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
202 if (err < 0)
203 goto unlock;
204
205 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
206 if (err < 0)
207 goto unlock;
208
209 mutex_unlock(&adnp->i2c_lock);
210
211 for (j = 0; j < 8; j++) {
212 unsigned int bit = (i << adnp->reg_shift) + j;
213 const char *direction = "input ";
214 const char *level = "low ";
215 const char *interrupt = "disabled";
216 const char *pending = "";
217
218 if (ddr & BIT(j))
219 direction = "output";
220
221 if (plr & BIT(j))
222 level = "high";
223
224 if (ier & BIT(j))
225 interrupt = "enabled ";
226
227 if (isr & BIT(j))
228 pending = "pending";
229
230 seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
231 direction, level, interrupt, pending);
232 }
233 }
234
235 return;
236
237unlock:
238 mutex_unlock(&adnp->i2c_lock);
239}
240
241static irqreturn_t adnp_irq(int irq, void *data)
242{
243 struct adnp *adnp = data;
244 unsigned int num_regs, i;
245
246 num_regs = 1 << adnp->reg_shift;
247
248 for (i = 0; i < num_regs; i++) {
249 unsigned int base = i << adnp->reg_shift, bit;
250 u8 changed, level, isr, ier;
251 unsigned long pending;
252 int err;
253
254 mutex_lock(&adnp->i2c_lock);
255
256 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
257 if (err < 0) {
258 mutex_unlock(&adnp->i2c_lock);
259 continue;
260 }
261
262 err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
263 if (err < 0) {
264 mutex_unlock(&adnp->i2c_lock);
265 continue;
266 }
267
268 err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
269 if (err < 0) {
270 mutex_unlock(&adnp->i2c_lock);
271 continue;
272 }
273
274 mutex_unlock(&adnp->i2c_lock);
275
276 /* determine pins that changed levels */
277 changed = level ^ adnp->irq_level[i];
278
279 /* compute edge-triggered interrupts */
280 pending = changed & ((adnp->irq_fall[i] & ~level) |
281 (adnp->irq_rise[i] & level));
282
283 /* add in level-triggered interrupts */
284 pending |= (adnp->irq_high[i] & level) |
285 (adnp->irq_low[i] & ~level);
286
287 /* mask out non-pending and disabled interrupts */
288 pending &= isr & ier;
289
290 for_each_set_bit(bit, &pending, 8) {
291 unsigned int child_irq;
292 child_irq = irq_find_mapping(adnp->gpio.irq.domain,
293 base + bit);
294 handle_nested_irq(child_irq);
295 }
296 }
297
298 return IRQ_HANDLED;
299}
300
301static void adnp_irq_mask(struct irq_data *d)
302{
303 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
304 struct adnp *adnp = gpiochip_get_data(gc);
305 unsigned int reg = d->hwirq >> adnp->reg_shift;
306 unsigned int pos = d->hwirq & 7;
307
308 adnp->irq_enable[reg] &= ~BIT(pos);
309}
310
311static void adnp_irq_unmask(struct irq_data *d)
312{
313 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
314 struct adnp *adnp = gpiochip_get_data(gc);
315 unsigned int reg = d->hwirq >> adnp->reg_shift;
316 unsigned int pos = d->hwirq & 7;
317
318 adnp->irq_enable[reg] |= BIT(pos);
319}
320
321static int adnp_irq_set_type(struct irq_data *d, unsigned int type)
322{
323 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
324 struct adnp *adnp = gpiochip_get_data(gc);
325 unsigned int reg = d->hwirq >> adnp->reg_shift;
326 unsigned int pos = d->hwirq & 7;
327
328 if (type & IRQ_TYPE_EDGE_RISING)
329 adnp->irq_rise[reg] |= BIT(pos);
330 else
331 adnp->irq_rise[reg] &= ~BIT(pos);
332
333 if (type & IRQ_TYPE_EDGE_FALLING)
334 adnp->irq_fall[reg] |= BIT(pos);
335 else
336 adnp->irq_fall[reg] &= ~BIT(pos);
337
338 if (type & IRQ_TYPE_LEVEL_HIGH)
339 adnp->irq_high[reg] |= BIT(pos);
340 else
341 adnp->irq_high[reg] &= ~BIT(pos);
342
343 if (type & IRQ_TYPE_LEVEL_LOW)
344 adnp->irq_low[reg] |= BIT(pos);
345 else
346 adnp->irq_low[reg] &= ~BIT(pos);
347
348 return 0;
349}
350
351static void adnp_irq_bus_lock(struct irq_data *d)
352{
353 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
354 struct adnp *adnp = gpiochip_get_data(gc);
355
356 mutex_lock(&adnp->irq_lock);
357}
358
359static void adnp_irq_bus_unlock(struct irq_data *d)
360{
361 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
362 struct adnp *adnp = gpiochip_get_data(gc);
363 unsigned int num_regs = 1 << adnp->reg_shift, i;
364
365 mutex_lock(&adnp->i2c_lock);
366
367 for (i = 0; i < num_regs; i++)
368 adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
369
370 mutex_unlock(&adnp->i2c_lock);
371 mutex_unlock(&adnp->irq_lock);
372}
373
374static struct irq_chip adnp_irq_chip = {
375 .name = "gpio-adnp",
376 .irq_mask = adnp_irq_mask,
377 .irq_unmask = adnp_irq_unmask,
378 .irq_set_type = adnp_irq_set_type,
379 .irq_bus_lock = adnp_irq_bus_lock,
380 .irq_bus_sync_unlock = adnp_irq_bus_unlock,
381};
382
383static int adnp_irq_setup(struct adnp *adnp)
384{
385 unsigned int num_regs = 1 << adnp->reg_shift, i;
386 struct gpio_chip *chip = &adnp->gpio;
387 int err;
388
389 mutex_init(&adnp->irq_lock);
390
391 /*
392 * Allocate memory to keep track of the current level and trigger
393 * modes of the interrupts. To avoid multiple allocations, a single
394 * large buffer is allocated and pointers are setup to point at the
395 * corresponding offsets. For consistency, the layout of the buffer
396 * is chosen to match the register layout of the hardware in that
397 * each segment contains the corresponding bits for all interrupts.
398 */
399 adnp->irq_enable = devm_kcalloc(chip->parent, num_regs, 6,
400 GFP_KERNEL);
401 if (!adnp->irq_enable)
402 return -ENOMEM;
403
404 adnp->irq_level = adnp->irq_enable + (num_regs * 1);
405 adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
406 adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
407 adnp->irq_high = adnp->irq_enable + (num_regs * 4);
408 adnp->irq_low = adnp->irq_enable + (num_regs * 5);
409
410 for (i = 0; i < num_regs; i++) {
411 /*
412 * Read the initial level of all pins to allow the emulation
413 * of edge triggered interrupts.
414 */
415 err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
416 if (err < 0)
417 return err;
418
419 /* disable all interrupts */
420 err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
421 if (err < 0)
422 return err;
423
424 adnp->irq_enable[i] = 0x00;
425 }
426
427 err = devm_request_threaded_irq(chip->parent, adnp->client->irq,
428 NULL, adnp_irq,
429 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
430 dev_name(chip->parent), adnp);
431 if (err != 0) {
432 dev_err(chip->parent, "can't request IRQ#%d: %d\n",
433 adnp->client->irq, err);
434 return err;
435 }
436
437 return 0;
438}
439
440static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios,
441 bool is_irq_controller)
442{
443 struct gpio_chip *chip = &adnp->gpio;
444 int err;
445
446 adnp->reg_shift = get_count_order(num_gpios) - 3;
447
448 chip->direction_input = adnp_gpio_direction_input;
449 chip->direction_output = adnp_gpio_direction_output;
450 chip->get = adnp_gpio_get;
451 chip->set = adnp_gpio_set;
452 chip->can_sleep = true;
453
454 if (IS_ENABLED(CONFIG_DEBUG_FS))
455 chip->dbg_show = adnp_gpio_dbg_show;
456
457 chip->base = -1;
458 chip->ngpio = num_gpios;
459 chip->label = adnp->client->name;
460 chip->parent = &adnp->client->dev;
461 chip->of_node = chip->parent->of_node;
462 chip->owner = THIS_MODULE;
463
464 if (is_irq_controller) {
465 struct gpio_irq_chip *girq;
466
467 err = adnp_irq_setup(adnp);
468 if (err)
469 return err;
470
471 girq = &chip->irq;
472 girq->chip = &adnp_irq_chip;
473 /* This will let us handle the parent IRQ in the driver */
474 girq->parent_handler = NULL;
475 girq->num_parents = 0;
476 girq->parents = NULL;
477 girq->default_type = IRQ_TYPE_NONE;
478 girq->handler = handle_simple_irq;
479 girq->threaded = true;
480 }
481
482 err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp);
483 if (err)
484 return err;
485
486 return 0;
487}
488
489static int adnp_i2c_probe(struct i2c_client *client,
490 const struct i2c_device_id *id)
491{
492 struct device_node *np = client->dev.of_node;
493 struct adnp *adnp;
494 u32 num_gpios;
495 int err;
496
497 err = of_property_read_u32(np, "nr-gpios", &num_gpios);
498 if (err < 0)
499 return err;
500
501 client->irq = irq_of_parse_and_map(np, 0);
502 if (!client->irq)
503 return -EPROBE_DEFER;
504
505 adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
506 if (!adnp)
507 return -ENOMEM;
508
509 mutex_init(&adnp->i2c_lock);
510 adnp->client = client;
511
512 err = adnp_gpio_setup(adnp, num_gpios,
513 of_property_read_bool(np, "interrupt-controller"));
514 if (err)
515 return err;
516
517 i2c_set_clientdata(client, adnp);
518
519 return 0;
520}
521
522static const struct i2c_device_id adnp_i2c_id[] = {
523 { "gpio-adnp" },
524 { },
525};
526MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
527
528static const struct of_device_id adnp_of_match[] = {
529 { .compatible = "ad,gpio-adnp", },
530 { },
531};
532MODULE_DEVICE_TABLE(of, adnp_of_match);
533
534static struct i2c_driver adnp_i2c_driver = {
535 .driver = {
536 .name = "gpio-adnp",
537 .of_match_table = adnp_of_match,
538 },
539 .probe = adnp_i2c_probe,
540 .id_table = adnp_i2c_id,
541};
542module_i2c_driver(adnp_i2c_driver);
543
544MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
545MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
546MODULE_LICENSE("GPL");