1config ARM64
   2	def_bool y
   3	select ACPI_CCA_REQUIRED if ACPI
   4	select ACPI_GENERIC_GSI if ACPI
   5	select ACPI_GTDT if ACPI
   6	select ACPI_IORT if ACPI
   7	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
   8	select ACPI_MCFG if ACPI
   9	select ACPI_SPCR_TABLE if ACPI
  10	select ARCH_CLOCKSOURCE_DATA
 
 
 
 
 
 
 
 
  11	select ARCH_HAS_DEBUG_VIRTUAL
  12	select ARCH_HAS_DEVMEM_IS_ALLOWED
 
  13	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
  14	select ARCH_HAS_ELF_RANDOMIZE
  15	select ARCH_HAS_FORTIFY_SOURCE
  16	select ARCH_HAS_GCOV_PROFILE_ALL
  17	select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
  18	select ARCH_HAS_KCOV
 
  19	select ARCH_HAS_MEMBARRIER_SYNC_CORE
 
 
 
 
 
  20	select ARCH_HAS_SET_MEMORY
  21	select ARCH_HAS_SG_CHAIN
  22	select ARCH_HAS_STRICT_KERNEL_RWX
  23	select ARCH_HAS_STRICT_MODULE_RWX
 
 
 
 
  24	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
 
 
  25	select ARCH_HAVE_NMI_SAFE_CMPXCHG
  26	select ARCH_INLINE_READ_LOCK if !PREEMPT
  27	select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
  28	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
  29	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
  30	select ARCH_INLINE_READ_UNLOCK if !PREEMPT
  31	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
  32	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
  33	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
  34	select ARCH_INLINE_WRITE_LOCK if !PREEMPT
  35	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
  36	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
  37	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
  38	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
  39	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
  40	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
  41	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
 
 
 
 
 
 
 
 
 
 
 
  42	select ARCH_USE_CMPXCHG_LOCKREF
 
 
  43	select ARCH_USE_QUEUED_RWLOCKS
 
 
 
 
  44	select ARCH_SUPPORTS_MEMORY_FAILURE
 
 
 
 
  45	select ARCH_SUPPORTS_ATOMIC_RMW
 
  46	select ARCH_SUPPORTS_NUMA_BALANCING
  47	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
 
 
  48	select ARCH_WANT_FRAME_POINTERS
 
 
 
  49	select ARCH_HAS_UBSAN_SANITIZE_ALL
  50	select ARM_AMBA
  51	select ARM_ARCH_TIMER
  52	select ARM_GIC
  53	select AUDIT_ARCH_COMPAT_GENERIC
  54	select ARM_GIC_V2M if PCI
  55	select ARM_GIC_V3
  56	select ARM_GIC_V3_ITS if PCI
  57	select ARM_PSCI_FW
  58	select BUILDTIME_EXTABLE_SORT
  59	select CLONE_BACKWARDS
  60	select COMMON_CLK
  61	select CPU_PM if (SUSPEND || CPU_IDLE)
 
  62	select DCACHE_WORD_ACCESS
  63	select DMA_DIRECT_OPS
  64	select EDAC_SUPPORT
  65	select FRAME_POINTER
  66	select GENERIC_ALLOCATOR
  67	select GENERIC_ARCH_TOPOLOGY
  68	select GENERIC_CLOCKEVENTS
  69	select GENERIC_CLOCKEVENTS_BROADCAST
  70	select GENERIC_CPU_AUTOPROBE
 
  71	select GENERIC_EARLY_IOREMAP
 
  72	select GENERIC_IDLE_POLL_SETUP
 
  73	select GENERIC_IRQ_PROBE
  74	select GENERIC_IRQ_SHOW
  75	select GENERIC_IRQ_SHOW_LEVEL
 
  76	select GENERIC_PCI_IOMAP
 
  77	select GENERIC_SCHED_CLOCK
  78	select GENERIC_SMP_IDLE_THREAD
  79	select GENERIC_STRNCPY_FROM_USER
  80	select GENERIC_STRNLEN_USER
  81	select GENERIC_TIME_VSYSCALL
 
 
  82	select HANDLE_DOMAIN_IRQ
  83	select HARDIRQS_SW_RESEND
 
 
 
  84	select HAVE_ACPI_APEI if (ACPI && EFI)
  85	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
  86	select HAVE_ARCH_AUDITSYSCALL
  87	select HAVE_ARCH_BITREVERSE
 
  88	select HAVE_ARCH_HUGE_VMAP
  89	select HAVE_ARCH_JUMP_LABEL
 
  90	select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
 
 
 
 
  91	select HAVE_ARCH_KGDB
  92	select HAVE_ARCH_MMAP_RND_BITS
  93	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
 
 
 
  94	select HAVE_ARCH_SECCOMP_FILTER
 
  95	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
  96	select HAVE_ARCH_TRACEHOOK
  97	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
  98	select HAVE_ARCH_VMAP_STACK
  99	select HAVE_ARM_SMCCC
 
 100	select HAVE_EBPF_JIT
 101	select HAVE_C_RECORDMCOUNT
 102	select HAVE_CC_STACKPROTECTOR
 103	select HAVE_CMPXCHG_DOUBLE
 104	select HAVE_CMPXCHG_LOCAL
 105	select HAVE_CONTEXT_TRACKING
 106	select HAVE_DEBUG_BUGVERBOSE
 107	select HAVE_DEBUG_KMEMLEAK
 108	select HAVE_DMA_API_DEBUG
 109	select HAVE_DMA_CONTIGUOUS
 110	select HAVE_DYNAMIC_FTRACE
 
 
 
 
 111	select HAVE_EFFICIENT_UNALIGNED_ACCESS
 
 112	select HAVE_FTRACE_MCOUNT_RECORD
 113	select HAVE_FUNCTION_TRACER
 
 114	select HAVE_FUNCTION_GRAPH_TRACER
 115	select HAVE_GCC_PLUGINS
 116	select HAVE_GENERIC_DMA_COHERENT
 117	select HAVE_HW_BREAKPOINT if PERF_EVENTS
 118	select HAVE_IRQ_TIME_ACCOUNTING
 119	select HAVE_MEMBLOCK
 120	select HAVE_MEMBLOCK_NODE_MAP if NUMA
 121	select HAVE_NMI
 122	select HAVE_PATA_PLATFORM
 123	select HAVE_PERF_EVENTS
 124	select HAVE_PERF_REGS
 125	select HAVE_PERF_USER_STACK_DUMP
 126	select HAVE_REGS_AND_STACK_ACCESS_API
 127	select HAVE_RCU_TABLE_FREE
 
 
 
 
 128	select HAVE_SYSCALL_TRACEPOINTS
 129	select HAVE_KPROBES
 130	select HAVE_KRETPROBES
 
 131	select IOMMU_DMA if IOMMU_SUPPORT
 132	select IRQ_DOMAIN
 133	select IRQ_FORCED_THREADING
 
 134	select MODULES_USE_ELF_RELA
 135	select MULTI_IRQ_HANDLER
 136	select NO_BOOTMEM
 137	select OF
 138	select OF_EARLY_FLATTREE
 139	select OF_RESERVED_MEM
 140	select PCI_ECAM if ACPI
 
 141	select POWER_RESET
 142	select POWER_SUPPLY
 143	select REFCOUNT_FULL
 144	select SPARSE_IRQ
 
 145	select SYSCTL_EXCEPTION_TRACE
 146	select THREAD_INFO_IN_TASK
 
 147	help
 148	  ARM 64-bit (AArch64) Linux support.
 149
 150config 64BIT
 151	def_bool y
 152
 153config ARCH_PHYS_ADDR_T_64BIT
 154	def_bool y
 155
 156config MMU
 157	def_bool y
 158
 159config ARM64_PAGE_SHIFT
 160	int
 161	default 16 if ARM64_64K_PAGES
 162	default 14 if ARM64_16K_PAGES
 163	default 12
 164
 165config ARM64_CONT_SHIFT
 166	int
 167	default 5 if ARM64_64K_PAGES
 168	default 7 if ARM64_16K_PAGES
 169	default 4
 170
 
 
 
 
 
 
 171config ARCH_MMAP_RND_BITS_MIN
 172       default 14 if ARM64_64K_PAGES
 173       default 16 if ARM64_16K_PAGES
 174       default 18
 175
 176# max bits determined by the following formula:
 177#  VA_BITS - PAGE_SHIFT - 3
 178config ARCH_MMAP_RND_BITS_MAX
 179       default 19 if ARM64_VA_BITS=36
 180       default 24 if ARM64_VA_BITS=39
 181       default 27 if ARM64_VA_BITS=42
 182       default 30 if ARM64_VA_BITS=47
 183       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
 184       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
 185       default 33 if ARM64_VA_BITS=48
 186       default 14 if ARM64_64K_PAGES
 187       default 16 if ARM64_16K_PAGES
 188       default 18
 189
 190config ARCH_MMAP_RND_COMPAT_BITS_MIN
 191       default 7 if ARM64_64K_PAGES
 192       default 9 if ARM64_16K_PAGES
 193       default 11
 194
 195config ARCH_MMAP_RND_COMPAT_BITS_MAX
 196       default 16
 197
 198config NO_IOPORT_MAP
 199	def_bool y if !PCI
 200
 201config STACKTRACE_SUPPORT
 202	def_bool y
 203
 204config ILLEGAL_POINTER_VALUE
 205	hex
 206	default 0xdead000000000000
 207
 208config LOCKDEP_SUPPORT
 209	def_bool y
 210
 211config TRACE_IRQFLAGS_SUPPORT
 212	def_bool y
 213
 214config RWSEM_XCHGADD_ALGORITHM
 215	def_bool y
 216
 217config GENERIC_BUG
 218	def_bool y
 219	depends on BUG
 220
 221config GENERIC_BUG_RELATIVE_POINTERS
 222	def_bool y
 223	depends on GENERIC_BUG
 224
 225config GENERIC_HWEIGHT
 226	def_bool y
 227
 228config GENERIC_CSUM
 229        def_bool y
 230
 231config GENERIC_CALIBRATE_DELAY
 232	def_bool y
 233
 234config ZONE_DMA32
 235	def_bool y
 236
 237config HAVE_GENERIC_GUP
 238	def_bool y
 239
 240config ARCH_DMA_ADDR_T_64BIT
 241	def_bool y
 242
 243config NEED_DMA_MAP_STATE
 244	def_bool y
 245
 246config NEED_SG_DMA_LENGTH
 247	def_bool y
 248
 249config SMP
 250	def_bool y
 251
 252config SWIOTLB
 253	def_bool y
 254
 255config IOMMU_HELPER
 256	def_bool SWIOTLB
 257
 258config KERNEL_MODE_NEON
 259	def_bool y
 260
 261config FIX_EARLYCON_MEM
 262	def_bool y
 263
 264config PGTABLE_LEVELS
 265	int
 266	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
 267	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
 268	default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
 269	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
 270	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
 271	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
 272
 273config ARCH_SUPPORTS_UPROBES
 274	def_bool y
 275
 276config ARCH_PROC_KCORE_TEXT
 277	def_bool y
 278
 279config MULTI_IRQ_HANDLER
 280	def_bool y
 281
 282source "init/Kconfig"
 283
 284source "kernel/Kconfig.freezer"
 
 
 
 
 
 
 
 
 
 
 
 
 
 285
 286source "arch/arm64/Kconfig.platforms"
 287
 288menu "Bus support"
 289
 290config PCI
 291	bool "PCI support"
 292	help
 293	  This feature enables support for PCI bus system. If you say Y
 294	  here, the kernel will include drivers and infrastructure code
 295	  to support PCI bus devices.
 296
 297config PCI_DOMAINS
 298	def_bool PCI
 299
 300config PCI_DOMAINS_GENERIC
 301	def_bool PCI
 302
 303config PCI_SYSCALL
 304	def_bool PCI
 305
 306source "drivers/pci/Kconfig"
 307
 308endmenu
 309
 310menu "Kernel Features"
 311
 312menu "ARM errata workarounds via the alternatives framework"
 313
 
 
 
 314config ARM64_ERRATUM_826319
 315	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
 316	default y
 
 317	help
 318	  This option adds an alternative code sequence to work around ARM
 319	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
 320	  AXI master interface and an L2 cache.
 321
 322	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
 323	  and is unable to accept a certain write via this interface, it will
 324	  not progress on read data presented on the read data channel and the
 325	  system can deadlock.
 326
 327	  The workaround promotes data cache clean instructions to
 328	  data cache clean-and-invalidate.
 329	  Please note that this does not necessarily enable the workaround,
 330	  as it depends on the alternative framework, which will only patch
 331	  the kernel if an affected CPU is detected.
 332
 333	  If unsure, say Y.
 334
 335config ARM64_ERRATUM_827319
 336	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
 337	default y
 
 338	help
 339	  This option adds an alternative code sequence to work around ARM
 340	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
 341	  master interface and an L2 cache.
 342
 343	  Under certain conditions this erratum can cause a clean line eviction
 344	  to occur at the same time as another transaction to the same address
 345	  on the AMBA 5 CHI interface, which can cause data corruption if the
 346	  interconnect reorders the two transactions.
 347
 348	  The workaround promotes data cache clean instructions to
 349	  data cache clean-and-invalidate.
 350	  Please note that this does not necessarily enable the workaround,
 351	  as it depends on the alternative framework, which will only patch
 352	  the kernel if an affected CPU is detected.
 353
 354	  If unsure, say Y.
 355
 356config ARM64_ERRATUM_824069
 357	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
 358	default y
 
 359	help
 360	  This option adds an alternative code sequence to work around ARM
 361	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
 362	  to a coherent interconnect.
 363
 364	  If a Cortex-A53 processor is executing a store or prefetch for
 365	  write instruction at the same time as a processor in another
 366	  cluster is executing a cache maintenance operation to the same
 367	  address, then this erratum might cause a clean cache line to be
 368	  incorrectly marked as dirty.
 369
 370	  The workaround promotes data cache clean instructions to
 371	  data cache clean-and-invalidate.
 372	  Please note that this option does not necessarily enable the
 373	  workaround, as it depends on the alternative framework, which will
 374	  only patch the kernel if an affected CPU is detected.
 375
 376	  If unsure, say Y.
 377
 378config ARM64_ERRATUM_819472
 379	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
 380	default y
 
 381	help
 382	  This option adds an alternative code sequence to work around ARM
 383	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
 384	  present when it is connected to a coherent interconnect.
 385
 386	  If the processor is executing a load and store exclusive sequence at
 387	  the same time as a processor in another cluster is executing a cache
 388	  maintenance operation to the same address, then this erratum might
 389	  cause data corruption.
 390
 391	  The workaround promotes data cache clean instructions to
 392	  data cache clean-and-invalidate.
 393	  Please note that this does not necessarily enable the workaround,
 394	  as it depends on the alternative framework, which will only patch
 395	  the kernel if an affected CPU is detected.
 396
 397	  If unsure, say Y.
 398
 399config ARM64_ERRATUM_832075
 400	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
 401	default y
 402	help
 403	  This option adds an alternative code sequence to work around ARM
 404	  erratum 832075 on Cortex-A57 parts up to r1p2.
 405
 406	  Affected Cortex-A57 parts might deadlock when exclusive load/store
 407	  instructions to Write-Back memory are mixed with Device loads.
 408
 409	  The workaround is to promote device loads to use Load-Acquire
 410	  semantics.
 411	  Please note that this does not necessarily enable the workaround,
 412	  as it depends on the alternative framework, which will only patch
 413	  the kernel if an affected CPU is detected.
 414
 415	  If unsure, say Y.
 416
 417config ARM64_ERRATUM_834220
 418	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
 419	depends on KVM
 420	default y
 421	help
 422	  This option adds an alternative code sequence to work around ARM
 423	  erratum 834220 on Cortex-A57 parts up to r1p2.
 424
 425	  Affected Cortex-A57 parts might report a Stage 2 translation
 426	  fault as the result of a Stage 1 fault for load crossing a
 427	  page boundary when there is a permission or device memory
 428	  alignment fault at Stage 1 and a translation fault at Stage 2.
 429
 430	  The workaround is to verify that the Stage 1 translation
 431	  doesn't generate a fault before handling the Stage 2 fault.
 432	  Please note that this does not necessarily enable the workaround,
 433	  as it depends on the alternative framework, which will only patch
 434	  the kernel if an affected CPU is detected.
 435
 436	  If unsure, say Y.
 437
 438config ARM64_ERRATUM_845719
 439	bool "Cortex-A53: 845719: a load might read incorrect data"
 440	depends on COMPAT
 441	default y
 442	help
 443	  This option adds an alternative code sequence to work around ARM
 444	  erratum 845719 on Cortex-A53 parts up to r0p4.
 445
 446	  When running a compat (AArch32) userspace on an affected Cortex-A53
 447	  part, a load at EL0 from a virtual address that matches the bottom 32
 448	  bits of the virtual address used by a recent load at (AArch64) EL1
 449	  might return incorrect data.
 450
 451	  The workaround is to write the contextidr_el1 register on exception
 452	  return to a 32-bit task.
 453	  Please note that this does not necessarily enable the workaround,
 454	  as it depends on the alternative framework, which will only patch
 455	  the kernel if an affected CPU is detected.
 456
 457	  If unsure, say Y.
 458
 459config ARM64_ERRATUM_843419
 460	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
 461	default y
 462	select ARM64_MODULE_PLTS if MODULES
 463	help
 464	  This option links the kernel with '--fix-cortex-a53-843419' and
 465	  enables PLT support to replace certain ADRP instructions, which can
 466	  cause subsequent memory accesses to use an incorrect address on
 467	  Cortex-A53 parts up to r0p4.
 468
 469	  If unsure, say Y.
 470
 
 
 
 471config ARM64_ERRATUM_1024718
 472	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
 473	default y
 474	help
 475	  This option adds work around for Arm Cortex-A55 Erratum 1024718.
 476
 477	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
 478	  update of the hardware dirty bit when the DBM/AP bits are updated
 479	  without a break-before-make. The work around is to disable the usage
 480	  of hardware DBM locally on the affected cores. CPUs not affected by
 481	  erratum will continue to use the feature.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 482
 483	  If unsure, say Y.
 484
 485config CAVIUM_ERRATUM_22375
 486	bool "Cavium erratum 22375, 24313"
 487	default y
 488	help
 489	  Enable workaround for erratum 22375, 24313.
 490
 491	  This implements two gicv3-its errata workarounds for ThunderX. Both
 492	  with small impact affecting only ITS table allocation.
 493
 494	    erratum 22375: only alloc 8MB table size
 495	    erratum 24313: ignore memory access type
 496
 497	  The fixes are in ITS initialization and basically ignore memory access
 498	  type and table size provided by the TYPER and BASER registers.
 499
 500	  If unsure, say Y.
 501
 502config CAVIUM_ERRATUM_23144
 503	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
 504	depends on NUMA
 505	default y
 506	help
 507	  ITS SYNC command hang for cross node io and collections/cpu mapping.
 508
 509	  If unsure, say Y.
 510
 511config CAVIUM_ERRATUM_23154
 512	bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
 513	default y
 514	help
 515	  The gicv3 of ThunderX requires a modified version for
 516	  reading the IAR status to ensure data synchronization
 517	  (access to icc_iar1_el1 is not sync'ed before and after).
 518
 519	  If unsure, say Y.
 520
 521config CAVIUM_ERRATUM_27456
 522	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
 523	default y
 524	help
 525	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
 526	  instructions may cause the icache to become corrupted if it
 527	  contains data for a non-current ASID.  The fix is to
 528	  invalidate the icache when changing the mm context.
 529
 530	  If unsure, say Y.
 531
 532config CAVIUM_ERRATUM_30115
 533	bool "Cavium erratum 30115: Guest may disable interrupts in host"
 534	default y
 535	help
 536	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
 537	  1.2, and T83 Pass 1.0, KVM guest execution may disable
 538	  interrupts in host. Trapping both GICv3 group-0 and group-1
 539	  accesses sidesteps the issue.
 540
 541	  If unsure, say Y.
 542
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 543config QCOM_FALKOR_ERRATUM_1003
 544	bool "Falkor E1003: Incorrect translation due to ASID change"
 545	default y
 546	help
 547	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
 548	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
 549	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
 550	  then only for entries in the walk cache, since the leaf translation
 551	  is unchanged. Work around the erratum by invalidating the walk cache
 552	  entries for the trampoline before entering the kernel proper.
 553
 554config QCOM_FALKOR_ERRATUM_1009
 555	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
 556	default y
 
 557	help
 558	  On Falkor v1, the CPU may prematurely complete a DSB following a
 559	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
 560	  one more time to fix the issue.
 561
 562	  If unsure, say Y.
 563
 564config QCOM_QDF2400_ERRATUM_0065
 565	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
 566	default y
 567	help
 568	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
 569	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
 570	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
 571
 572	  If unsure, say Y.
 573
 574config SOCIONEXT_SYNQUACER_PREITS
 575	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
 576	default y
 577	help
 578	  Socionext Synquacer SoCs implement a separate h/w block to generate
 579	  MSI doorbell writes with non-zero values for the device ID.
 
 580
 581	  If unsure, say Y.
 582
 583config HISILICON_ERRATUM_161600802
 584	bool "Hip07 161600802: Erroneous redistributor VLPI base"
 585	default y
 586	help
 587	  The HiSilicon Hip07 SoC usees the wrong redistributor base
 588	  when issued ITS commands such as VMOVP and VMAPP, and requires
 589	  a 128kB offset to be applied to the target address in this commands.
 590
 591	  If unsure, say Y.
 592
 593config QCOM_FALKOR_ERRATUM_E1041
 594	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
 595	default y
 596	help
 597	  Falkor CPU may speculatively fetch instructions from an improper
 598	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
 599	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
 600
 601	  If unsure, say Y.
 602
 603endmenu
 604
 605
 606choice
 607	prompt "Page size"
 608	default ARM64_4K_PAGES
 609	help
 610	  Page size (translation granule) configuration.
 611
 612config ARM64_4K_PAGES
 613	bool "4KB"
 614	help
 615	  This feature enables 4KB pages support.
 616
 617config ARM64_16K_PAGES
 618	bool "16KB"
 619	help
 620	  The system will use 16KB pages support. AArch32 emulation
 621	  requires applications compiled with 16K (or a multiple of 16K)
 622	  aligned segments.
 623
 624config ARM64_64K_PAGES
 625	bool "64KB"
 626	help
 627	  This feature enables 64KB pages support (4KB by default)
 628	  allowing only two levels of page tables and faster TLB
 629	  look-up. AArch32 emulation requires applications compiled
 630	  with 64K aligned segments.
 631
 632endchoice
 633
 634choice
 635	prompt "Virtual address space size"
 636	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
 637	default ARM64_VA_BITS_47 if ARM64_16K_PAGES
 638	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
 639	help
 640	  Allows choosing one of multiple possible virtual address
 641	  space sizes. The level of translation table is determined by
 642	  a combination of page size and virtual address space size.
 643
 644config ARM64_VA_BITS_36
 645	bool "36-bit" if EXPERT
 646	depends on ARM64_16K_PAGES
 647
 648config ARM64_VA_BITS_39
 649	bool "39-bit"
 650	depends on ARM64_4K_PAGES
 651
 652config ARM64_VA_BITS_42
 653	bool "42-bit"
 654	depends on ARM64_64K_PAGES
 655
 656config ARM64_VA_BITS_47
 657	bool "47-bit"
 658	depends on ARM64_16K_PAGES
 659
 660config ARM64_VA_BITS_48
 661	bool "48-bit"
 662
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 663endchoice
 664
 
 
 
 
 
 
 
 
 
 
 
 
 
 665config ARM64_VA_BITS
 666	int
 667	default 36 if ARM64_VA_BITS_36
 668	default 39 if ARM64_VA_BITS_39
 669	default 42 if ARM64_VA_BITS_42
 670	default 47 if ARM64_VA_BITS_47
 671	default 48 if ARM64_VA_BITS_48
 
 672
 673choice
 674	prompt "Physical address space size"
 675	default ARM64_PA_BITS_48
 676	help
 677	  Choose the maximum physical address range that the kernel will
 678	  support.
 679
 680config ARM64_PA_BITS_48
 681	bool "48-bit"
 682
 683config ARM64_PA_BITS_52
 684	bool "52-bit (ARMv8.2)"
 685	depends on ARM64_64K_PAGES
 686	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
 687	help
 688	  Enable support for a 52-bit physical address space, introduced as
 689	  part of the ARMv8.2-LPA extension.
 690
 691	  With this enabled, the kernel will also continue to work on CPUs that
 692	  do not support ARMv8.2-LPA, but with some added memory overhead (and
 693	  minor performance overhead).
 694
 695endchoice
 696
 697config ARM64_PA_BITS
 698	int
 699	default 48 if ARM64_PA_BITS_48
 700	default 52 if ARM64_PA_BITS_52
 701
 
 
 
 
 
 
 
 
 702config CPU_BIG_ENDIAN
 703       bool "Build big-endian kernel"
 704       help
 705         Say Y if you plan on running a kernel in big-endian mode.
 
 
 
 
 
 
 
 
 
 706
 707config SCHED_MC
 708	bool "Multi-core scheduler support"
 709	help
 710	  Multi-core scheduler support improves the CPU scheduler's decision
 711	  making when dealing with multi-core CPU chips at a cost of slightly
 712	  increased overhead in some places. If unsure say N here.
 713
 714config SCHED_SMT
 715	bool "SMT scheduler support"
 716	help
 717	  Improves the CPU scheduler's decision making when dealing with
 718	  MultiThreading at a cost of slightly increased overhead in some
 719	  places. If unsure say N here.
 720
 721config NR_CPUS
 722	int "Maximum number of CPUs (2-4096)"
 723	range 2 4096
 724	# These have to remain sorted largest to smallest
 725	default "64"
 726
 727config HOTPLUG_CPU
 728	bool "Support for hot-pluggable CPUs"
 729	select GENERIC_IRQ_MIGRATION
 730	help
 731	  Say Y here to experiment with turning CPUs off and on.  CPUs
 732	  can be controlled through /sys/devices/system/cpu.
 733
 734# Common NUMA Features
 735config NUMA
 736	bool "Numa Memory Allocation and Scheduler Support"
 
 737	select ACPI_NUMA if ACPI
 738	select OF_NUMA
 739	help
 740	  Enable NUMA (Non Uniform Memory Access) support.
 741
 742	  The kernel will try to allocate memory used by a CPU on the
 743	  local memory of the CPU and add some more
 744	  NUMA awareness to the kernel.
 745
 746config NODES_SHIFT
 747	int "Maximum NUMA Nodes (as a power of 2)"
 748	range 1 10
 749	default "2"
 750	depends on NEED_MULTIPLE_NODES
 751	help
 752	  Specify the maximum number of NUMA Nodes available on the target
 753	  system.  Increases memory reserved to accommodate various tables.
 754
 755config USE_PERCPU_NUMA_NODE_ID
 756	def_bool y
 757	depends on NUMA
 758
 759config HAVE_SETUP_PER_CPU_AREA
 760	def_bool y
 761	depends on NUMA
 762
 763config NEED_PER_CPU_EMBED_FIRST_CHUNK
 764	def_bool y
 765	depends on NUMA
 766
 767config HOLES_IN_ZONE
 768	def_bool y
 769	depends on NUMA
 770
 771source kernel/Kconfig.preempt
 772source kernel/Kconfig.hz
 773
 774config ARCH_SUPPORTS_DEBUG_PAGEALLOC
 775	def_bool y
 776
 777config ARCH_HAS_HOLES_MEMORYMODEL
 778	def_bool y if SPARSEMEM
 779
 780config ARCH_SPARSEMEM_ENABLE
 781	def_bool y
 782	select SPARSEMEM_VMEMMAP_ENABLE
 783
 784config ARCH_SPARSEMEM_DEFAULT
 785	def_bool ARCH_SPARSEMEM_ENABLE
 786
 787config ARCH_SELECT_MEMORY_MODEL
 788	def_bool ARCH_SPARSEMEM_ENABLE
 789
 790config HAVE_ARCH_PFN_VALID
 791	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
 792
 793config HW_PERF_EVENTS
 794	def_bool y
 795	depends on ARM_PMU
 796
 797config SYS_SUPPORTS_HUGETLBFS
 798	def_bool y
 799
 800config ARCH_WANT_HUGE_PMD_SHARE
 801	def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
 802
 803config ARCH_HAS_CACHE_LINE_SIZE
 804	def_bool y
 805
 806source "mm/Kconfig"
 807
 808config SECCOMP
 809	bool "Enable seccomp to safely compute untrusted bytecode"
 810	---help---
 811	  This kernel feature is useful for number crunching applications
 812	  that may need to compute untrusted bytecode during their
 813	  execution. By using pipes or other transports made available to
 814	  the process as file descriptors supporting the read/write
 815	  syscalls, it's possible to isolate those applications in
 816	  their own address space using seccomp. Once seccomp is
 817	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
 818	  and the task is only allowed to execute a few safe syscalls
 819	  defined by each seccomp mode.
 820
 821config PARAVIRT
 822	bool "Enable paravirtualization code"
 823	help
 824	  This changes the kernel so it can modify itself when it is run
 825	  under a hypervisor, potentially improving performance significantly
 826	  over full virtualization.
 827
 828config PARAVIRT_TIME_ACCOUNTING
 829	bool "Paravirtual steal time accounting"
 830	select PARAVIRT
 831	default n
 832	help
 833	  Select this option to enable fine granularity task steal time
 834	  accounting. Time spent executing other tasks in parallel with
 835	  the current vCPU is discounted from the vCPU power. To account for
 836	  that, there can be a small performance impact.
 837
 838	  If in doubt, say N here.
 839
 840config KEXEC
 841	depends on PM_SLEEP_SMP
 842	select KEXEC_CORE
 843	bool "kexec system call"
 844	---help---
 845	  kexec is a system call that implements the ability to shutdown your
 846	  current kernel, and to start another kernel.  It is like a reboot
 847	  but it is independent of the system firmware.   And like a reboot
 848	  you can start any kernel with it, not just Linux.
 849
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 850config CRASH_DUMP
 851	bool "Build kdump crash kernel"
 852	help
 853	  Generate crash dump after being started by kexec. This should
 854	  be normally only set in special crash dump kernels which are
 855	  loaded in the main kernel with kexec-tools into a specially
 856	  reserved region and then later executed after a crash by
 857	  kdump/kexec.
 858
 859	  For more details see Documentation/kdump/kdump.txt
 
 
 
 
 860
 861config XEN_DOM0
 862	def_bool y
 863	depends on XEN
 864
 865config XEN
 866	bool "Xen guest support on ARM64"
 867	depends on ARM64 && OF
 868	select SWIOTLB_XEN
 869	select PARAVIRT
 870	help
 871	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
 872
 873config FORCE_MAX_ZONEORDER
 874	int
 875	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
 876	default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
 877	default "11"
 878	help
 879	  The kernel memory allocator divides physically contiguous memory
 880	  blocks into "zones", where each zone is a power of two number of
 881	  pages.  This option selects the largest power of two that the kernel
 882	  keeps in the memory allocator.  If you need to allocate very large
 883	  blocks of physically contiguous memory, then you may need to
 884	  increase this value.
 885
 886	  This config option is actually maximum order plus one. For example,
 887	  a value of 11 means that the largest free memory block is 2^10 pages.
 888
 889	  We make sure that we can allocate upto a HugePage size for each configuration.
 890	  Hence we have :
 891		MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
 892
 893	  However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
 894	  4M allocations matching the default size used by generic code.
 895
 896config UNMAP_KERNEL_AT_EL0
 897	bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
 898	default y
 899	help
 900	  Speculation attacks against some high-performance processors can
 901	  be used to bypass MMU permission checks and leak kernel data to
 902	  userspace. This can be defended against by unmapping the kernel
 903	  when running in userspace, mapping it back in on exception entry
 904	  via a trampoline page in the vector table.
 905
 906	  If unsure, say Y.
 907
 908config HARDEN_BRANCH_PREDICTOR
 909	bool "Harden the branch predictor against aliasing attacks" if EXPERT
 910	default y
 911	help
 912	  Speculation attacks against some high-performance processors rely on
 913	  being able to manipulate the branch predictor for a victim context by
 914	  executing aliasing branches in the attacker context.  Such attacks
 915	  can be partially mitigated against by clearing internal branch
 916	  predictor state and limiting the prediction logic in some situations.
 
 917
 918	  This config option will take CPU-specific actions to harden the
 919	  branch predictor against aliasing attacks and may rely on specific
 920	  instruction sequences or control bits being set by the system
 921	  firmware.
 922
 923	  If unsure, say Y.
 
 
 
 
 
 
 924
 925config HARDEN_EL2_VECTORS
 926	bool "Harden EL2 vector mapping against system register leak" if EXPERT
 927	default y
 928	help
 929	  Speculation attacks against some high-performance processors can
 930	  be used to leak privileged information such as the vector base
 931	  register, resulting in a potential defeat of the EL2 layout
 932	  randomization.
 933
 934	  This config option will map the vectors to a fixed location,
 935	  independent of the EL2 code mapping, so that revealing VBAR_EL2
 936	  to an attacker does not give away any extra information. This
 937	  only gets enabled on affected CPUs.
 938
 939	  If unsure, say Y.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 940
 941menuconfig ARMV8_DEPRECATED
 942	bool "Emulate deprecated/obsolete ARMv8 instructions"
 943	depends on COMPAT
 944	depends on SYSCTL
 945	help
 946	  Legacy software support may require certain instructions
 947	  that have been deprecated or obsoleted in the architecture.
 948
 949	  Enable this config to enable selective emulation of these
 950	  features.
 951
 952	  If unsure, say Y
 953
 954if ARMV8_DEPRECATED
 955
 956config SWP_EMULATION
 957	bool "Emulate SWP/SWPB instructions"
 958	help
 959	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
 960	  they are always undefined. Say Y here to enable software
 961	  emulation of these instructions for userspace using LDXR/STXR.
 
 
 962
 963	  In some older versions of glibc [<=2.8] SWP is used during futex
 964	  trylock() operations with the assumption that the code will not
 965	  be preempted. This invalid assumption may be more likely to fail
 966	  with SWP emulation enabled, leading to deadlock of the user
 967	  application.
 968
 969	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
 970	  on an external transaction monitoring block called a global
 971	  monitor to maintain update atomicity. If your system does not
 972	  implement a global monitor, this option can cause programs that
 973	  perform SWP operations to uncached memory to deadlock.
 974
 975	  If unsure, say Y
 976
 977config CP15_BARRIER_EMULATION
 978	bool "Emulate CP15 Barrier instructions"
 979	help
 980	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
 981	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
 982	  strongly recommended to use the ISB, DSB, and DMB
 983	  instructions instead.
 984
 985	  Say Y here to enable software emulation of these
 986	  instructions for AArch32 userspace code. When this option is
 987	  enabled, CP15 barrier usage is traced which can help
 988	  identify software that needs updating.
 
 989
 990	  If unsure, say Y
 991
 992config SETEND_EMULATION
 993	bool "Emulate SETEND instruction"
 994	help
 995	  The SETEND instruction alters the data-endianness of the
 996	  AArch32 EL0, and is deprecated in ARMv8.
 997
 998	  Say Y here to enable software emulation of the instruction
 999	  for AArch32 userspace code.
 
1000
1001	  Note: All the cpus on the system must have mixed endian support at EL0
1002	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1003	  endian - is hotplugged in after this feature has been enabled, there could
1004	  be unexpected results in the applications.
1005
1006	  If unsure, say Y
1007endif
1008
1009config ARM64_SW_TTBR0_PAN
1010	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1011	help
1012	  Enabling this option prevents the kernel from accessing
1013	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1014	  zeroed area and reserved ASID. The user access routines
1015	  restore the valid TTBR0_EL1 temporarily.
1016
1017menu "ARMv8.1 architectural features"
1018
1019config ARM64_HW_AFDBM
1020	bool "Support for hardware updates of the Access and Dirty page flags"
1021	default y
1022	help
1023	  The ARMv8.1 architecture extensions introduce support for
1024	  hardware updates of the access and dirty information in page
1025	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1026	  capable processors, accesses to pages with PTE_AF cleared will
1027	  set this bit instead of raising an access flag fault.
1028	  Similarly, writes to read-only pages with the DBM bit set will
1029	  clear the read-only bit (AP[2]) instead of raising a
1030	  permission fault.
1031
1032	  Kernels built with this configuration option enabled continue
1033	  to work on pre-ARMv8.1 hardware and the performance impact is
1034	  minimal. If unsure, say Y.
1035
1036config ARM64_PAN
1037	bool "Enable support for Privileged Access Never (PAN)"
1038	default y
1039	help
1040	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1041	 prevents the kernel or hypervisor from accessing user-space (EL0)
1042	 memory directly.
1043
1044	 Choosing this option will cause any unprotected (not using
1045	 copy_to_user et al) memory access to fail with a permission fault.
1046
1047	 The feature is detected at runtime, and will remain as a 'nop'
1048	 instruction if the cpu does not implement the feature.
1049
 
 
 
 
 
 
1050config ARM64_LSE_ATOMICS
 
 
 
 
 
1051	bool "Atomic instructions"
 
 
1052	help
1053	  As part of the Large System Extensions, ARMv8.1 introduces new
1054	  atomic instructions that are designed specifically to scale in
1055	  very large systems.
1056
1057	  Say Y here to make use of these instructions for the in-kernel
1058	  atomic routines. This incurs a small overhead on CPUs that do
1059	  not support these instructions and requires the kernel to be
1060	  built with binutils >= 2.25.
1061
1062config ARM64_VHE
1063	bool "Enable support for Virtualization Host Extensions (VHE)"
1064	default y
1065	help
1066	  Virtualization Host Extensions (VHE) allow the kernel to run
1067	  directly at EL2 (instead of EL1) on processors that support
1068	  it. This leads to better performance for KVM, as they reduce
1069	  the cost of the world switch.
1070
1071	  Selecting this option allows the VHE feature to be detected
1072	  at runtime, and does not affect processors that do not
1073	  implement this feature.
1074
1075endmenu
1076
1077menu "ARMv8.2 architectural features"
1078
1079config ARM64_UAO
1080	bool "Enable support for User Access Override (UAO)"
1081	default y
1082	help
1083	  User Access Override (UAO; part of the ARMv8.2 Extensions)
1084	  causes the 'unprivileged' variant of the load/store instructions to
1085	  be overridden to be privileged.
1086
1087	  This option changes get_user() and friends to use the 'unprivileged'
1088	  variant of the load/store instructions. This ensures that user-space
1089	  really did have access to the supplied memory. When addr_limit is
1090	  set to kernel memory the UAO bit will be set, allowing privileged
1091	  access to kernel memory.
1092
1093	  Choosing this option will cause copy_to_user() et al to use user-space
1094	  memory permissions.
1095
1096	  The feature is detected at runtime, the kernel will use the
1097	  regular load/store instructions if the cpu does not implement the
1098	  feature.
1099
1100config ARM64_PMEM
1101	bool "Enable support for persistent memory"
1102	select ARCH_HAS_PMEM_API
1103	select ARCH_HAS_UACCESS_FLUSHCACHE
1104	help
1105	  Say Y to enable support for the persistent memory API based on the
1106	  ARMv8.2 DCPoP feature.
1107
1108	  The feature is detected at runtime, and the kernel will use DC CVAC
1109	  operations if DC CVAP is not supported (following the behaviour of
1110	  DC CVAP itself if the system does not define a point of persistence).
1111
1112config ARM64_RAS_EXTN
1113	bool "Enable support for RAS CPU Extensions"
1114	default y
1115	help
1116	  CPUs that support the Reliability, Availability and Serviceability
1117	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1118	  errors, classify them and report them to software.
1119
1120	  On CPUs with these extensions system software can use additional
1121	  barriers to determine if faults are pending and read the
1122	  classification from a new set of registers.
1123
1124	  Selecting this feature will allow the kernel to use these barriers
1125	  and access the new registers if the system supports the extension.
1126	  Platform RAS features may additionally depend on firmware support.
1127
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1128endmenu
1129
1130config ARM64_SVE
1131	bool "ARM Scalable Vector Extension support"
1132	default y
1133	help
1134	  The Scalable Vector Extension (SVE) is an extension to the AArch64
1135	  execution state which complements and extends the SIMD functionality
1136	  of the base architecture to support much larger vectors and to enable
1137	  additional vectorisation opportunities.
1138
1139	  To enable use of this extension on CPUs that implement it, say Y.
1140
 
 
 
1141	  Note that for architectural reasons, firmware _must_ implement SVE
1142	  support when running on SVE capable hardware.  The required support
1143	  is present in:
1144
1145	    * version 1.5 and later of the ARM Trusted Firmware
1146	    * the AArch64 boot wrapper since commit 5e1261e08abf
1147	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
1148
1149	  For other firmware implementations, consult the firmware documentation
1150	  or vendor.
1151
1152	  If you need the kernel to boot on SVE-capable hardware with broken
1153	  firmware, you may need to say N here until you get your firmware
1154	  fixed.  Otherwise, you may experience firmware panics or lockups when
1155	  booting the kernel.  If unsure and you are not observing these
1156	  symptoms, you should assume that it is safe to say Y.
1157
1158config ARM64_MODULE_PLTS
1159	bool
 
1160	select HAVE_MOD_ARCH_SPECIFIC
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1161
1162config RELOCATABLE
1163	bool
 
 
1164	help
1165	  This builds the kernel as a Position Independent Executable (PIE),
1166	  which retains all relocation metadata required to relocate the
1167	  kernel binary at runtime to a different virtual address than the
1168	  address it was linked at.
1169	  Since AArch64 uses the RELA relocation format, this requires a
1170	  relocation pass at runtime even if the kernel is loaded at the
1171	  same address it was linked at.
1172
1173config RANDOMIZE_BASE
1174	bool "Randomize the address of the kernel image"
1175	select ARM64_MODULE_PLTS if MODULES
1176	select RELOCATABLE
1177	help
1178	  Randomizes the virtual address at which the kernel image is
1179	  loaded, as a security feature that deters exploit attempts
1180	  relying on knowledge of the location of kernel internals.
1181
1182	  It is the bootloader's job to provide entropy, by passing a
1183	  random u64 value in /chosen/kaslr-seed at kernel entry.
1184
1185	  When booting via the UEFI stub, it will invoke the firmware's
1186	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1187	  to the kernel proper. In addition, it will randomise the physical
1188	  location of the kernel Image as well.
1189
1190	  If unsure, say N.
1191
1192config RANDOMIZE_MODULE_REGION_FULL
1193	bool "Randomize the module region over a 4 GB range"
1194	depends on RANDOMIZE_BASE
1195	default y
1196	help
1197	  Randomizes the location of the module region inside a 4 GB window
1198	  covering the core kernel. This way, it is less likely for modules
1199	  to leak information about the location of core kernel data structures
1200	  but it does imply that function calls between modules and the core
1201	  kernel will need to be resolved via veneers in the module PLT.
1202
1203	  When this option is not set, the module region will be randomized over
1204	  a limited range that contains the [_stext, _etext] interval of the
1205	  core kernel, so branch relocations are always in range.
 
 
 
 
 
 
 
 
 
 
1206
1207endmenu
1208
1209menu "Boot options"
1210
1211config ARM64_ACPI_PARKING_PROTOCOL
1212	bool "Enable support for the ARM64 ACPI parking protocol"
1213	depends on ACPI
1214	help
1215	  Enable support for the ARM64 ACPI parking protocol. If disabled
1216	  the kernel will not allow booting through the ARM64 ACPI parking
1217	  protocol even if the corresponding data is present in the ACPI
1218	  MADT table.
1219
1220config CMDLINE
1221	string "Default kernel command string"
1222	default ""
1223	help
1224	  Provide a set of default command-line options at build time by
1225	  entering them here. As a minimum, you should specify the the
1226	  root device (e.g. root=/dev/nfs).
1227
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1228config CMDLINE_FORCE
1229	bool "Always use the default kernel command string"
1230	help
1231	  Always use the default kernel command string, even if the boot
1232	  loader passes other arguments to the kernel.
1233	  This is useful if you cannot or don't want to change the
1234	  command-line options your boot loader passes to the kernel.
1235
 
 
1236config EFI_STUB
1237	bool
1238
1239config EFI
1240	bool "UEFI runtime support"
1241	depends on OF && !CPU_BIG_ENDIAN
1242	depends on KERNEL_MODE_NEON
 
1243	select LIBFDT
1244	select UCS2_STRING
1245	select EFI_PARAMS_FROM_FDT
1246	select EFI_RUNTIME_WRAPPERS
1247	select EFI_STUB
1248	select EFI_ARMSTUB
 
1249	default y
1250	help
1251	  This option provides support for runtime services provided
1252	  by UEFI firmware (such as non-volatile variables, realtime
1253          clock, and platform reset). A UEFI stub is also provided to
1254	  allow the kernel to be booted as an EFI application. This
1255	  is only useful on systems that have UEFI firmware.
1256
1257config DMI
1258	bool "Enable support for SMBIOS (DMI) tables"
1259	depends on EFI
1260	default y
1261	help
1262	  This enables SMBIOS/DMI feature for systems.
1263
1264	  This option is only useful on systems that have UEFI firmware.
1265	  However, even with this option, the resultant kernel should
1266	  continue to boot on existing non-UEFI platforms.
1267
1268endmenu
1269
1270menu "Userspace binary formats"
1271
1272source "fs/Kconfig.binfmt"
1273
1274config COMPAT
1275	bool "Kernel support for 32-bit EL0"
1276	depends on ARM64_4K_PAGES || EXPERT
1277	select COMPAT_BINFMT_ELF if BINFMT_ELF
1278	select HAVE_UID16
1279	select OLD_SIGSUSPEND3
1280	select COMPAT_OLD_SIGACTION
1281	help
1282	  This option enables support for a 32-bit EL0 running under a 64-bit
1283	  kernel at EL1. AArch32-specific components such as system calls,
1284	  the user helper functions, VFP support and the ptrace interface are
1285	  handled appropriately by the kernel.
1286
1287	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1288	  that you will only be able to execute AArch32 binaries that were compiled
1289	  with page size aligned segments.
1290
1291	  If you want to execute 32-bit userspace applications, say Y.
1292
1293config SYSVIPC_COMPAT
1294	def_bool y
1295	depends on COMPAT && SYSVIPC
1296
1297endmenu
1298
1299menu "Power management options"
1300
1301source "kernel/power/Kconfig"
1302
1303config ARCH_HIBERNATION_POSSIBLE
1304	def_bool y
1305	depends on CPU_PM
1306
1307config ARCH_HIBERNATION_HEADER
1308	def_bool y
1309	depends on HIBERNATION
1310
1311config ARCH_SUSPEND_POSSIBLE
1312	def_bool y
1313
1314endmenu
1315
1316menu "CPU Power Management"
1317
1318source "drivers/cpuidle/Kconfig"
1319
1320source "drivers/cpufreq/Kconfig"
1321
1322endmenu
1323
1324source "net/Kconfig"
1325
1326source "drivers/Kconfig"
1327
1328source "drivers/firmware/Kconfig"
1329
1330source "drivers/acpi/Kconfig"
1331
1332source "fs/Kconfig"
1333
1334source "arch/arm64/kvm/Kconfig"
1335
1336source "arch/arm64/Kconfig.debug"
1337
1338source "security/Kconfig"
1339
1340source "crypto/Kconfig"
1341if CRYPTO
1342source "arch/arm64/crypto/Kconfig"
1343endif
1344
1345source "lib/Kconfig"