1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2021 Michael Walle <michael@walle.cc>
  4 */
  5/dts-v1/;
  6/include/ "zynq-7000.dtsi"
  7
  8/ {
  9	model = "Ebang EBAZ4205";
 10	compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
 11
 12	aliases {
 13		ethernet0 = &gem0;
 14		serial0 = &uart1;
 15	};
 16
 17	memory@0 {
 18		device_type = "memory";
 19		reg = <0x0 0x10000000>;
 20	};
 21
 22	chosen {
 23		stdout-path = "serial0:115200n8";
 24	};
 25};
 26
 27&clkc {
 28	ps-clk-frequency = <33333333>;
 29	fclk-enable = <8>;
 30};
 31
 32&gem0 {
 33	status = "okay";
 34	phy-mode = "mii";
 35	phy-handle = <&phy>;
 36
 37	/* PHY clock */
 38	assigned-clocks = <&clkc 18>;
 39	assigned-clock-rates = <25000000>;
 40
 41	phy: ethernet-phy@0 {
 42		reg = <0>;
 43	};
 44};
 45
 46&gpio0 {
 47	pinctrl-names = "default";
 48	pinctrl-0 = <&pinctrl_gpio0_default>;
 49};
 50
 51&pinctrl0 {
 52	pinctrl_gpio0_default: gpio0-default {
 53		mux {
 54			groups = "gpio0_20_grp", "gpio0_32_grp";
 55			function = "gpio0";
 56		};
 57
 58		conf {
 59			groups = "gpio0_20_grp", "gpio0_32_grp";
 60			io-standard = <3>;
 61			slew-rate = <0>;
 62		};
 63
 64		conf-pull-up {
 65			pins = "MIO20", "MIO32";
 66			bias-disable;
 67		};
 68	};
 69
 70	pinctrl_sdhci0_default: sdhci0-default {
 71		mux {
 72			groups = "sdio0_2_grp";
 73			function = "sdio0";
 74		};
 75
 76		conf {
 77			groups = "sdio0_2_grp";
 78			io-standard = <3>;
 79			slew-rate = <0>;
 80			bias-disable;
 81		};
 82
 83		mux-cd {
 84			groups = "gpio0_34_grp";
 85			function = "sdio0_cd";
 86		};
 87
 88		conf-cd {
 89			groups = "gpio0_34_grp";
 90			io-standard = <3>;
 91			slew-rate = <0>;
 92			bias-high-impedance;
 93			bias-pull-up;
 94		};
 95	};
 96
 97	pinctrl_uart1_default: uart1-default {
 98		mux {
 99			groups = "uart1_4_grp";
100			function = "uart1";
101		};
102
103		conf {
104			groups = "uart1_4_grp";
105			io-standard = <3>;
106			slew-rate = <0>;
107		};
108
109		conf-rx {
110			pins = "MIO25";
111			bias-high-impedance;
112		};
113
114		conf-tx {
115			pins = "MIO24";
116			bias-disable;
117		};
118	};
119};
120
121&sdhci0 {
122	status = "okay";
123	disable-wp;
124	pinctrl-names = "default";
125	pinctrl-0 = <&pinctrl_sdhci0_default>;
126};
127
128&uart1 {
129	status = "okay";
130	pinctrl-names = "default";
131	pinctrl-0 = <&pinctrl_uart1_default>;
132};