Loading...
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra30-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra30-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7
8#include "skeleton.dtsi"
9
10/ {
11 compatible = "nvidia,tegra30";
12 interrupt-parent = <&lic>;
13
14 pcie@3000 {
15 compatible = "nvidia,tegra30-pcie";
16 device_type = "pci";
17 reg = <0x00003000 0x00000800 /* PADS registers */
18 0x00003800 0x00000200 /* AFI registers */
19 0x10000000 0x10000000>; /* configuration space */
20 reg-names = "pads", "afi", "cs";
21 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
22 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
23 interrupt-names = "intr", "msi";
24
25 #interrupt-cells = <1>;
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28
29 bus-range = <0x00 0xff>;
30 #address-cells = <3>;
31 #size-cells = <2>;
32
33 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
35 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
36 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
37 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
38 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
39
40 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
41 <&tegra_car TEGRA30_CLK_AFI>,
42 <&tegra_car TEGRA30_CLK_PLL_E>,
43 <&tegra_car TEGRA30_CLK_CML0>;
44 clock-names = "pex", "afi", "pll_e", "cml";
45 resets = <&tegra_car 70>,
46 <&tegra_car 72>,
47 <&tegra_car 74>;
48 reset-names = "pex", "afi", "pcie_x";
49 status = "disabled";
50
51 pci@1,0 {
52 device_type = "pci";
53 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
54 reg = <0x000800 0 0 0 0>;
55 bus-range = <0x00 0xff>;
56 status = "disabled";
57
58 #address-cells = <3>;
59 #size-cells = <2>;
60 ranges;
61
62 nvidia,num-lanes = <2>;
63 };
64
65 pci@2,0 {
66 device_type = "pci";
67 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
68 reg = <0x001000 0 0 0 0>;
69 bus-range = <0x00 0xff>;
70 status = "disabled";
71
72 #address-cells = <3>;
73 #size-cells = <2>;
74 ranges;
75
76 nvidia,num-lanes = <2>;
77 };
78
79 pci@3,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
82 reg = <0x001800 0 0 0 0>;
83 bus-range = <0x00 0xff>;
84 status = "disabled";
85
86 #address-cells = <3>;
87 #size-cells = <2>;
88 ranges;
89
90 nvidia,num-lanes = <2>;
91 };
92 };
93
94 iram@40000000 {
95 compatible = "mmio-sram";
96 reg = <0x40000000 0x40000>;
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges = <0 0x40000000 0x40000>;
100
101 vde_pool: vde@400 {
102 reg = <0x400 0x3fc00>;
103 pool;
104 };
105 };
106
107 host1x@50000000 {
108 compatible = "nvidia,tegra30-host1x", "simple-bus";
109 reg = <0x50000000 0x00024000>;
110 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
111 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
112 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
113 resets = <&tegra_car 28>;
114 reset-names = "host1x";
115
116 #address-cells = <1>;
117 #size-cells = <1>;
118
119 ranges = <0x54000000 0x54000000 0x04000000>;
120
121 mpe@54040000 {
122 compatible = "nvidia,tegra30-mpe";
123 reg = <0x54040000 0x00040000>;
124 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&tegra_car TEGRA30_CLK_MPE>;
126 resets = <&tegra_car 60>;
127 reset-names = "mpe";
128 };
129
130 vi@54080000 {
131 compatible = "nvidia,tegra30-vi";
132 reg = <0x54080000 0x00040000>;
133 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&tegra_car TEGRA30_CLK_VI>;
135 resets = <&tegra_car 20>;
136 reset-names = "vi";
137 };
138
139 epp@540c0000 {
140 compatible = "nvidia,tegra30-epp";
141 reg = <0x540c0000 0x00040000>;
142 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&tegra_car TEGRA30_CLK_EPP>;
144 resets = <&tegra_car 19>;
145 reset-names = "epp";
146 };
147
148 isp@54100000 {
149 compatible = "nvidia,tegra30-isp";
150 reg = <0x54100000 0x00040000>;
151 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&tegra_car TEGRA30_CLK_ISP>;
153 resets = <&tegra_car 23>;
154 reset-names = "isp";
155 };
156
157 gr2d@54140000 {
158 compatible = "nvidia,tegra30-gr2d";
159 reg = <0x54140000 0x00040000>;
160 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
162 resets = <&tegra_car 21>;
163 reset-names = "2d";
164 };
165
166 gr3d@54180000 {
167 compatible = "nvidia,tegra30-gr3d";
168 reg = <0x54180000 0x00040000>;
169 clocks = <&tegra_car TEGRA30_CLK_GR3D
170 &tegra_car TEGRA30_CLK_GR3D2>;
171 clock-names = "3d", "3d2";
172 resets = <&tegra_car 24>,
173 <&tegra_car 98>;
174 reset-names = "3d", "3d2";
175 };
176
177 dc@54200000 {
178 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
179 reg = <0x54200000 0x00040000>;
180 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
182 <&tegra_car TEGRA30_CLK_PLL_P>;
183 clock-names = "dc", "parent";
184 resets = <&tegra_car 27>;
185 reset-names = "dc";
186
187 iommus = <&mc TEGRA_SWGROUP_DC>;
188
189 nvidia,head = <0>;
190
191 rgb {
192 status = "disabled";
193 };
194 };
195
196 dc@54240000 {
197 compatible = "nvidia,tegra30-dc";
198 reg = <0x54240000 0x00040000>;
199 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
201 <&tegra_car TEGRA30_CLK_PLL_P>;
202 clock-names = "dc", "parent";
203 resets = <&tegra_car 26>;
204 reset-names = "dc";
205
206 iommus = <&mc TEGRA_SWGROUP_DCB>;
207
208 nvidia,head = <1>;
209
210 rgb {
211 status = "disabled";
212 };
213 };
214
215 hdmi@54280000 {
216 compatible = "nvidia,tegra30-hdmi";
217 reg = <0x54280000 0x00040000>;
218 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
220 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
221 clock-names = "hdmi", "parent";
222 resets = <&tegra_car 51>;
223 reset-names = "hdmi";
224 status = "disabled";
225 };
226
227 tvo@542c0000 {
228 compatible = "nvidia,tegra30-tvo";
229 reg = <0x542c0000 0x00040000>;
230 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&tegra_car TEGRA30_CLK_TVO>;
232 status = "disabled";
233 };
234
235 dsi@54300000 {
236 compatible = "nvidia,tegra30-dsi";
237 reg = <0x54300000 0x00040000>;
238 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
239 resets = <&tegra_car 48>;
240 reset-names = "dsi";
241 status = "disabled";
242 };
243 };
244
245 timer@50040600 {
246 compatible = "arm,cortex-a9-twd-timer";
247 reg = <0x50040600 0x20>;
248 interrupt-parent = <&intc>;
249 interrupts = <GIC_PPI 13
250 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
251 clocks = <&tegra_car TEGRA30_CLK_TWD>;
252 };
253
254 intc: interrupt-controller@50041000 {
255 compatible = "arm,cortex-a9-gic";
256 reg = <0x50041000 0x1000
257 0x50040100 0x0100>;
258 interrupt-controller;
259 #interrupt-cells = <3>;
260 interrupt-parent = <&intc>;
261 };
262
263 cache-controller@50043000 {
264 compatible = "arm,pl310-cache";
265 reg = <0x50043000 0x1000>;
266 arm,data-latency = <6 6 2>;
267 arm,tag-latency = <5 5 2>;
268 cache-unified;
269 cache-level = <2>;
270 };
271
272 lic: interrupt-controller@60004000 {
273 compatible = "nvidia,tegra30-ictlr";
274 reg = <0x60004000 0x100>,
275 <0x60004100 0x50>,
276 <0x60004200 0x50>,
277 <0x60004300 0x50>,
278 <0x60004400 0x50>;
279 interrupt-controller;
280 #interrupt-cells = <3>;
281 interrupt-parent = <&intc>;
282 };
283
284 timer@60005000 {
285 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
286 reg = <0x60005000 0x400>;
287 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
294 };
295
296 tegra_car: clock@60006000 {
297 compatible = "nvidia,tegra30-car";
298 reg = <0x60006000 0x1000>;
299 #clock-cells = <1>;
300 #reset-cells = <1>;
301 };
302
303 flow-controller@60007000 {
304 compatible = "nvidia,tegra30-flowctrl";
305 reg = <0x60007000 0x1000>;
306 };
307
308 apbdma: dma@6000a000 {
309 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
310 reg = <0x6000a000 0x1400>;
311 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
344 resets = <&tegra_car 34>;
345 reset-names = "dma";
346 #dma-cells = <1>;
347 };
348
349 ahb: ahb@6000c000 {
350 compatible = "nvidia,tegra30-ahb";
351 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
352 };
353
354 gpio: gpio@6000d000 {
355 compatible = "nvidia,tegra30-gpio";
356 reg = <0x6000d000 0x1000>;
357 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
365 #gpio-cells = <2>;
366 gpio-controller;
367 #interrupt-cells = <2>;
368 interrupt-controller;
369 /*
370 gpio-ranges = <&pinmux 0 0 248>;
371 */
372 };
373
374 vde@6001a000 {
375 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
376 reg = <0x6001a000 0x1000 /* Syntax Engine */
377 0x6001b000 0x1000 /* Video Bitstream Engine */
378 0x6001c000 0x100 /* Macroblock Engine */
379 0x6001c200 0x100 /* Post-processing Engine */
380 0x6001c400 0x100 /* Motion Compensation Engine */
381 0x6001c600 0x100 /* Transform Engine */
382 0x6001c800 0x100 /* Pixel prediction block */
383 0x6001ca00 0x100 /* Video DMA */
384 0x6001d800 0x400>; /* Video frame controls */
385 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
386 "tfe", "ppb", "vdma", "frameid";
387 iram = <&vde_pool>; /* IRAM region */
388 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
389 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
390 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
391 interrupt-names = "sync-token", "bsev", "sxe";
392 clocks = <&tegra_car TEGRA30_CLK_VDE>;
393 resets = <&tegra_car 61>;
394 };
395
396 apbmisc@70000800 {
397 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
398 reg = <0x70000800 0x64 /* Chip revision */
399 0x70000008 0x04>; /* Strapping options */
400 };
401
402 pinmux: pinmux@70000868 {
403 compatible = "nvidia,tegra30-pinmux";
404 reg = <0x70000868 0xd4 /* Pad control registers */
405 0x70003000 0x3e4>; /* Mux registers */
406 };
407
408 /*
409 * There are two serial driver i.e. 8250 based simple serial
410 * driver and APB DMA based serial driver for higher baudrate
411 * and performace. To enable the 8250 based driver, the compatible
412 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
413 * the APB DMA based serial driver, the compatible is
414 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
415 */
416 uarta: serial@70006000 {
417 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
418 reg = <0x70006000 0x40>;
419 reg-shift = <2>;
420 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
422 resets = <&tegra_car 6>;
423 reset-names = "serial";
424 dmas = <&apbdma 8>, <&apbdma 8>;
425 dma-names = "rx", "tx";
426 status = "disabled";
427 };
428
429 uartb: serial@70006040 {
430 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
431 reg = <0x70006040 0x40>;
432 reg-shift = <2>;
433 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
435 resets = <&tegra_car 7>;
436 reset-names = "serial";
437 dmas = <&apbdma 9>, <&apbdma 9>;
438 dma-names = "rx", "tx";
439 status = "disabled";
440 };
441
442 uartc: serial@70006200 {
443 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
444 reg = <0x70006200 0x100>;
445 reg-shift = <2>;
446 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
448 resets = <&tegra_car 55>;
449 reset-names = "serial";
450 dmas = <&apbdma 10>, <&apbdma 10>;
451 dma-names = "rx", "tx";
452 status = "disabled";
453 };
454
455 uartd: serial@70006300 {
456 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
457 reg = <0x70006300 0x100>;
458 reg-shift = <2>;
459 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
461 resets = <&tegra_car 65>;
462 reset-names = "serial";
463 dmas = <&apbdma 19>, <&apbdma 19>;
464 dma-names = "rx", "tx";
465 status = "disabled";
466 };
467
468 uarte: serial@70006400 {
469 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
470 reg = <0x70006400 0x100>;
471 reg-shift = <2>;
472 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
474 resets = <&tegra_car 66>;
475 reset-names = "serial";
476 dmas = <&apbdma 20>, <&apbdma 20>;
477 dma-names = "rx", "tx";
478 status = "disabled";
479 };
480
481 gmi@70009000 {
482 compatible = "nvidia,tegra30-gmi";
483 reg = <0x70009000 0x1000>;
484 #address-cells = <2>;
485 #size-cells = <1>;
486 ranges = <0 0 0x48000000 0x7ffffff>;
487 clocks = <&tegra_car TEGRA30_CLK_NOR>;
488 clock-names = "gmi";
489 resets = <&tegra_car 42>;
490 reset-names = "gmi";
491 status = "disabled";
492 };
493
494 pwm: pwm@7000a000 {
495 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
496 reg = <0x7000a000 0x100>;
497 #pwm-cells = <2>;
498 clocks = <&tegra_car TEGRA30_CLK_PWM>;
499 resets = <&tegra_car 17>;
500 reset-names = "pwm";
501 status = "disabled";
502 };
503
504 rtc@7000e000 {
505 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
506 reg = <0x7000e000 0x100>;
507 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&tegra_car TEGRA30_CLK_RTC>;
509 };
510
511 i2c@7000c000 {
512 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
513 reg = <0x7000c000 0x100>;
514 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
518 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
519 clock-names = "div-clk", "fast-clk";
520 resets = <&tegra_car 12>;
521 reset-names = "i2c";
522 dmas = <&apbdma 21>, <&apbdma 21>;
523 dma-names = "rx", "tx";
524 status = "disabled";
525 };
526
527 i2c@7000c400 {
528 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
529 reg = <0x7000c400 0x100>;
530 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
534 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
535 clock-names = "div-clk", "fast-clk";
536 resets = <&tegra_car 54>;
537 reset-names = "i2c";
538 dmas = <&apbdma 22>, <&apbdma 22>;
539 dma-names = "rx", "tx";
540 status = "disabled";
541 };
542
543 i2c@7000c500 {
544 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
545 reg = <0x7000c500 0x100>;
546 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
550 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
551 clock-names = "div-clk", "fast-clk";
552 resets = <&tegra_car 67>;
553 reset-names = "i2c";
554 dmas = <&apbdma 23>, <&apbdma 23>;
555 dma-names = "rx", "tx";
556 status = "disabled";
557 };
558
559 i2c@7000c700 {
560 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
561 reg = <0x7000c700 0x100>;
562 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
563 #address-cells = <1>;
564 #size-cells = <0>;
565 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
566 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
567 resets = <&tegra_car 103>;
568 reset-names = "i2c";
569 clock-names = "div-clk", "fast-clk";
570 dmas = <&apbdma 26>, <&apbdma 26>;
571 dma-names = "rx", "tx";
572 status = "disabled";
573 };
574
575 i2c@7000d000 {
576 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
577 reg = <0x7000d000 0x100>;
578 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
579 #address-cells = <1>;
580 #size-cells = <0>;
581 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
582 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
583 clock-names = "div-clk", "fast-clk";
584 resets = <&tegra_car 47>;
585 reset-names = "i2c";
586 dmas = <&apbdma 24>, <&apbdma 24>;
587 dma-names = "rx", "tx";
588 status = "disabled";
589 };
590
591 spi@7000d400 {
592 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
593 reg = <0x7000d400 0x200>;
594 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
595 #address-cells = <1>;
596 #size-cells = <0>;
597 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
598 resets = <&tegra_car 41>;
599 reset-names = "spi";
600 dmas = <&apbdma 15>, <&apbdma 15>;
601 dma-names = "rx", "tx";
602 status = "disabled";
603 };
604
605 spi@7000d600 {
606 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
607 reg = <0x7000d600 0x200>;
608 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
609 #address-cells = <1>;
610 #size-cells = <0>;
611 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
612 resets = <&tegra_car 44>;
613 reset-names = "spi";
614 dmas = <&apbdma 16>, <&apbdma 16>;
615 dma-names = "rx", "tx";
616 status = "disabled";
617 };
618
619 spi@7000d800 {
620 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
621 reg = <0x7000d800 0x200>;
622 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
623 #address-cells = <1>;
624 #size-cells = <0>;
625 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
626 resets = <&tegra_car 46>;
627 reset-names = "spi";
628 dmas = <&apbdma 17>, <&apbdma 17>;
629 dma-names = "rx", "tx";
630 status = "disabled";
631 };
632
633 spi@7000da00 {
634 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
635 reg = <0x7000da00 0x200>;
636 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
637 #address-cells = <1>;
638 #size-cells = <0>;
639 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
640 resets = <&tegra_car 68>;
641 reset-names = "spi";
642 dmas = <&apbdma 18>, <&apbdma 18>;
643 dma-names = "rx", "tx";
644 status = "disabled";
645 };
646
647 spi@7000dc00 {
648 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
649 reg = <0x7000dc00 0x200>;
650 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
651 #address-cells = <1>;
652 #size-cells = <0>;
653 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
654 resets = <&tegra_car 104>;
655 reset-names = "spi";
656 dmas = <&apbdma 27>, <&apbdma 27>;
657 dma-names = "rx", "tx";
658 status = "disabled";
659 };
660
661 spi@7000de00 {
662 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
663 reg = <0x7000de00 0x200>;
664 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
665 #address-cells = <1>;
666 #size-cells = <0>;
667 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
668 resets = <&tegra_car 106>;
669 reset-names = "spi";
670 dmas = <&apbdma 28>, <&apbdma 28>;
671 dma-names = "rx", "tx";
672 status = "disabled";
673 };
674
675 kbc@7000e200 {
676 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
677 reg = <0x7000e200 0x100>;
678 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&tegra_car TEGRA30_CLK_KBC>;
680 resets = <&tegra_car 36>;
681 reset-names = "kbc";
682 status = "disabled";
683 };
684
685 pmc@7000e400 {
686 compatible = "nvidia,tegra30-pmc";
687 reg = <0x7000e400 0x400>;
688 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
689 clock-names = "pclk", "clk32k_in";
690 };
691
692 mc: memory-controller@7000f000 {
693 compatible = "nvidia,tegra30-mc";
694 reg = <0x7000f000 0x400>;
695 clocks = <&tegra_car TEGRA30_CLK_MC>;
696 clock-names = "mc";
697
698 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
699
700 #iommu-cells = <1>;
701 };
702
703 fuse@7000f800 {
704 compatible = "nvidia,tegra30-efuse";
705 reg = <0x7000f800 0x400>;
706 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
707 clock-names = "fuse";
708 resets = <&tegra_car 39>;
709 reset-names = "fuse";
710 };
711
712 hda@70030000 {
713 compatible = "nvidia,tegra30-hda";
714 reg = <0x70030000 0x10000>;
715 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&tegra_car TEGRA30_CLK_HDA>,
717 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
718 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
719 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
720 resets = <&tegra_car 125>, /* hda */
721 <&tegra_car 128>, /* hda2hdmi */
722 <&tegra_car 111>; /* hda2codec_2x */
723 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
724 status = "disabled";
725 };
726
727 ahub@70080000 {
728 compatible = "nvidia,tegra30-ahub";
729 reg = <0x70080000 0x200
730 0x70080200 0x100>;
731 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
733 <&tegra_car TEGRA30_CLK_APBIF>;
734 clock-names = "d_audio", "apbif";
735 resets = <&tegra_car 106>, /* d_audio */
736 <&tegra_car 107>, /* apbif */
737 <&tegra_car 30>, /* i2s0 */
738 <&tegra_car 11>, /* i2s1 */
739 <&tegra_car 18>, /* i2s2 */
740 <&tegra_car 101>, /* i2s3 */
741 <&tegra_car 102>, /* i2s4 */
742 <&tegra_car 108>, /* dam0 */
743 <&tegra_car 109>, /* dam1 */
744 <&tegra_car 110>, /* dam2 */
745 <&tegra_car 10>; /* spdif */
746 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
747 "i2s3", "i2s4", "dam0", "dam1", "dam2",
748 "spdif";
749 dmas = <&apbdma 1>, <&apbdma 1>,
750 <&apbdma 2>, <&apbdma 2>,
751 <&apbdma 3>, <&apbdma 3>,
752 <&apbdma 4>, <&apbdma 4>;
753 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
754 "rx3", "tx3";
755 ranges;
756 #address-cells = <1>;
757 #size-cells = <1>;
758
759 tegra_i2s0: i2s@70080300 {
760 compatible = "nvidia,tegra30-i2s";
761 reg = <0x70080300 0x100>;
762 nvidia,ahub-cif-ids = <4 4>;
763 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
764 resets = <&tegra_car 30>;
765 reset-names = "i2s";
766 status = "disabled";
767 };
768
769 tegra_i2s1: i2s@70080400 {
770 compatible = "nvidia,tegra30-i2s";
771 reg = <0x70080400 0x100>;
772 nvidia,ahub-cif-ids = <5 5>;
773 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
774 resets = <&tegra_car 11>;
775 reset-names = "i2s";
776 status = "disabled";
777 };
778
779 tegra_i2s2: i2s@70080500 {
780 compatible = "nvidia,tegra30-i2s";
781 reg = <0x70080500 0x100>;
782 nvidia,ahub-cif-ids = <6 6>;
783 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
784 resets = <&tegra_car 18>;
785 reset-names = "i2s";
786 status = "disabled";
787 };
788
789 tegra_i2s3: i2s@70080600 {
790 compatible = "nvidia,tegra30-i2s";
791 reg = <0x70080600 0x100>;
792 nvidia,ahub-cif-ids = <7 7>;
793 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
794 resets = <&tegra_car 101>;
795 reset-names = "i2s";
796 status = "disabled";
797 };
798
799 tegra_i2s4: i2s@70080700 {
800 compatible = "nvidia,tegra30-i2s";
801 reg = <0x70080700 0x100>;
802 nvidia,ahub-cif-ids = <8 8>;
803 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
804 resets = <&tegra_car 102>;
805 reset-names = "i2s";
806 status = "disabled";
807 };
808 };
809
810 sdhci@78000000 {
811 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
812 reg = <0x78000000 0x200>;
813 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
815 resets = <&tegra_car 14>;
816 reset-names = "sdhci";
817 status = "disabled";
818 };
819
820 sdhci@78000200 {
821 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
822 reg = <0x78000200 0x200>;
823 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
825 resets = <&tegra_car 9>;
826 reset-names = "sdhci";
827 status = "disabled";
828 };
829
830 sdhci@78000400 {
831 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
832 reg = <0x78000400 0x200>;
833 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
835 resets = <&tegra_car 69>;
836 reset-names = "sdhci";
837 status = "disabled";
838 };
839
840 sdhci@78000600 {
841 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
842 reg = <0x78000600 0x200>;
843 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
845 resets = <&tegra_car 15>;
846 reset-names = "sdhci";
847 status = "disabled";
848 };
849
850 usb@7d000000 {
851 compatible = "nvidia,tegra30-ehci", "usb-ehci";
852 reg = <0x7d000000 0x4000>;
853 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
854 phy_type = "utmi";
855 clocks = <&tegra_car TEGRA30_CLK_USBD>;
856 resets = <&tegra_car 22>;
857 reset-names = "usb";
858 nvidia,needs-double-reset;
859 nvidia,phy = <&phy1>;
860 status = "disabled";
861 };
862
863 phy1: usb-phy@7d000000 {
864 compatible = "nvidia,tegra30-usb-phy";
865 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
866 phy_type = "utmi";
867 clocks = <&tegra_car TEGRA30_CLK_USBD>,
868 <&tegra_car TEGRA30_CLK_PLL_U>,
869 <&tegra_car TEGRA30_CLK_USBD>;
870 clock-names = "reg", "pll_u", "utmi-pads";
871 resets = <&tegra_car 22>, <&tegra_car 22>;
872 reset-names = "usb", "utmi-pads";
873 nvidia,hssync-start-delay = <9>;
874 nvidia,idle-wait-delay = <17>;
875 nvidia,elastic-limit = <16>;
876 nvidia,term-range-adj = <6>;
877 nvidia,xcvr-setup = <51>;
878 nvidia.xcvr-setup-use-fuses;
879 nvidia,xcvr-lsfslew = <1>;
880 nvidia,xcvr-lsrslew = <1>;
881 nvidia,xcvr-hsslew = <32>;
882 nvidia,hssquelch-level = <2>;
883 nvidia,hsdiscon-level = <5>;
884 nvidia,has-utmi-pad-registers;
885 status = "disabled";
886 };
887
888 usb@7d004000 {
889 compatible = "nvidia,tegra30-ehci", "usb-ehci";
890 reg = <0x7d004000 0x4000>;
891 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
892 phy_type = "utmi";
893 clocks = <&tegra_car TEGRA30_CLK_USB2>;
894 resets = <&tegra_car 58>;
895 reset-names = "usb";
896 nvidia,phy = <&phy2>;
897 status = "disabled";
898 };
899
900 phy2: usb-phy@7d004000 {
901 compatible = "nvidia,tegra30-usb-phy";
902 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
903 phy_type = "utmi";
904 clocks = <&tegra_car TEGRA30_CLK_USB2>,
905 <&tegra_car TEGRA30_CLK_PLL_U>,
906 <&tegra_car TEGRA30_CLK_USBD>;
907 clock-names = "reg", "pll_u", "utmi-pads";
908 resets = <&tegra_car 58>, <&tegra_car 22>;
909 reset-names = "usb", "utmi-pads";
910 nvidia,hssync-start-delay = <9>;
911 nvidia,idle-wait-delay = <17>;
912 nvidia,elastic-limit = <16>;
913 nvidia,term-range-adj = <6>;
914 nvidia,xcvr-setup = <51>;
915 nvidia.xcvr-setup-use-fuses;
916 nvidia,xcvr-lsfslew = <2>;
917 nvidia,xcvr-lsrslew = <2>;
918 nvidia,xcvr-hsslew = <32>;
919 nvidia,hssquelch-level = <2>;
920 nvidia,hsdiscon-level = <5>;
921 status = "disabled";
922 };
923
924 usb@7d008000 {
925 compatible = "nvidia,tegra30-ehci", "usb-ehci";
926 reg = <0x7d008000 0x4000>;
927 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
928 phy_type = "utmi";
929 clocks = <&tegra_car TEGRA30_CLK_USB3>;
930 resets = <&tegra_car 59>;
931 reset-names = "usb";
932 nvidia,phy = <&phy3>;
933 status = "disabled";
934 };
935
936 phy3: usb-phy@7d008000 {
937 compatible = "nvidia,tegra30-usb-phy";
938 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
939 phy_type = "utmi";
940 clocks = <&tegra_car TEGRA30_CLK_USB3>,
941 <&tegra_car TEGRA30_CLK_PLL_U>,
942 <&tegra_car TEGRA30_CLK_USBD>;
943 clock-names = "reg", "pll_u", "utmi-pads";
944 resets = <&tegra_car 59>, <&tegra_car 22>;
945 reset-names = "usb", "utmi-pads";
946 nvidia,hssync-start-delay = <0>;
947 nvidia,idle-wait-delay = <17>;
948 nvidia,elastic-limit = <16>;
949 nvidia,term-range-adj = <6>;
950 nvidia,xcvr-setup = <51>;
951 nvidia.xcvr-setup-use-fuses;
952 nvidia,xcvr-lsfslew = <2>;
953 nvidia,xcvr-lsrslew = <2>;
954 nvidia,xcvr-hsslew = <32>;
955 nvidia,hssquelch-level = <2>;
956 nvidia,hsdiscon-level = <5>;
957 status = "disabled";
958 };
959
960 cpus {
961 #address-cells = <1>;
962 #size-cells = <0>;
963
964 cpu@0 {
965 device_type = "cpu";
966 compatible = "arm,cortex-a9";
967 reg = <0>;
968 };
969
970 cpu@1 {
971 device_type = "cpu";
972 compatible = "arm,cortex-a9";
973 reg = <1>;
974 };
975
976 cpu@2 {
977 device_type = "cpu";
978 compatible = "arm,cortex-a9";
979 reg = <2>;
980 };
981
982 cpu@3 {
983 device_type = "cpu";
984 compatible = "arm,cortex-a9";
985 reg = <3>;
986 };
987 };
988
989 pmu {
990 compatible = "arm,cortex-a9-pmu";
991 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
995 };
996};
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra30-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra30-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/soc/tegra-pmc.h>
8
9#include "tegra30-peripherals-opp.dtsi"
10
11/ {
12 compatible = "nvidia,tegra30";
13 interrupt-parent = <&lic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 memory@80000000 {
18 device_type = "memory";
19 reg = <0x80000000 0x0>;
20 };
21
22 pcie@3000 {
23 compatible = "nvidia,tegra30-pcie";
24 device_type = "pci";
25 reg = <0x00003000 0x00000800>, /* PADS registers */
26 <0x00003800 0x00000200>, /* AFI registers */
27 <0x10000000 0x10000000>; /* configuration space */
28 reg-names = "pads", "afi", "cs";
29 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
30 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
31 interrupt-names = "intr", "msi";
32
33 #interrupt-cells = <1>;
34 interrupt-map-mask = <0 0 0 0>;
35 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
36
37 bus-range = <0x00 0xff>;
38 #address-cells = <3>;
39 #size-cells = <2>;
40
41 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
42 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
43 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
44 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
45 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
46 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
47
48 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
49 <&tegra_car TEGRA30_CLK_AFI>,
50 <&tegra_car TEGRA30_CLK_PLL_E>,
51 <&tegra_car TEGRA30_CLK_CML0>;
52 clock-names = "pex", "afi", "pll_e", "cml";
53 resets = <&tegra_car 70>,
54 <&tegra_car 72>,
55 <&tegra_car 74>;
56 reset-names = "pex", "afi", "pcie_x";
57 status = "disabled";
58
59 pci@1,0 {
60 device_type = "pci";
61 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
62 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff>;
64 status = "disabled";
65
66 #address-cells = <3>;
67 #size-cells = <2>;
68 ranges;
69
70 nvidia,num-lanes = <2>;
71 };
72
73 pci@2,0 {
74 device_type = "pci";
75 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
76 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff>;
78 status = "disabled";
79
80 #address-cells = <3>;
81 #size-cells = <2>;
82 ranges;
83
84 nvidia,num-lanes = <2>;
85 };
86
87 pci@3,0 {
88 device_type = "pci";
89 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
90 reg = <0x001800 0 0 0 0>;
91 bus-range = <0x00 0xff>;
92 status = "disabled";
93
94 #address-cells = <3>;
95 #size-cells = <2>;
96 ranges;
97
98 nvidia,num-lanes = <2>;
99 };
100 };
101
102 sram@40000000 {
103 compatible = "mmio-sram";
104 reg = <0x40000000 0x40000>;
105 #address-cells = <1>;
106 #size-cells = <1>;
107 ranges = <0 0x40000000 0x40000>;
108
109 vde_pool: sram@400 {
110 reg = <0x400 0x3fc00>;
111 pool;
112 };
113 };
114
115 host1x@50000000 {
116 compatible = "nvidia,tegra30-host1x";
117 reg = <0x50000000 0x00024000>;
118 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
119 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
120 interrupt-names = "syncpt", "host1x";
121 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
122 clock-names = "host1x";
123 resets = <&tegra_car 28>;
124 reset-names = "host1x";
125 iommus = <&mc TEGRA_SWGROUP_HC>;
126
127 #address-cells = <1>;
128 #size-cells = <1>;
129
130 ranges = <0x54000000 0x54000000 0x04000000>;
131
132 mpe@54040000 {
133 compatible = "nvidia,tegra30-mpe";
134 reg = <0x54040000 0x00040000>;
135 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&tegra_car TEGRA30_CLK_MPE>;
137 resets = <&tegra_car 60>;
138 reset-names = "mpe";
139
140 iommus = <&mc TEGRA_SWGROUP_MPE>;
141 };
142
143 vi@54080000 {
144 compatible = "nvidia,tegra30-vi";
145 reg = <0x54080000 0x00040000>;
146 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&tegra_car TEGRA30_CLK_VI>;
148 resets = <&tegra_car 20>;
149 reset-names = "vi";
150
151 iommus = <&mc TEGRA_SWGROUP_VI>;
152 };
153
154 epp@540c0000 {
155 compatible = "nvidia,tegra30-epp";
156 reg = <0x540c0000 0x00040000>;
157 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&tegra_car TEGRA30_CLK_EPP>;
159 resets = <&tegra_car 19>;
160 reset-names = "epp";
161
162 iommus = <&mc TEGRA_SWGROUP_EPP>;
163 };
164
165 isp@54100000 {
166 compatible = "nvidia,tegra30-isp";
167 reg = <0x54100000 0x00040000>;
168 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
169 clocks = <&tegra_car TEGRA30_CLK_ISP>;
170 resets = <&tegra_car 23>;
171 reset-names = "isp";
172
173 iommus = <&mc TEGRA_SWGROUP_ISP>;
174 };
175
176 gr2d@54140000 {
177 compatible = "nvidia,tegra30-gr2d";
178 reg = <0x54140000 0x00040000>;
179 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
181 resets = <&tegra_car 21>;
182 reset-names = "2d";
183
184 iommus = <&mc TEGRA_SWGROUP_G2>;
185 };
186
187 gr3d@54180000 {
188 compatible = "nvidia,tegra30-gr3d";
189 reg = <0x54180000 0x00040000>;
190 clocks = <&tegra_car TEGRA30_CLK_GR3D>,
191 <&tegra_car TEGRA30_CLK_GR3D2>;
192 clock-names = "3d", "3d2";
193 resets = <&tegra_car 24>,
194 <&tegra_car 98>;
195 reset-names = "3d", "3d2";
196
197 iommus = <&mc TEGRA_SWGROUP_NV>,
198 <&mc TEGRA_SWGROUP_NV2>;
199 };
200
201 dc@54200000 {
202 compatible = "nvidia,tegra30-dc";
203 reg = <0x54200000 0x00040000>;
204 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
206 <&tegra_car TEGRA30_CLK_PLL_P>;
207 clock-names = "dc", "parent";
208 resets = <&tegra_car 27>;
209 reset-names = "dc";
210
211 iommus = <&mc TEGRA_SWGROUP_DC>;
212
213 nvidia,head = <0>;
214
215 interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>,
216 <&mc TEGRA30_MC_DISPLAY0B &emc>,
217 <&mc TEGRA30_MC_DISPLAY1B &emc>,
218 <&mc TEGRA30_MC_DISPLAY0C &emc>,
219 <&mc TEGRA30_MC_DISPLAYHC &emc>;
220 interconnect-names = "wina",
221 "winb",
222 "winb-vfilter",
223 "winc",
224 "cursor";
225
226 rgb {
227 status = "disabled";
228 };
229 };
230
231 dc@54240000 {
232 compatible = "nvidia,tegra30-dc";
233 reg = <0x54240000 0x00040000>;
234 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
236 <&tegra_car TEGRA30_CLK_PLL_P>;
237 clock-names = "dc", "parent";
238 resets = <&tegra_car 26>;
239 reset-names = "dc";
240
241 iommus = <&mc TEGRA_SWGROUP_DCB>;
242
243 nvidia,head = <1>;
244
245 interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>,
246 <&mc TEGRA30_MC_DISPLAY0BB &emc>,
247 <&mc TEGRA30_MC_DISPLAY1BB &emc>,
248 <&mc TEGRA30_MC_DISPLAY0CB &emc>,
249 <&mc TEGRA30_MC_DISPLAYHCB &emc>;
250 interconnect-names = "wina",
251 "winb",
252 "winb-vfilter",
253 "winc",
254 "cursor";
255
256 rgb {
257 status = "disabled";
258 };
259 };
260
261 hdmi@54280000 {
262 compatible = "nvidia,tegra30-hdmi";
263 reg = <0x54280000 0x00040000>;
264 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
266 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
267 clock-names = "hdmi", "parent";
268 resets = <&tegra_car 51>;
269 reset-names = "hdmi";
270 status = "disabled";
271 };
272
273 tvo@542c0000 {
274 compatible = "nvidia,tegra30-tvo";
275 reg = <0x542c0000 0x00040000>;
276 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&tegra_car TEGRA30_CLK_TVO>;
278 status = "disabled";
279 };
280
281 dsi@54300000 {
282 compatible = "nvidia,tegra30-dsi";
283 reg = <0x54300000 0x00040000>;
284 clocks = <&tegra_car TEGRA30_CLK_DSIA>,
285 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
286 clock-names = "dsi", "parent";
287 resets = <&tegra_car 48>;
288 reset-names = "dsi";
289 status = "disabled";
290 };
291
292 dsi@54400000 {
293 compatible = "nvidia,tegra30-dsi";
294 reg = <0x54400000 0x00040000>;
295 clocks = <&tegra_car TEGRA30_CLK_DSIB>,
296 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
297 clock-names = "dsi", "parent";
298 resets = <&tegra_car 84>;
299 reset-names = "dsi";
300 status = "disabled";
301 };
302 };
303
304 timer@50040600 {
305 compatible = "arm,cortex-a9-twd-timer";
306 reg = <0x50040600 0x20>;
307 interrupt-parent = <&intc>;
308 interrupts = <GIC_PPI 13
309 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
310 clocks = <&tegra_car TEGRA30_CLK_TWD>;
311 };
312
313 intc: interrupt-controller@50041000 {
314 compatible = "arm,cortex-a9-gic";
315 reg = <0x50041000 0x1000>,
316 <0x50040100 0x0100>;
317 interrupt-controller;
318 #interrupt-cells = <3>;
319 interrupt-parent = <&intc>;
320 };
321
322 cache-controller@50043000 {
323 compatible = "arm,pl310-cache";
324 reg = <0x50043000 0x1000>;
325 arm,data-latency = <6 6 2>;
326 arm,tag-latency = <5 5 2>;
327 cache-unified;
328 cache-level = <2>;
329 };
330
331 lic: interrupt-controller@60004000 {
332 compatible = "nvidia,tegra30-ictlr";
333 reg = <0x60004000 0x100>,
334 <0x60004100 0x50>,
335 <0x60004200 0x50>,
336 <0x60004300 0x50>,
337 <0x60004400 0x50>;
338 interrupt-controller;
339 #interrupt-cells = <3>;
340 interrupt-parent = <&intc>;
341 };
342
343 timer@60005000 {
344 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
345 reg = <0x60005000 0x400>;
346 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
353 };
354
355 tegra_car: clock@60006000 {
356 compatible = "nvidia,tegra30-car";
357 reg = <0x60006000 0x1000>;
358 #clock-cells = <1>;
359 #reset-cells = <1>;
360 };
361
362 flow-controller@60007000 {
363 compatible = "nvidia,tegra30-flowctrl";
364 reg = <0x60007000 0x1000>;
365 };
366
367 apbdma: dma@6000a000 {
368 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
369 reg = <0x6000a000 0x1400>;
370 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
403 resets = <&tegra_car 34>;
404 reset-names = "dma";
405 #dma-cells = <1>;
406 };
407
408 ahb: ahb@6000c000 {
409 compatible = "nvidia,tegra30-ahb";
410 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
411 };
412
413 actmon: actmon@6000c800 {
414 compatible = "nvidia,tegra30-actmon";
415 reg = <0x6000c800 0x400>;
416 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
418 <&tegra_car TEGRA30_CLK_EMC>;
419 clock-names = "actmon", "emc";
420 resets = <&tegra_car TEGRA30_CLK_ACTMON>;
421 reset-names = "actmon";
422 operating-points-v2 = <&emc_bw_dfs_opp_table>;
423 interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
424 interconnect-names = "cpu-read";
425 #cooling-cells = <2>;
426 };
427
428 gpio: gpio@6000d000 {
429 compatible = "nvidia,tegra30-gpio";
430 reg = <0x6000d000 0x1000>;
431 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
439 #gpio-cells = <2>;
440 gpio-controller;
441 #interrupt-cells = <2>;
442 interrupt-controller;
443 /*
444 gpio-ranges = <&pinmux 0 0 248>;
445 */
446 };
447
448 vde@6001a000 {
449 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
450 reg = <0x6001a000 0x1000>, /* Syntax Engine */
451 <0x6001b000 0x1000>, /* Video Bitstream Engine */
452 <0x6001c000 0x100>, /* Macroblock Engine */
453 <0x6001c200 0x100>, /* Post-processing Engine */
454 <0x6001c400 0x100>, /* Motion Compensation Engine */
455 <0x6001c600 0x100>, /* Transform Engine */
456 <0x6001c800 0x100>, /* Pixel prediction block */
457 <0x6001ca00 0x100>, /* Video DMA */
458 <0x6001d800 0x400>; /* Video frame controls */
459 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
460 "tfe", "ppb", "vdma", "frameid";
461 iram = <&vde_pool>; /* IRAM region */
462 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
463 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
464 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
465 interrupt-names = "sync-token", "bsev", "sxe";
466 clocks = <&tegra_car TEGRA30_CLK_VDE>;
467 reset-names = "vde", "mc";
468 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
469 iommus = <&mc TEGRA_SWGROUP_VDE>;
470 };
471
472 apbmisc@70000800 {
473 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
474 reg = <0x70000800 0x64>, /* Chip revision */
475 <0x70000008 0x04>; /* Strapping options */
476 };
477
478 pinmux: pinmux@70000868 {
479 compatible = "nvidia,tegra30-pinmux";
480 reg = <0x70000868 0x0d4>, /* Pad control registers */
481 <0x70003000 0x3e4>; /* Mux registers */
482 };
483
484 /*
485 * There are two serial driver i.e. 8250 based simple serial
486 * driver and APB DMA based serial driver for higher baudrate
487 * and performace. To enable the 8250 based driver, the compatible
488 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
489 * the APB DMA based serial driver, the compatible is
490 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
491 */
492 uarta: serial@70006000 {
493 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
494 reg = <0x70006000 0x40>;
495 reg-shift = <2>;
496 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
498 resets = <&tegra_car 6>;
499 reset-names = "serial";
500 dmas = <&apbdma 8>, <&apbdma 8>;
501 dma-names = "rx", "tx";
502 status = "disabled";
503 };
504
505 uartb: serial@70006040 {
506 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
507 reg = <0x70006040 0x40>;
508 reg-shift = <2>;
509 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
511 resets = <&tegra_car 7>;
512 reset-names = "serial";
513 dmas = <&apbdma 9>, <&apbdma 9>;
514 dma-names = "rx", "tx";
515 status = "disabled";
516 };
517
518 uartc: serial@70006200 {
519 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
520 reg = <0x70006200 0x100>;
521 reg-shift = <2>;
522 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
524 resets = <&tegra_car 55>;
525 reset-names = "serial";
526 dmas = <&apbdma 10>, <&apbdma 10>;
527 dma-names = "rx", "tx";
528 status = "disabled";
529 };
530
531 uartd: serial@70006300 {
532 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
533 reg = <0x70006300 0x100>;
534 reg-shift = <2>;
535 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
537 resets = <&tegra_car 65>;
538 reset-names = "serial";
539 dmas = <&apbdma 19>, <&apbdma 19>;
540 dma-names = "rx", "tx";
541 status = "disabled";
542 };
543
544 uarte: serial@70006400 {
545 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
546 reg = <0x70006400 0x100>;
547 reg-shift = <2>;
548 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
550 resets = <&tegra_car 66>;
551 reset-names = "serial";
552 dmas = <&apbdma 20>, <&apbdma 20>;
553 dma-names = "rx", "tx";
554 status = "disabled";
555 };
556
557 gmi@70009000 {
558 compatible = "nvidia,tegra30-gmi";
559 reg = <0x70009000 0x1000>;
560 #address-cells = <2>;
561 #size-cells = <1>;
562 ranges = <0 0 0x48000000 0x7ffffff>;
563 clocks = <&tegra_car TEGRA30_CLK_NOR>;
564 clock-names = "gmi";
565 resets = <&tegra_car 42>;
566 reset-names = "gmi";
567 status = "disabled";
568 };
569
570 pwm: pwm@7000a000 {
571 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
572 reg = <0x7000a000 0x100>;
573 #pwm-cells = <2>;
574 clocks = <&tegra_car TEGRA30_CLK_PWM>;
575 resets = <&tegra_car 17>;
576 reset-names = "pwm";
577 status = "disabled";
578 };
579
580 rtc@7000e000 {
581 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
582 reg = <0x7000e000 0x100>;
583 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&tegra_car TEGRA30_CLK_RTC>;
585 };
586
587 i2c@7000c000 {
588 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
589 reg = <0x7000c000 0x100>;
590 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
591 #address-cells = <1>;
592 #size-cells = <0>;
593 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
594 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
595 clock-names = "div-clk", "fast-clk";
596 resets = <&tegra_car 12>;
597 reset-names = "i2c";
598 dmas = <&apbdma 21>, <&apbdma 21>;
599 dma-names = "rx", "tx";
600 status = "disabled";
601 };
602
603 i2c@7000c400 {
604 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
605 reg = <0x7000c400 0x100>;
606 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
607 #address-cells = <1>;
608 #size-cells = <0>;
609 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
610 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
611 clock-names = "div-clk", "fast-clk";
612 resets = <&tegra_car 54>;
613 reset-names = "i2c";
614 dmas = <&apbdma 22>, <&apbdma 22>;
615 dma-names = "rx", "tx";
616 status = "disabled";
617 };
618
619 i2c@7000c500 {
620 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
621 reg = <0x7000c500 0x100>;
622 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
623 #address-cells = <1>;
624 #size-cells = <0>;
625 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
626 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
627 clock-names = "div-clk", "fast-clk";
628 resets = <&tegra_car 67>;
629 reset-names = "i2c";
630 dmas = <&apbdma 23>, <&apbdma 23>;
631 dma-names = "rx", "tx";
632 status = "disabled";
633 };
634
635 i2c@7000c700 {
636 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
637 reg = <0x7000c700 0x100>;
638 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
639 #address-cells = <1>;
640 #size-cells = <0>;
641 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
642 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
643 resets = <&tegra_car 103>;
644 reset-names = "i2c";
645 clock-names = "div-clk", "fast-clk";
646 dmas = <&apbdma 26>, <&apbdma 26>;
647 dma-names = "rx", "tx";
648 status = "disabled";
649 };
650
651 i2c@7000d000 {
652 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
653 reg = <0x7000d000 0x100>;
654 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
655 #address-cells = <1>;
656 #size-cells = <0>;
657 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
658 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
659 clock-names = "div-clk", "fast-clk";
660 resets = <&tegra_car 47>;
661 reset-names = "i2c";
662 dmas = <&apbdma 24>, <&apbdma 24>;
663 dma-names = "rx", "tx";
664 status = "disabled";
665 };
666
667 spi@7000d400 {
668 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
669 reg = <0x7000d400 0x200>;
670 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
671 #address-cells = <1>;
672 #size-cells = <0>;
673 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
674 resets = <&tegra_car 41>;
675 reset-names = "spi";
676 dmas = <&apbdma 15>, <&apbdma 15>;
677 dma-names = "rx", "tx";
678 status = "disabled";
679 };
680
681 spi@7000d600 {
682 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
683 reg = <0x7000d600 0x200>;
684 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
685 #address-cells = <1>;
686 #size-cells = <0>;
687 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
688 resets = <&tegra_car 44>;
689 reset-names = "spi";
690 dmas = <&apbdma 16>, <&apbdma 16>;
691 dma-names = "rx", "tx";
692 status = "disabled";
693 };
694
695 spi@7000d800 {
696 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
697 reg = <0x7000d800 0x200>;
698 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
699 #address-cells = <1>;
700 #size-cells = <0>;
701 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
702 resets = <&tegra_car 46>;
703 reset-names = "spi";
704 dmas = <&apbdma 17>, <&apbdma 17>;
705 dma-names = "rx", "tx";
706 status = "disabled";
707 };
708
709 spi@7000da00 {
710 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
711 reg = <0x7000da00 0x200>;
712 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
713 #address-cells = <1>;
714 #size-cells = <0>;
715 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
716 resets = <&tegra_car 68>;
717 reset-names = "spi";
718 dmas = <&apbdma 18>, <&apbdma 18>;
719 dma-names = "rx", "tx";
720 status = "disabled";
721 };
722
723 spi@7000dc00 {
724 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
725 reg = <0x7000dc00 0x200>;
726 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
727 #address-cells = <1>;
728 #size-cells = <0>;
729 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
730 resets = <&tegra_car 104>;
731 reset-names = "spi";
732 dmas = <&apbdma 27>, <&apbdma 27>;
733 dma-names = "rx", "tx";
734 status = "disabled";
735 };
736
737 spi@7000de00 {
738 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
739 reg = <0x7000de00 0x200>;
740 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
741 #address-cells = <1>;
742 #size-cells = <0>;
743 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
744 resets = <&tegra_car 106>;
745 reset-names = "spi";
746 dmas = <&apbdma 28>, <&apbdma 28>;
747 dma-names = "rx", "tx";
748 status = "disabled";
749 };
750
751 kbc@7000e200 {
752 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
753 reg = <0x7000e200 0x100>;
754 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&tegra_car TEGRA30_CLK_KBC>;
756 resets = <&tegra_car 36>;
757 reset-names = "kbc";
758 status = "disabled";
759 };
760
761 tegra_pmc: pmc@7000e400 {
762 compatible = "nvidia,tegra30-pmc";
763 reg = <0x7000e400 0x400>;
764 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
765 clock-names = "pclk", "clk32k_in";
766 #clock-cells = <1>;
767 };
768
769 mc: memory-controller@7000f000 {
770 compatible = "nvidia,tegra30-mc";
771 reg = <0x7000f000 0x400>;
772 clocks = <&tegra_car TEGRA30_CLK_MC>;
773 clock-names = "mc";
774
775 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
776
777 #iommu-cells = <1>;
778 #reset-cells = <1>;
779 #interconnect-cells = <1>;
780 };
781
782 emc: memory-controller@7000f400 {
783 compatible = "nvidia,tegra30-emc";
784 reg = <0x7000f400 0x400>;
785 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&tegra_car TEGRA30_CLK_EMC>;
787
788 nvidia,memory-controller = <&mc>;
789 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
790
791 #interconnect-cells = <0>;
792 };
793
794 fuse@7000f800 {
795 compatible = "nvidia,tegra30-efuse";
796 reg = <0x7000f800 0x400>;
797 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
798 clock-names = "fuse";
799 resets = <&tegra_car 39>;
800 reset-names = "fuse";
801 };
802
803 hda@70030000 {
804 compatible = "nvidia,tegra30-hda";
805 reg = <0x70030000 0x10000>;
806 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&tegra_car TEGRA30_CLK_HDA>,
808 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
809 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
810 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
811 resets = <&tegra_car 125>, /* hda */
812 <&tegra_car 128>, /* hda2hdmi */
813 <&tegra_car 111>; /* hda2codec_2x */
814 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
815 status = "disabled";
816 };
817
818 ahub@70080000 {
819 compatible = "nvidia,tegra30-ahub";
820 reg = <0x70080000 0x200>,
821 <0x70080200 0x100>;
822 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
824 <&tegra_car TEGRA30_CLK_APBIF>;
825 clock-names = "d_audio", "apbif";
826 resets = <&tegra_car 106>, /* d_audio */
827 <&tegra_car 107>, /* apbif */
828 <&tegra_car 30>, /* i2s0 */
829 <&tegra_car 11>, /* i2s1 */
830 <&tegra_car 18>, /* i2s2 */
831 <&tegra_car 101>, /* i2s3 */
832 <&tegra_car 102>, /* i2s4 */
833 <&tegra_car 108>, /* dam0 */
834 <&tegra_car 109>, /* dam1 */
835 <&tegra_car 110>, /* dam2 */
836 <&tegra_car 10>; /* spdif */
837 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
838 "i2s3", "i2s4", "dam0", "dam1", "dam2",
839 "spdif";
840 dmas = <&apbdma 1>, <&apbdma 1>,
841 <&apbdma 2>, <&apbdma 2>,
842 <&apbdma 3>, <&apbdma 3>,
843 <&apbdma 4>, <&apbdma 4>;
844 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
845 "rx3", "tx3";
846 ranges;
847 #address-cells = <1>;
848 #size-cells = <1>;
849
850 tegra_i2s0: i2s@70080300 {
851 compatible = "nvidia,tegra30-i2s";
852 reg = <0x70080300 0x100>;
853 nvidia,ahub-cif-ids = <4 4>;
854 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
855 resets = <&tegra_car 30>;
856 reset-names = "i2s";
857 status = "disabled";
858 };
859
860 tegra_i2s1: i2s@70080400 {
861 compatible = "nvidia,tegra30-i2s";
862 reg = <0x70080400 0x100>;
863 nvidia,ahub-cif-ids = <5 5>;
864 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
865 resets = <&tegra_car 11>;
866 reset-names = "i2s";
867 status = "disabled";
868 };
869
870 tegra_i2s2: i2s@70080500 {
871 compatible = "nvidia,tegra30-i2s";
872 reg = <0x70080500 0x100>;
873 nvidia,ahub-cif-ids = <6 6>;
874 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
875 resets = <&tegra_car 18>;
876 reset-names = "i2s";
877 status = "disabled";
878 };
879
880 tegra_i2s3: i2s@70080600 {
881 compatible = "nvidia,tegra30-i2s";
882 reg = <0x70080600 0x100>;
883 nvidia,ahub-cif-ids = <7 7>;
884 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
885 resets = <&tegra_car 101>;
886 reset-names = "i2s";
887 status = "disabled";
888 };
889
890 tegra_i2s4: i2s@70080700 {
891 compatible = "nvidia,tegra30-i2s";
892 reg = <0x70080700 0x100>;
893 nvidia,ahub-cif-ids = <8 8>;
894 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
895 resets = <&tegra_car 102>;
896 reset-names = "i2s";
897 status = "disabled";
898 };
899 };
900
901 mmc@78000000 {
902 compatible = "nvidia,tegra30-sdhci";
903 reg = <0x78000000 0x200>;
904 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
906 clock-names = "sdhci";
907 resets = <&tegra_car 14>;
908 reset-names = "sdhci";
909 status = "disabled";
910 };
911
912 mmc@78000200 {
913 compatible = "nvidia,tegra30-sdhci";
914 reg = <0x78000200 0x200>;
915 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
917 clock-names = "sdhci";
918 resets = <&tegra_car 9>;
919 reset-names = "sdhci";
920 status = "disabled";
921 };
922
923 mmc@78000400 {
924 compatible = "nvidia,tegra30-sdhci";
925 reg = <0x78000400 0x200>;
926 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
928 clock-names = "sdhci";
929 resets = <&tegra_car 69>;
930 reset-names = "sdhci";
931 status = "disabled";
932 };
933
934 mmc@78000600 {
935 compatible = "nvidia,tegra30-sdhci";
936 reg = <0x78000600 0x200>;
937 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
939 clock-names = "sdhci";
940 resets = <&tegra_car 15>;
941 reset-names = "sdhci";
942 status = "disabled";
943 };
944
945 usb@7d000000 {
946 compatible = "nvidia,tegra30-ehci", "usb-ehci";
947 reg = <0x7d000000 0x4000>;
948 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
949 phy_type = "utmi";
950 clocks = <&tegra_car TEGRA30_CLK_USBD>;
951 resets = <&tegra_car 22>;
952 reset-names = "usb";
953 nvidia,needs-double-reset;
954 nvidia,phy = <&phy1>;
955 status = "disabled";
956 };
957
958 phy1: usb-phy@7d000000 {
959 compatible = "nvidia,tegra30-usb-phy";
960 reg = <0x7d000000 0x4000>,
961 <0x7d000000 0x4000>;
962 phy_type = "utmi";
963 clocks = <&tegra_car TEGRA30_CLK_USBD>,
964 <&tegra_car TEGRA30_CLK_PLL_U>,
965 <&tegra_car TEGRA30_CLK_USBD>;
966 clock-names = "reg", "pll_u", "utmi-pads";
967 resets = <&tegra_car 22>, <&tegra_car 22>;
968 reset-names = "usb", "utmi-pads";
969 #phy-cells = <0>;
970 nvidia,hssync-start-delay = <9>;
971 nvidia,idle-wait-delay = <17>;
972 nvidia,elastic-limit = <16>;
973 nvidia,term-range-adj = <6>;
974 nvidia,xcvr-setup = <51>;
975 nvidia,xcvr-setup-use-fuses;
976 nvidia,xcvr-lsfslew = <1>;
977 nvidia,xcvr-lsrslew = <1>;
978 nvidia,xcvr-hsslew = <32>;
979 nvidia,hssquelch-level = <2>;
980 nvidia,hsdiscon-level = <5>;
981 nvidia,has-utmi-pad-registers;
982 status = "disabled";
983 };
984
985 usb@7d004000 {
986 compatible = "nvidia,tegra30-ehci", "usb-ehci";
987 reg = <0x7d004000 0x4000>;
988 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
989 phy_type = "utmi";
990 clocks = <&tegra_car TEGRA30_CLK_USB2>;
991 resets = <&tegra_car 58>;
992 reset-names = "usb";
993 nvidia,phy = <&phy2>;
994 status = "disabled";
995 };
996
997 phy2: usb-phy@7d004000 {
998 compatible = "nvidia,tegra30-usb-phy";
999 reg = <0x7d004000 0x4000>,
1000 <0x7d000000 0x4000>;
1001 phy_type = "utmi";
1002 clocks = <&tegra_car TEGRA30_CLK_USB2>,
1003 <&tegra_car TEGRA30_CLK_PLL_U>,
1004 <&tegra_car TEGRA30_CLK_USBD>;
1005 clock-names = "reg", "pll_u", "utmi-pads";
1006 resets = <&tegra_car 58>, <&tegra_car 22>;
1007 reset-names = "usb", "utmi-pads";
1008 #phy-cells = <0>;
1009 nvidia,hssync-start-delay = <9>;
1010 nvidia,idle-wait-delay = <17>;
1011 nvidia,elastic-limit = <16>;
1012 nvidia,term-range-adj = <6>;
1013 nvidia,xcvr-setup = <51>;
1014 nvidia,xcvr-setup-use-fuses;
1015 nvidia,xcvr-lsfslew = <2>;
1016 nvidia,xcvr-lsrslew = <2>;
1017 nvidia,xcvr-hsslew = <32>;
1018 nvidia,hssquelch-level = <2>;
1019 nvidia,hsdiscon-level = <5>;
1020 status = "disabled";
1021 };
1022
1023 usb@7d008000 {
1024 compatible = "nvidia,tegra30-ehci", "usb-ehci";
1025 reg = <0x7d008000 0x4000>;
1026 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1027 phy_type = "utmi";
1028 clocks = <&tegra_car TEGRA30_CLK_USB3>;
1029 resets = <&tegra_car 59>;
1030 reset-names = "usb";
1031 nvidia,phy = <&phy3>;
1032 status = "disabled";
1033 };
1034
1035 phy3: usb-phy@7d008000 {
1036 compatible = "nvidia,tegra30-usb-phy";
1037 reg = <0x7d008000 0x4000>,
1038 <0x7d000000 0x4000>;
1039 phy_type = "utmi";
1040 clocks = <&tegra_car TEGRA30_CLK_USB3>,
1041 <&tegra_car TEGRA30_CLK_PLL_U>,
1042 <&tegra_car TEGRA30_CLK_USBD>;
1043 clock-names = "reg", "pll_u", "utmi-pads";
1044 resets = <&tegra_car 59>, <&tegra_car 22>;
1045 reset-names = "usb", "utmi-pads";
1046 #phy-cells = <0>;
1047 nvidia,hssync-start-delay = <0>;
1048 nvidia,idle-wait-delay = <17>;
1049 nvidia,elastic-limit = <16>;
1050 nvidia,term-range-adj = <6>;
1051 nvidia,xcvr-setup = <51>;
1052 nvidia,xcvr-setup-use-fuses;
1053 nvidia,xcvr-lsfslew = <2>;
1054 nvidia,xcvr-lsrslew = <2>;
1055 nvidia,xcvr-hsslew = <32>;
1056 nvidia,hssquelch-level = <2>;
1057 nvidia,hsdiscon-level = <5>;
1058 status = "disabled";
1059 };
1060
1061 cpus {
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1064
1065 cpu@0 {
1066 device_type = "cpu";
1067 compatible = "arm,cortex-a9";
1068 reg = <0>;
1069 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1070 };
1071
1072 cpu@1 {
1073 device_type = "cpu";
1074 compatible = "arm,cortex-a9";
1075 reg = <1>;
1076 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1077 };
1078
1079 cpu@2 {
1080 device_type = "cpu";
1081 compatible = "arm,cortex-a9";
1082 reg = <2>;
1083 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1084 };
1085
1086 cpu@3 {
1087 device_type = "cpu";
1088 compatible = "arm,cortex-a9";
1089 reg = <3>;
1090 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1091 };
1092 };
1093
1094 pmu {
1095 compatible = "arm,cortex-a9-pmu";
1096 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1100 interrupt-affinity = <&{/cpus/cpu@0}>,
1101 <&{/cpus/cpu@1}>,
1102 <&{/cpus/cpu@2}>,
1103 <&{/cpus/cpu@3}>;
1104 };
1105};