Loading...
Note: File does not exist in v4.17.
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8&pinctrl {
9 adc1_in6_pins_a: adc1-in6-0 {
10 pins {
11 pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
12 };
13 };
14
15 adc12_ain_pins_a: adc12-ain-0 {
16 pins {
17 pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */
18 <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
19 <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */
20 <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */
21 };
22 };
23
24 adc12_ain_pins_b: adc12-ain-1 {
25 pins {
26 pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
27 <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */
28 };
29 };
30
31 adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 {
32 pins {
33 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
34 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
35 };
36 };
37
38 cec_pins_a: cec-0 {
39 pins {
40 pinmux = <STM32_PINMUX('A', 15, AF4)>;
41 bias-disable;
42 drive-open-drain;
43 slew-rate = <0>;
44 };
45 };
46
47 cec_sleep_pins_a: cec-sleep-0 {
48 pins {
49 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
50 };
51 };
52
53 cec_pins_b: cec-1 {
54 pins {
55 pinmux = <STM32_PINMUX('B', 6, AF5)>;
56 bias-disable;
57 drive-open-drain;
58 slew-rate = <0>;
59 };
60 };
61
62 cec_sleep_pins_b: cec-sleep-1 {
63 pins {
64 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
65 };
66 };
67
68 dac_ch1_pins_a: dac-ch1-0 {
69 pins {
70 pinmux = <STM32_PINMUX('A', 4, ANALOG)>;
71 };
72 };
73
74 dac_ch2_pins_a: dac-ch2-0 {
75 pins {
76 pinmux = <STM32_PINMUX('A', 5, ANALOG)>;
77 };
78 };
79
80 dcmi_pins_a: dcmi-0 {
81 pins {
82 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
83 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
84 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
85 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
86 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
87 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
88 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
89 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
90 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
91 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
92 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
93 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
94 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
95 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
96 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
97 bias-disable;
98 };
99 };
100
101 dcmi_sleep_pins_a: dcmi-sleep-0 {
102 pins {
103 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
104 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
105 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
106 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
107 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
108 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
109 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
110 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
111 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
112 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
113 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
114 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
115 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
116 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
117 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
118 };
119 };
120
121 dcmi_pins_b: dcmi-1 {
122 pins {
123 pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
124 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
125 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
126 <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
127 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
128 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
129 <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
130 <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
131 <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
132 <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
133 <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
134 bias-disable;
135 };
136 };
137
138 dcmi_sleep_pins_b: dcmi-sleep-1 {
139 pins {
140 pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
141 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
142 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
143 <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
144 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
145 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
146 <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
147 <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
148 <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
149 <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
150 <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
151 };
152 };
153
154 ethernet0_rgmii_pins_a: rgmii-0 {
155 pins1 {
156 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
157 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
158 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
159 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
160 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
161 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
162 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
163 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
164 bias-disable;
165 drive-push-pull;
166 slew-rate = <2>;
167 };
168 pins2 {
169 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
170 bias-disable;
171 drive-push-pull;
172 slew-rate = <0>;
173 };
174 pins3 {
175 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
176 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
177 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
178 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
179 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
180 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
181 bias-disable;
182 };
183 };
184
185 ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 {
186 pins1 {
187 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
188 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
189 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
190 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
191 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
192 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
193 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
194 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
195 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
196 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
197 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
198 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
199 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
200 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
201 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
202 };
203 };
204
205 ethernet0_rgmii_pins_b: rgmii-1 {
206 pins1 {
207 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
208 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
209 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
210 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
211 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
212 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
213 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
214 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
215 bias-disable;
216 drive-push-pull;
217 slew-rate = <2>;
218 };
219 pins2 {
220 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
221 bias-disable;
222 drive-push-pull;
223 slew-rate = <0>;
224 };
225 pins3 {
226 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
227 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
228 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
229 <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */
230 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
231 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
232 bias-disable;
233 };
234 };
235
236 ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 {
237 pins1 {
238 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
239 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
240 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
241 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
242 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
243 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
244 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
245 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
246 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
247 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
248 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
249 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
250 <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */
251 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
252 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
253 };
254 };
255
256 ethernet0_rgmii_pins_c: rgmii-2 {
257 pins1 {
258 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
259 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
260 <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */
261 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
262 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
263 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
264 <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */
265 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
266 bias-disable;
267 drive-push-pull;
268 slew-rate = <2>;
269 };
270 pins2 {
271 pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
272 bias-disable;
273 drive-push-pull;
274 slew-rate = <0>;
275 };
276 pins3 {
277 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
278 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
279 <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */
280 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
281 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
282 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
283 bias-disable;
284 };
285 };
286
287 ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 {
288 pins1 {
289 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
290 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
291 <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */
292 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
293 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
294 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
295 <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
296 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
297 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
298 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
299 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
300 <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */
301 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
302 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
303 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
304 };
305 };
306
307 ethernet0_rmii_pins_a: rmii-0 {
308 pins1 {
309 pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
310 <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
311 <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
312 <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */
313 <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
314 <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
315 bias-disable;
316 drive-push-pull;
317 slew-rate = <2>;
318 };
319 pins2 {
320 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
321 <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
322 <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
323 bias-disable;
324 };
325 };
326
327 ethernet0_rmii_sleep_pins_a: rmii-sleep-0 {
328 pins1 {
329 pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
330 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
331 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
332 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
333 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
334 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
335 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
336 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
337 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
338 };
339 };
340
341 fmc_pins_a: fmc-0 {
342 pins1 {
343 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
344 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
345 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
346 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
347 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
348 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
349 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
350 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
351 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
352 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
353 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
354 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
355 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
356 bias-disable;
357 drive-push-pull;
358 slew-rate = <1>;
359 };
360 pins2 {
361 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
362 bias-pull-up;
363 };
364 };
365
366 fmc_sleep_pins_a: fmc-sleep-0 {
367 pins {
368 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
369 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
370 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
371 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
372 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
373 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
374 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
375 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
376 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
377 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
378 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
379 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
380 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
381 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
382 };
383 };
384
385 fmc_pins_b: fmc-1 {
386 pins {
387 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
388 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
389 <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
390 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
391 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
392 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
393 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
394 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
395 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
396 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
397 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
398 <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
399 <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
400 <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
401 <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
402 <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
403 <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
404 <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
405 <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
406 <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
407 <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
408 bias-disable;
409 drive-push-pull;
410 slew-rate = <3>;
411 };
412 };
413
414 fmc_sleep_pins_b: fmc-sleep-1 {
415 pins {
416 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
417 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
418 <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
419 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
420 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
421 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
422 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
423 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
424 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
425 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
426 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
427 <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
428 <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
429 <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
430 <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
431 <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
432 <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
433 <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
434 <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
435 <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
436 <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
437 };
438 };
439
440 i2c1_pins_a: i2c1-0 {
441 pins {
442 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
443 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
444 bias-disable;
445 drive-open-drain;
446 slew-rate = <0>;
447 };
448 };
449
450 i2c1_sleep_pins_a: i2c1-sleep-0 {
451 pins {
452 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
453 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
454 };
455 };
456
457 i2c1_pins_b: i2c1-1 {
458 pins {
459 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
460 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
461 bias-disable;
462 drive-open-drain;
463 slew-rate = <0>;
464 };
465 };
466
467 i2c1_sleep_pins_b: i2c1-sleep-1 {
468 pins {
469 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
470 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
471 };
472 };
473
474 i2c2_pins_a: i2c2-0 {
475 pins {
476 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
477 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
478 bias-disable;
479 drive-open-drain;
480 slew-rate = <0>;
481 };
482 };
483
484 i2c2_sleep_pins_a: i2c2-sleep-0 {
485 pins {
486 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
487 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
488 };
489 };
490
491 i2c2_pins_b1: i2c2-1 {
492 pins {
493 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
494 bias-disable;
495 drive-open-drain;
496 slew-rate = <0>;
497 };
498 };
499
500 i2c2_sleep_pins_b1: i2c2-sleep-1 {
501 pins {
502 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
503 };
504 };
505
506 i2c2_pins_c: i2c2-2 {
507 pins {
508 pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */
509 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
510 bias-disable;
511 drive-open-drain;
512 slew-rate = <0>;
513 };
514 };
515
516 i2c2_pins_sleep_c: i2c2-sleep-2 {
517 pins {
518 pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */
519 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
520 };
521 };
522
523 i2c5_pins_a: i2c5-0 {
524 pins {
525 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
526 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
527 bias-disable;
528 drive-open-drain;
529 slew-rate = <0>;
530 };
531 };
532
533 i2c5_sleep_pins_a: i2c5-sleep-0 {
534 pins {
535 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
536 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
537
538 };
539 };
540
541 i2c5_pins_b: i2c5-1 {
542 pins {
543 pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */
544 <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */
545 bias-disable;
546 drive-open-drain;
547 slew-rate = <0>;
548 };
549 };
550
551 i2c5_sleep_pins_b: i2c5-sleep-1 {
552 pins {
553 pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */
554 <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */
555 };
556 };
557
558 i2s2_pins_a: i2s2-0 {
559 pins {
560 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
561 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
562 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
563 slew-rate = <1>;
564 drive-push-pull;
565 bias-disable;
566 };
567 };
568
569 i2s2_sleep_pins_a: i2s2-sleep-0 {
570 pins {
571 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
572 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
573 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
574 };
575 };
576
577 ltdc_pins_a: ltdc-0 {
578 pins {
579 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
580 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
581 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
582 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
583 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
584 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
585 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
586 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
587 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
588 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
589 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
590 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
591 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
592 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
593 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
594 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
595 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
596 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
597 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
598 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
599 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
600 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
601 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
602 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
603 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
604 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
605 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
606 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
607 bias-disable;
608 drive-push-pull;
609 slew-rate = <1>;
610 };
611 };
612
613 ltdc_sleep_pins_a: ltdc-sleep-0 {
614 pins {
615 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
616 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
617 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
618 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
619 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
620 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
621 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
622 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
623 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
624 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
625 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
626 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
627 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
628 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
629 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
630 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
631 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
632 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
633 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
634 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
635 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
636 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
637 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
638 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
639 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
640 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
641 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
642 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
643 };
644 };
645
646 ltdc_pins_b: ltdc-1 {
647 pins {
648 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
649 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
650 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
651 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
652 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
653 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
654 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
655 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
656 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
657 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
658 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
659 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
660 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
661 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
662 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
663 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
664 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
665 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
666 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
667 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
668 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
669 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
670 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
671 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
672 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
673 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
674 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
675 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
676 bias-disable;
677 drive-push-pull;
678 slew-rate = <1>;
679 };
680 };
681
682 ltdc_sleep_pins_b: ltdc-sleep-1 {
683 pins {
684 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
685 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
686 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
687 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
688 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
689 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
690 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
691 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
692 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
693 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
694 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
695 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
696 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
697 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
698 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
699 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
700 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
701 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
702 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
703 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
704 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
705 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
706 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
707 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
708 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
709 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
710 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
711 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
712 };
713 };
714
715 ltdc_pins_c: ltdc-2 {
716 pins1 {
717 pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */
718 <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */
719 <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */
720 <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */
721 <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */
722 <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
723 <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */
724 <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */
725 <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */
726 <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */
727 <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */
728 <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */
729 <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
730 <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */
731 <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */
732 <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */
733 <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
734 <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */
735 <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */
736 <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
737 <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */
738 bias-disable;
739 drive-push-pull;
740 slew-rate = <0>;
741 };
742 pins2 {
743 pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */
744 bias-disable;
745 drive-push-pull;
746 slew-rate = <1>;
747 };
748 };
749
750 ltdc_sleep_pins_c: ltdc-sleep-2 {
751 pins1 {
752 pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */
753 <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */
754 <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */
755 <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */
756 <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */
757 <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */
758 <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */
759 <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */
760 <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */
761 <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */
762 <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */
763 <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */
764 <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */
765 <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */
766 <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */
767 <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */
768 <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */
769 <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */
770 <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */
771 <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */
772 <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */
773 <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */
774 };
775 };
776
777 ltdc_pins_d: ltdc-3 {
778 pins1 {
779 pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */
780 bias-disable;
781 drive-push-pull;
782 slew-rate = <3>;
783 };
784 pins2 {
785 pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
786 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
787 <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */
788 <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */
789 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
790 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
791 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
792 <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */
793 <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */
794 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
795 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
796 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
797 <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */
798 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
799 <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */
800 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
801 <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */
802 <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */
803 <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */
804 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
805 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
806 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
807 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
808 <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */
809 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
810 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
811 <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */
812 bias-disable;
813 drive-push-pull;
814 slew-rate = <2>;
815 };
816 };
817
818 ltdc_sleep_pins_d: ltdc-sleep-3 {
819 pins {
820 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
821 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
822 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
823 <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */
824 <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */
825 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
826 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
827 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
828 <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */
829 <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */
830 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
831 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
832 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
833 <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */
834 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
835 <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */
836 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
837 <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */
838 <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */
839 <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */
840 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
841 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
842 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
843 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
844 <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */
845 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
846 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
847 <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */
848 };
849 };
850
851 m_can1_pins_a: m-can1-0 {
852 pins1 {
853 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
854 slew-rate = <1>;
855 drive-push-pull;
856 bias-disable;
857 };
858 pins2 {
859 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
860 bias-disable;
861 };
862 };
863
864 m_can1_sleep_pins_a: m_can1-sleep-0 {
865 pins {
866 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
867 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
868 };
869 };
870
871 m_can1_pins_b: m-can1-1 {
872 pins1 {
873 pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
874 slew-rate = <1>;
875 drive-push-pull;
876 bias-disable;
877 };
878 pins2 {
879 pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
880 bias-disable;
881 };
882 };
883
884 m_can1_sleep_pins_b: m_can1-sleep-1 {
885 pins {
886 pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */
887 <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */
888 };
889 };
890
891 m_can2_pins_a: m-can2-0 {
892 pins1 {
893 pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
894 slew-rate = <1>;
895 drive-push-pull;
896 bias-disable;
897 };
898 pins2 {
899 pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
900 bias-disable;
901 };
902 };
903
904 m_can2_sleep_pins_a: m_can2-sleep-0 {
905 pins {
906 pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */
907 <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */
908 };
909 };
910
911 pwm1_pins_a: pwm1-0 {
912 pins {
913 pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */
914 <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */
915 <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */
916 bias-pull-down;
917 drive-push-pull;
918 slew-rate = <0>;
919 };
920 };
921
922 pwm1_sleep_pins_a: pwm1-sleep-0 {
923 pins {
924 pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */
925 <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */
926 <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */
927 };
928 };
929
930 pwm2_pins_a: pwm2-0 {
931 pins {
932 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
933 bias-pull-down;
934 drive-push-pull;
935 slew-rate = <0>;
936 };
937 };
938
939 pwm2_sleep_pins_a: pwm2-sleep-0 {
940 pins {
941 pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */
942 };
943 };
944
945 pwm3_pins_a: pwm3-0 {
946 pins {
947 pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */
948 bias-pull-down;
949 drive-push-pull;
950 slew-rate = <0>;
951 };
952 };
953
954 pwm3_sleep_pins_a: pwm3-sleep-0 {
955 pins {
956 pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */
957 };
958 };
959
960 pwm3_pins_b: pwm3-1 {
961 pins {
962 pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
963 bias-disable;
964 drive-push-pull;
965 slew-rate = <0>;
966 };
967 };
968
969 pwm3_sleep_pins_b: pwm3-sleep-1 {
970 pins {
971 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */
972 };
973 };
974
975 pwm4_pins_a: pwm4-0 {
976 pins {
977 pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */
978 <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */
979 bias-pull-down;
980 drive-push-pull;
981 slew-rate = <0>;
982 };
983 };
984
985 pwm4_sleep_pins_a: pwm4-sleep-0 {
986 pins {
987 pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */
988 <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */
989 };
990 };
991
992 pwm4_pins_b: pwm4-1 {
993 pins {
994 pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
995 bias-pull-down;
996 drive-push-pull;
997 slew-rate = <0>;
998 };
999 };
1000
1001 pwm4_sleep_pins_b: pwm4-sleep-1 {
1002 pins {
1003 pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
1004 };
1005 };
1006
1007 pwm5_pins_a: pwm5-0 {
1008 pins {
1009 pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */
1010 bias-pull-down;
1011 drive-push-pull;
1012 slew-rate = <0>;
1013 };
1014 };
1015
1016 pwm5_sleep_pins_a: pwm5-sleep-0 {
1017 pins {
1018 pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */
1019 };
1020 };
1021
1022 pwm5_pins_b: pwm5-1 {
1023 pins {
1024 pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */
1025 <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */
1026 <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */
1027 bias-disable;
1028 drive-push-pull;
1029 slew-rate = <0>;
1030 };
1031 };
1032
1033 pwm5_sleep_pins_b: pwm5-sleep-1 {
1034 pins {
1035 pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */
1036 <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */
1037 <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */
1038 };
1039 };
1040
1041 pwm8_pins_a: pwm8-0 {
1042 pins {
1043 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
1044 bias-pull-down;
1045 drive-push-pull;
1046 slew-rate = <0>;
1047 };
1048 };
1049
1050 pwm8_sleep_pins_a: pwm8-sleep-0 {
1051 pins {
1052 pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */
1053 };
1054 };
1055
1056 pwm12_pins_a: pwm12-0 {
1057 pins {
1058 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
1059 bias-pull-down;
1060 drive-push-pull;
1061 slew-rate = <0>;
1062 };
1063 };
1064
1065 pwm12_sleep_pins_a: pwm12-sleep-0 {
1066 pins {
1067 pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */
1068 };
1069 };
1070
1071 qspi_clk_pins_a: qspi-clk-0 {
1072 pins {
1073 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
1074 bias-disable;
1075 drive-push-pull;
1076 slew-rate = <3>;
1077 };
1078 };
1079
1080 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
1081 pins {
1082 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
1083 };
1084 };
1085
1086 qspi_bk1_pins_a: qspi-bk1-0 {
1087 pins1 {
1088 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
1089 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
1090 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
1091 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
1092 bias-disable;
1093 drive-push-pull;
1094 slew-rate = <1>;
1095 };
1096 pins2 {
1097 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
1098 bias-pull-up;
1099 drive-push-pull;
1100 slew-rate = <1>;
1101 };
1102 };
1103
1104 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
1105 pins {
1106 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
1107 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
1108 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
1109 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
1110 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
1111 };
1112 };
1113
1114 qspi_bk2_pins_a: qspi-bk2-0 {
1115 pins1 {
1116 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
1117 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
1118 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
1119 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
1120 bias-disable;
1121 drive-push-pull;
1122 slew-rate = <1>;
1123 };
1124 pins2 {
1125 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
1126 bias-pull-up;
1127 drive-push-pull;
1128 slew-rate = <1>;
1129 };
1130 };
1131
1132 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
1133 pins {
1134 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
1135 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
1136 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
1137 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
1138 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
1139 };
1140 };
1141
1142 sai2a_pins_a: sai2a-0 {
1143 pins {
1144 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
1145 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
1146 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
1147 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
1148 slew-rate = <0>;
1149 drive-push-pull;
1150 bias-disable;
1151 };
1152 };
1153
1154 sai2a_sleep_pins_a: sai2a-sleep-0 {
1155 pins {
1156 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
1157 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
1158 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
1159 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
1160 };
1161 };
1162
1163 sai2a_pins_b: sai2a-1 {
1164 pins1 {
1165 pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
1166 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
1167 <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */
1168 slew-rate = <0>;
1169 drive-push-pull;
1170 bias-disable;
1171 };
1172 };
1173
1174 sai2a_sleep_pins_b: sai2a-sleep-1 {
1175 pins {
1176 pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
1177 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
1178 <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */
1179 };
1180 };
1181
1182 sai2a_pins_c: sai2a-4 {
1183 pins {
1184 pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */
1185 <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */
1186 <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */
1187 slew-rate = <0>;
1188 drive-push-pull;
1189 bias-disable;
1190 };
1191 };
1192
1193 sai2a_sleep_pins_c: sai2a-5 {
1194 pins {
1195 pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */
1196 <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */
1197 <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */
1198 };
1199 };
1200
1201 sai2b_pins_a: sai2b-0 {
1202 pins1 {
1203 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
1204 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
1205 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
1206 slew-rate = <0>;
1207 drive-push-pull;
1208 bias-disable;
1209 };
1210 pins2 {
1211 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1212 bias-disable;
1213 };
1214 };
1215
1216 sai2b_sleep_pins_a: sai2b-sleep-0 {
1217 pins {
1218 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
1219 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
1220 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
1221 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
1222 };
1223 };
1224
1225 sai2b_pins_b: sai2b-1 {
1226 pins {
1227 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1228 bias-disable;
1229 };
1230 };
1231
1232 sai2b_sleep_pins_b: sai2b-sleep-1 {
1233 pins {
1234 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
1235 };
1236 };
1237
1238 sai2b_pins_c: sai2a-4 {
1239 pins1 {
1240 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
1241 bias-disable;
1242 };
1243 };
1244
1245 sai2b_sleep_pins_c: sai2a-sleep-5 {
1246 pins {
1247 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
1248 };
1249 };
1250
1251 sai4a_pins_a: sai4a-0 {
1252 pins {
1253 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
1254 slew-rate = <0>;
1255 drive-push-pull;
1256 bias-disable;
1257 };
1258 };
1259
1260 sai4a_sleep_pins_a: sai4a-sleep-0 {
1261 pins {
1262 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
1263 };
1264 };
1265
1266 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
1267 pins1 {
1268 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
1269 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1270 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
1271 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
1272 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1273 slew-rate = <1>;
1274 drive-push-pull;
1275 bias-disable;
1276 };
1277 pins2 {
1278 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
1279 slew-rate = <2>;
1280 drive-push-pull;
1281 bias-disable;
1282 };
1283 };
1284
1285 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
1286 pins1 {
1287 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
1288 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1289 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
1290 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
1291 slew-rate = <1>;
1292 drive-push-pull;
1293 bias-disable;
1294 };
1295 pins2 {
1296 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
1297 slew-rate = <2>;
1298 drive-push-pull;
1299 bias-disable;
1300 };
1301 pins3 {
1302 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
1303 slew-rate = <1>;
1304 drive-open-drain;
1305 bias-disable;
1306 };
1307 };
1308
1309 sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 {
1310 pins1 {
1311 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
1312 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
1313 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
1314 <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
1315 slew-rate = <1>;
1316 drive-push-pull;
1317 bias-disable;
1318 };
1319 };
1320
1321 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
1322 pins {
1323 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
1324 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
1325 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
1326 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
1327 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
1328 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
1329 };
1330 };
1331
1332 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
1333 pins1 {
1334 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
1335 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
1336 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1337 slew-rate = <1>;
1338 drive-push-pull;
1339 bias-pull-up;
1340 };
1341 pins2{
1342 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
1343 bias-pull-up;
1344 };
1345 };
1346
1347 sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 {
1348 pins1 {
1349 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
1350 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
1351 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1352 slew-rate = <1>;
1353 drive-push-pull;
1354 bias-pull-up;
1355 };
1356 };
1357
1358 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
1359 pins {
1360 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
1361 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
1362 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
1363 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
1364 };
1365 };
1366
1367 sdmmc1_dir_pins_b: sdmmc1-dir-1 {
1368 pins1 {
1369 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
1370 <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */
1371 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
1372 slew-rate = <1>;
1373 drive-push-pull;
1374 bias-pull-up;
1375 };
1376 pins2{
1377 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
1378 bias-pull-up;
1379 };
1380 };
1381
1382 sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 {
1383 pins {
1384 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
1385 <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */
1386 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
1387 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
1388 };
1389 };
1390
1391 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
1392 pins1 {
1393 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1394 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1395 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1396 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
1397 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1398 slew-rate = <1>;
1399 drive-push-pull;
1400 bias-pull-up;
1401 };
1402 pins2 {
1403 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1404 slew-rate = <2>;
1405 drive-push-pull;
1406 bias-pull-up;
1407 };
1408 };
1409
1410 sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
1411 pins1 {
1412 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1413 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1414 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1415 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
1416 slew-rate = <1>;
1417 drive-push-pull;
1418 bias-pull-up;
1419 };
1420 pins2 {
1421 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1422 slew-rate = <2>;
1423 drive-push-pull;
1424 bias-pull-up;
1425 };
1426 pins3 {
1427 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1428 slew-rate = <1>;
1429 drive-open-drain;
1430 bias-pull-up;
1431 };
1432 };
1433
1434 sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
1435 pins {
1436 pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
1437 <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
1438 <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
1439 <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
1440 <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
1441 <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
1442 };
1443 };
1444
1445 sdmmc2_b4_pins_b: sdmmc2-b4-1 {
1446 pins1 {
1447 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1448 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1449 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1450 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
1451 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1452 slew-rate = <1>;
1453 drive-push-pull;
1454 bias-disable;
1455 };
1456 pins2 {
1457 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1458 slew-rate = <2>;
1459 drive-push-pull;
1460 bias-disable;
1461 };
1462 };
1463
1464 sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 {
1465 pins1 {
1466 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
1467 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
1468 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
1469 <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */
1470 slew-rate = <1>;
1471 drive-push-pull;
1472 bias-disable;
1473 };
1474 pins2 {
1475 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
1476 slew-rate = <2>;
1477 drive-push-pull;
1478 bias-disable;
1479 };
1480 pins3 {
1481 pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
1482 slew-rate = <1>;
1483 drive-open-drain;
1484 bias-disable;
1485 };
1486 };
1487
1488 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
1489 pins {
1490 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1491 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1492 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
1493 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
1494 slew-rate = <1>;
1495 drive-push-pull;
1496 bias-pull-up;
1497 };
1498 };
1499
1500 sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
1501 pins {
1502 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1503 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1504 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
1505 <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */
1506 };
1507 };
1508
1509 sdmmc2_d47_pins_b: sdmmc2-d47-1 {
1510 pins {
1511 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1512 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1513 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
1514 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
1515 slew-rate = <1>;
1516 drive-push-pull;
1517 bias-disable;
1518 };
1519 };
1520
1521 sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 {
1522 pins {
1523 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1524 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1525 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
1526 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
1527 };
1528 };
1529
1530 sdmmc2_d47_pins_c: sdmmc2-d47-2 {
1531 pins {
1532 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1533 <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */
1534 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
1535 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
1536 slew-rate = <1>;
1537 drive-push-pull;
1538 bias-pull-up;
1539 };
1540 };
1541
1542 sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 {
1543 pins {
1544 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1545 <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */
1546 <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
1547 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
1548 };
1549 };
1550
1551 sdmmc2_d47_pins_d: sdmmc2-d47-3 {
1552 pins {
1553 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
1554 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
1555 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
1556 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
1557 };
1558 };
1559
1560 sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
1561 pins {
1562 pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */
1563 <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */
1564 <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */
1565 <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
1566 };
1567 };
1568
1569 sdmmc3_b4_pins_a: sdmmc3-b4-0 {
1570 pins1 {
1571 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1572 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1573 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
1574 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
1575 <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */
1576 slew-rate = <1>;
1577 drive-push-pull;
1578 bias-pull-up;
1579 };
1580 pins2 {
1581 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
1582 slew-rate = <2>;
1583 drive-push-pull;
1584 bias-pull-up;
1585 };
1586 };
1587
1588 sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 {
1589 pins1 {
1590 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1591 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1592 <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */
1593 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
1594 slew-rate = <1>;
1595 drive-push-pull;
1596 bias-pull-up;
1597 };
1598 pins2 {
1599 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
1600 slew-rate = <2>;
1601 drive-push-pull;
1602 bias-pull-up;
1603 };
1604 pins3 {
1605 pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */
1606 slew-rate = <1>;
1607 drive-open-drain;
1608 bias-pull-up;
1609 };
1610 };
1611
1612 sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 {
1613 pins {
1614 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
1615 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
1616 <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */
1617 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
1618 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
1619 <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */
1620 };
1621 };
1622
1623 sdmmc3_b4_pins_b: sdmmc3-b4-1 {
1624 pins1 {
1625 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1626 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1627 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
1628 <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */
1629 <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */
1630 slew-rate = <1>;
1631 drive-push-pull;
1632 bias-pull-up;
1633 };
1634 pins2 {
1635 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
1636 slew-rate = <2>;
1637 drive-push-pull;
1638 bias-pull-up;
1639 };
1640 };
1641
1642 sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 {
1643 pins1 {
1644 pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */
1645 <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */
1646 <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */
1647 <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */
1648 slew-rate = <1>;
1649 drive-push-pull;
1650 bias-pull-up;
1651 };
1652 pins2 {
1653 pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */
1654 slew-rate = <2>;
1655 drive-push-pull;
1656 bias-pull-up;
1657 };
1658 pins3 {
1659 pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */
1660 slew-rate = <1>;
1661 drive-open-drain;
1662 bias-pull-up;
1663 };
1664 };
1665
1666 sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 {
1667 pins {
1668 pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */
1669 <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */
1670 <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */
1671 <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */
1672 <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */
1673 <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */
1674 };
1675 };
1676
1677 spdifrx_pins_a: spdifrx-0 {
1678 pins {
1679 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
1680 bias-disable;
1681 };
1682 };
1683
1684 spdifrx_sleep_pins_a: spdifrx-sleep-0 {
1685 pins {
1686 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
1687 };
1688 };
1689
1690 spi2_pins_a: spi2-0 {
1691 pins1 {
1692 pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */
1693 <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */
1694 bias-disable;
1695 drive-push-pull;
1696 slew-rate = <1>;
1697 };
1698
1699 pins2 {
1700 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */
1701 bias-disable;
1702 };
1703 };
1704
1705 spi4_pins_a: spi4-0 {
1706 pins {
1707 pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */
1708 <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */
1709 bias-disable;
1710 drive-push-pull;
1711 slew-rate = <1>;
1712 };
1713 pins2 {
1714 pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */
1715 bias-disable;
1716 };
1717 };
1718
1719 stusb1600_pins_a: stusb1600-0 {
1720 pins {
1721 pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
1722 bias-pull-up;
1723 };
1724 };
1725
1726 uart4_pins_a: uart4-0 {
1727 pins1 {
1728 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
1729 bias-disable;
1730 drive-push-pull;
1731 slew-rate = <0>;
1732 };
1733 pins2 {
1734 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1735 bias-disable;
1736 };
1737 };
1738
1739 uart4_idle_pins_a: uart4-idle-0 {
1740 pins1 {
1741 pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */
1742 };
1743 pins2 {
1744 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1745 bias-disable;
1746 };
1747 };
1748
1749 uart4_sleep_pins_a: uart4-sleep-0 {
1750 pins {
1751 pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */
1752 <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */
1753 };
1754 };
1755
1756 uart4_pins_b: uart4-1 {
1757 pins1 {
1758 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
1759 bias-disable;
1760 drive-push-pull;
1761 slew-rate = <0>;
1762 };
1763 pins2 {
1764 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1765 bias-disable;
1766 };
1767 };
1768
1769 uart4_pins_c: uart4-2 {
1770 pins1 {
1771 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
1772 bias-disable;
1773 drive-push-pull;
1774 slew-rate = <0>;
1775 };
1776 pins2 {
1777 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
1778 bias-disable;
1779 };
1780 };
1781
1782 uart7_pins_a: uart7-0 {
1783 pins1 {
1784 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
1785 bias-disable;
1786 drive-push-pull;
1787 slew-rate = <0>;
1788 };
1789 pins2 {
1790 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */
1791 <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */
1792 <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */
1793 bias-disable;
1794 };
1795 };
1796
1797 uart7_pins_b: uart7-1 {
1798 pins1 {
1799 pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
1800 bias-disable;
1801 drive-push-pull;
1802 slew-rate = <0>;
1803 };
1804 pins2 {
1805 pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */
1806 bias-disable;
1807 };
1808 };
1809
1810 uart7_pins_c: uart7-2 {
1811 pins1 {
1812 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
1813 bias-disable;
1814 drive-push-pull;
1815 slew-rate = <0>;
1816 };
1817 pins2 {
1818 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
1819 bias-disable;
1820 };
1821 };
1822
1823 uart7_idle_pins_c: uart7-idle-2 {
1824 pins1 {
1825 pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */
1826 };
1827 pins2 {
1828 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
1829 bias-disable;
1830 };
1831 };
1832
1833 uart7_sleep_pins_c: uart7-sleep-2 {
1834 pins {
1835 pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */
1836 <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */
1837 };
1838 };
1839
1840 uart8_pins_a: uart8-0 {
1841 pins1 {
1842 pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
1843 bias-disable;
1844 drive-push-pull;
1845 slew-rate = <0>;
1846 };
1847 pins2 {
1848 pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */
1849 bias-disable;
1850 };
1851 };
1852
1853 uart8_rtscts_pins_a: uart8rtscts-0 {
1854 pins {
1855 pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */
1856 <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */
1857 bias-disable;
1858 };
1859 };
1860
1861 usart2_pins_a: usart2-0 {
1862 pins1 {
1863 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
1864 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
1865 bias-disable;
1866 drive-push-pull;
1867 slew-rate = <0>;
1868 };
1869 pins2 {
1870 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
1871 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
1872 bias-disable;
1873 };
1874 };
1875
1876 usart2_sleep_pins_a: usart2-sleep-0 {
1877 pins {
1878 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
1879 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
1880 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
1881 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
1882 };
1883 };
1884
1885 usart2_pins_b: usart2-1 {
1886 pins1 {
1887 pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
1888 <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
1889 bias-disable;
1890 drive-push-pull;
1891 slew-rate = <0>;
1892 };
1893 pins2 {
1894 pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */
1895 <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */
1896 bias-disable;
1897 };
1898 };
1899
1900 usart2_sleep_pins_b: usart2-sleep-1 {
1901 pins {
1902 pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */
1903 <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
1904 <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */
1905 <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
1906 };
1907 };
1908
1909 usart2_pins_c: usart2-2 {
1910 pins1 {
1911 pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
1912 <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
1913 bias-disable;
1914 drive-push-pull;
1915 slew-rate = <3>;
1916 };
1917 pins2 {
1918 pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
1919 <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */
1920 bias-disable;
1921 };
1922 };
1923
1924 usart2_idle_pins_c: usart2-idle-2 {
1925 pins1 {
1926 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
1927 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
1928 };
1929 pins2 {
1930 pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
1931 bias-disable;
1932 drive-push-pull;
1933 slew-rate = <3>;
1934 };
1935 pins3 {
1936 pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
1937 bias-disable;
1938 };
1939 };
1940
1941 usart2_sleep_pins_c: usart2-sleep-2 {
1942 pins {
1943 pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */
1944 <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
1945 <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */
1946 <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */
1947 };
1948 };
1949
1950 usart3_pins_a: usart3-0 {
1951 pins1 {
1952 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
1953 bias-disable;
1954 drive-push-pull;
1955 slew-rate = <0>;
1956 };
1957 pins2 {
1958 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
1959 bias-disable;
1960 };
1961 };
1962
1963 usart3_pins_b: usart3-1 {
1964 pins1 {
1965 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
1966 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
1967 bias-disable;
1968 drive-push-pull;
1969 slew-rate = <0>;
1970 };
1971 pins2 {
1972 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
1973 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
1974 bias-disable;
1975 };
1976 };
1977
1978 usart3_idle_pins_b: usart3-idle-1 {
1979 pins1 {
1980 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
1981 <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */
1982 };
1983 pins2 {
1984 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
1985 bias-disable;
1986 drive-push-pull;
1987 slew-rate = <0>;
1988 };
1989 pins3 {
1990 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
1991 bias-disable;
1992 };
1993 };
1994
1995 usart3_sleep_pins_b: usart3-sleep-1 {
1996 pins {
1997 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
1998 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
1999 <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */
2000 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
2001 };
2002 };
2003
2004 usart3_pins_c: usart3-2 {
2005 pins1 {
2006 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
2007 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
2008 bias-disable;
2009 drive-push-pull;
2010 slew-rate = <0>;
2011 };
2012 pins2 {
2013 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
2014 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
2015 bias-disable;
2016 };
2017 };
2018
2019 usart3_idle_pins_c: usart3-idle-2 {
2020 pins1 {
2021 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2022 <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */
2023 };
2024 pins2 {
2025 pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
2026 bias-disable;
2027 drive-push-pull;
2028 slew-rate = <0>;
2029 };
2030 pins3 {
2031 pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */
2032 bias-disable;
2033 };
2034 };
2035
2036 usart3_sleep_pins_c: usart3-sleep-2 {
2037 pins {
2038 pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */
2039 <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */
2040 <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */
2041 <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */
2042 };
2043 };
2044
2045 usbotg_hs_pins_a: usbotg-hs-0 {
2046 pins {
2047 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
2048 };
2049 };
2050
2051 usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
2052 pins {
2053 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
2054 <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */
2055 };
2056 };
2057};
2058
2059&pinctrl_z {
2060 i2c2_pins_b2: i2c2-0 {
2061 pins {
2062 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
2063 bias-disable;
2064 drive-open-drain;
2065 slew-rate = <0>;
2066 };
2067 };
2068
2069 i2c2_sleep_pins_b2: i2c2-sleep-0 {
2070 pins {
2071 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
2072 };
2073 };
2074
2075 i2c4_pins_a: i2c4-0 {
2076 pins {
2077 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
2078 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
2079 bias-disable;
2080 drive-open-drain;
2081 slew-rate = <0>;
2082 };
2083 };
2084
2085 i2c4_sleep_pins_a: i2c4-sleep-0 {
2086 pins {
2087 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
2088 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
2089 };
2090 };
2091
2092 i2c6_pins_a: i2c6-0 {
2093 pins {
2094 pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */
2095 <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */
2096 bias-disable;
2097 drive-open-drain;
2098 slew-rate = <0>;
2099 };
2100 };
2101
2102 i2c6_sleep_pins_a: i2c6-sleep-0 {
2103 pins {
2104 pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */
2105 <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */
2106 };
2107 };
2108
2109 spi1_pins_a: spi1-0 {
2110 pins1 {
2111 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
2112 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
2113 bias-disable;
2114 drive-push-pull;
2115 slew-rate = <1>;
2116 };
2117
2118 pins2 {
2119 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
2120 bias-disable;
2121 };
2122 };
2123};