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1/*
2 * Copyright (C) 2015 STMicroelectronics R&D Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <dt-bindings/clock/stih418-clks.h>
9/ {
10 /*
11 * Fixed 30MHz oscillator inputs to SoC
12 */
13 clk_sysin: clk-sysin {
14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <30000000>;
17 clock-output-names = "CLK_SYSIN";
18 };
19
20 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <0>;
24 };
25
26 clocks {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 ranges;
30
31 compatible = "st,stih418-clk", "simple-bus";
32
33 /*
34 * A9 PLL.
35 */
36 clockgen-a9@92b0000 {
37 compatible = "st,clkgen-c32";
38 reg = <0x92b0000 0xffff>;
39
40 clockgen_a9_pll: clockgen-a9-pll {
41 #clock-cells = <1>;
42 compatible = "st,stih418-clkgen-plla9";
43
44 clocks = <&clk_sysin>;
45
46 clock-output-names = "clockgen-a9-pll-odf";
47 };
48 };
49
50 /*
51 * ARM CPU related clocks.
52 */
53 clk_m_a9: clk-m-a9@92b0000 {
54 #clock-cells = <0>;
55 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
56 reg = <0x92b0000 0x10000>;
57
58 clocks = <&clockgen_a9_pll 0>,
59 <&clockgen_a9_pll 0>,
60 <&clk_s_c0_flexgen 13>,
61 <&clk_m_a9_ext2f_div2>;
62
63 /*
64 * ARM Peripheral clock for timers
65 */
66 arm_periph_clk: clk-m-a9-periphs {
67 #clock-cells = <0>;
68 compatible = "fixed-factor-clock";
69 clocks = <&clk_m_a9>;
70 clock-div = <2>;
71 clock-mult = <1>;
72 };
73 };
74
75 clockgen-a@90ff000 {
76 compatible = "st,clkgen-c32";
77 reg = <0x90ff000 0x1000>;
78
79 clk_s_a0_pll: clk-s-a0-pll {
80 #clock-cells = <1>;
81 compatible = "st,clkgen-pll0";
82
83 clocks = <&clk_sysin>;
84
85 clock-output-names = "clk-s-a0-pll-ofd-0";
86 };
87
88 clk_s_a0_flexgen: clk-s-a0-flexgen {
89 compatible = "st,flexgen";
90
91 #clock-cells = <1>;
92
93 clocks = <&clk_s_a0_pll 0>,
94 <&clk_sysin>;
95
96 clock-output-names = "clk-ic-lmi0",
97 "clk-ic-lmi1";
98 };
99 };
100
101 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
102 #clock-cells = <1>;
103 compatible = "st,quadfs-pll";
104 reg = <0x9103000 0x1000>;
105
106 clocks = <&clk_sysin>;
107
108 clock-output-names = "clk-s-c0-fs0-ch0",
109 "clk-s-c0-fs0-ch1",
110 "clk-s-c0-fs0-ch2",
111 "clk-s-c0-fs0-ch3";
112 };
113
114 clk_s_c0: clockgen-c@9103000 {
115 compatible = "st,clkgen-c32";
116 reg = <0x9103000 0x1000>;
117
118 clk_s_c0_pll0: clk-s-c0-pll0 {
119 #clock-cells = <1>;
120 compatible = "st,clkgen-pll0";
121
122 clocks = <&clk_sysin>;
123
124 clock-output-names = "clk-s-c0-pll0-odf-0";
125 };
126
127 clk_s_c0_pll1: clk-s-c0-pll1 {
128 #clock-cells = <1>;
129 compatible = "st,clkgen-pll1";
130
131 clocks = <&clk_sysin>;
132
133 clock-output-names = "clk-s-c0-pll1-odf-0";
134 };
135
136 clk_s_c0_flexgen: clk-s-c0-flexgen {
137 #clock-cells = <1>;
138 compatible = "st,flexgen";
139
140 clocks = <&clk_s_c0_pll0 0>,
141 <&clk_s_c0_pll1 0>,
142 <&clk_s_c0_quadfs 0>,
143 <&clk_s_c0_quadfs 1>,
144 <&clk_s_c0_quadfs 2>,
145 <&clk_s_c0_quadfs 3>,
146 <&clk_sysin>;
147
148 clock-output-names = "clk-icn-gpu",
149 "clk-fdma",
150 "clk-nand",
151 "clk-hva",
152 "clk-proc-stfe",
153 "clk-tp",
154 "clk-rx-icn-dmu",
155 "clk-rx-icn-hva",
156 "clk-icn-cpu",
157 "clk-tx-icn-dmu",
158 "clk-mmc-0",
159 "clk-mmc-1",
160 "clk-jpegdec",
161 "clk-icn-reg",
162 "clk-proc-bdisp-0",
163 "clk-proc-bdisp-1",
164 "clk-pp-dmu",
165 "clk-vid-dmu",
166 "clk-dss-lpc",
167 "clk-st231-aud-0",
168 "clk-st231-gp-1",
169 "clk-st231-dmu",
170 "clk-icn-lmi",
171 "clk-tx-icn-1",
172 "clk-icn-sbc",
173 "clk-stfe-frc2",
174 "clk-eth-phyref",
175 "clk-eth-ref-phyclk",
176 "clk-flash-promip",
177 "clk-main-disp",
178 "clk-aux-disp",
179 "clk-compo-dvp",
180 "clk-tx-icn-hades",
181 "clk-rx-icn-hades",
182 "clk-icn-reg-16",
183 "clk-pp-hevc",
184 "clk-clust-hevc",
185 "clk-hwpe-hevc",
186 "clk-fc-hevc",
187 "clk-proc-mixer",
188 "clk-proc-sc",
189 "clk-avsp-hevc";
190
191 /*
192 * ARM Peripheral clock for timers
193 */
194 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
195 #clock-cells = <0>;
196 compatible = "fixed-factor-clock";
197
198 clocks = <&clk_s_c0_flexgen 13>;
199
200 clock-output-names = "clk-m-a9-ext2f-div2";
201
202 clock-div = <2>;
203 clock-mult = <1>;
204 };
205 };
206 };
207
208 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
209 #clock-cells = <1>;
210 compatible = "st,quadfs";
211 reg = <0x9104000 0x1000>;
212
213 clocks = <&clk_sysin>;
214
215 clock-output-names = "clk-s-d0-fs0-ch0",
216 "clk-s-d0-fs0-ch1",
217 "clk-s-d0-fs0-ch2",
218 "clk-s-d0-fs0-ch3";
219 };
220
221 clockgen-d0@9104000 {
222 compatible = "st,clkgen-c32";
223 reg = <0x9104000 0x1000>;
224
225 clk_s_d0_flexgen: clk-s-d0-flexgen {
226 #clock-cells = <1>;
227 compatible = "st,flexgen-audio", "st,flexgen";
228
229 clocks = <&clk_s_d0_quadfs 0>,
230 <&clk_s_d0_quadfs 1>,
231 <&clk_s_d0_quadfs 2>,
232 <&clk_s_d0_quadfs 3>,
233 <&clk_sysin>;
234
235 clock-output-names = "clk-pcm-0",
236 "clk-pcm-1",
237 "clk-pcm-2",
238 "clk-spdiff",
239 "clk-pcmr10-master",
240 "clk-usb2-phy";
241 };
242 };
243
244 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
245 #clock-cells = <1>;
246 compatible = "st,quadfs";
247 reg = <0x9106000 0x1000>;
248
249 clocks = <&clk_sysin>;
250
251 clock-output-names = "clk-s-d2-fs0-ch0",
252 "clk-s-d2-fs0-ch1",
253 "clk-s-d2-fs0-ch2",
254 "clk-s-d2-fs0-ch3";
255 };
256
257 clockgen-d2@9106000 {
258 compatible = "st,clkgen-c32";
259 reg = <0x9106000 0x1000>;
260
261 clk_s_d2_flexgen: clk-s-d2-flexgen {
262 #clock-cells = <1>;
263 compatible = "st,flexgen-video", "st,flexgen";
264
265 clocks = <&clk_s_d2_quadfs 0>,
266 <&clk_s_d2_quadfs 1>,
267 <&clk_s_d2_quadfs 2>,
268 <&clk_s_d2_quadfs 3>,
269 <&clk_sysin>,
270 <&clk_sysin>,
271 <&clk_tmdsout_hdmi>;
272
273 clock-output-names = "clk-pix-main-disp",
274 "",
275 "",
276 "",
277 "",
278 "clk-tmds-hdmi-div2",
279 "clk-pix-aux-disp",
280 "clk-denc",
281 "clk-pix-hddac",
282 "clk-hddac",
283 "clk-sddac",
284 "clk-pix-dvo",
285 "clk-dvo",
286 "clk-pix-hdmi",
287 "clk-tmds-hdmi",
288 "clk-ref-hdmiphy",
289 "", "", "", "", "",
290 "", "", "", "", "",
291 "", "", "", "", "",
292 "", "", "", "", "",
293 "", "", "", "", "",
294 "", "", "", "", "",
295 "", "clk-vp9";
296 };
297 };
298
299 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
300 #clock-cells = <1>;
301 compatible = "st,quadfs";
302 reg = <0x9107000 0x1000>;
303
304 clocks = <&clk_sysin>;
305
306 clock-output-names = "clk-s-d3-fs0-ch0",
307 "clk-s-d3-fs0-ch1",
308 "clk-s-d3-fs0-ch2",
309 "clk-s-d3-fs0-ch3";
310 };
311
312 clockgen-d3@9107000 {
313 compatible = "st,clkgen-c32";
314 reg = <0x9107000 0x1000>;
315
316 clk_s_d3_flexgen: clk-s-d3-flexgen {
317 #clock-cells = <1>;
318 compatible = "st,flexgen";
319
320 clocks = <&clk_s_d3_quadfs 0>,
321 <&clk_s_d3_quadfs 1>,
322 <&clk_s_d3_quadfs 2>,
323 <&clk_s_d3_quadfs 3>,
324 <&clk_sysin>;
325
326 clock-output-names = "clk-stfe-frc1",
327 "clk-tsout-0",
328 "clk-tsout-1",
329 "clk-mchi",
330 "clk-vsens-compo",
331 "clk-frc1-remote",
332 "clk-lpc-0",
333 "clk-lpc-1";
334 };
335 };
336 };
337};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 STMicroelectronics R&D Limited
4 */
5#include <dt-bindings/clock/stih418-clks.h>
6/ {
7 /*
8 * Fixed 30MHz oscillator inputs to SoC
9 */
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
15 };
16
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <0>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 ranges;
27
28 compatible = "st,stih418-clk", "simple-bus";
29
30 /*
31 * A9 PLL.
32 */
33 clockgen-a9@92b0000 {
34 compatible = "st,clkgen-c32";
35 reg = <0x92b0000 0xffff>;
36
37 clockgen_a9_pll: clockgen-a9-pll {
38 #clock-cells = <1>;
39 compatible = "st,stih418-clkgen-plla9";
40
41 clocks = <&clk_sysin>;
42
43 clock-output-names = "clockgen-a9-pll-odf";
44 };
45 };
46
47 /*
48 * ARM CPU related clocks.
49 */
50 clk_m_a9: clk-m-a9@92b0000 {
51 #clock-cells = <0>;
52 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
53 reg = <0x92b0000 0x10000>;
54
55 clocks = <&clockgen_a9_pll 0>,
56 <&clockgen_a9_pll 0>,
57 <&clk_s_c0_flexgen 13>,
58 <&clk_m_a9_ext2f_div2>;
59
60 /*
61 * ARM Peripheral clock for timers
62 */
63 arm_periph_clk: clk-m-a9-periphs {
64 #clock-cells = <0>;
65 compatible = "fixed-factor-clock";
66 clocks = <&clk_m_a9>;
67 clock-div = <2>;
68 clock-mult = <1>;
69 };
70 };
71
72 clockgen-a@90ff000 {
73 compatible = "st,clkgen-c32";
74 reg = <0x90ff000 0x1000>;
75
76 clk_s_a0_pll: clk-s-a0-pll {
77 #clock-cells = <1>;
78 compatible = "st,clkgen-pll0";
79
80 clocks = <&clk_sysin>;
81
82 clock-output-names = "clk-s-a0-pll-ofd-0";
83 };
84
85 clk_s_a0_flexgen: clk-s-a0-flexgen {
86 compatible = "st,flexgen";
87
88 #clock-cells = <1>;
89
90 clocks = <&clk_s_a0_pll 0>,
91 <&clk_sysin>;
92
93 clock-output-names = "clk-ic-lmi0",
94 "clk-ic-lmi1";
95 };
96 };
97
98 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
99 #clock-cells = <1>;
100 compatible = "st,quadfs-pll";
101 reg = <0x9103000 0x1000>;
102
103 clocks = <&clk_sysin>;
104
105 clock-output-names = "clk-s-c0-fs0-ch0",
106 "clk-s-c0-fs0-ch1",
107 "clk-s-c0-fs0-ch2",
108 "clk-s-c0-fs0-ch3";
109 };
110
111 clk_s_c0: clockgen-c@9103000 {
112 compatible = "st,clkgen-c32";
113 reg = <0x9103000 0x1000>;
114
115 clk_s_c0_pll0: clk-s-c0-pll0 {
116 #clock-cells = <1>;
117 compatible = "st,clkgen-pll0";
118
119 clocks = <&clk_sysin>;
120
121 clock-output-names = "clk-s-c0-pll0-odf-0";
122 };
123
124 clk_s_c0_pll1: clk-s-c0-pll1 {
125 #clock-cells = <1>;
126 compatible = "st,clkgen-pll1";
127
128 clocks = <&clk_sysin>;
129
130 clock-output-names = "clk-s-c0-pll1-odf-0";
131 };
132
133 clk_s_c0_flexgen: clk-s-c0-flexgen {
134 #clock-cells = <1>;
135 compatible = "st,flexgen";
136
137 clocks = <&clk_s_c0_pll0 0>,
138 <&clk_s_c0_pll1 0>,
139 <&clk_s_c0_quadfs 0>,
140 <&clk_s_c0_quadfs 1>,
141 <&clk_s_c0_quadfs 2>,
142 <&clk_s_c0_quadfs 3>,
143 <&clk_sysin>;
144
145 clock-output-names = "clk-icn-gpu",
146 "clk-fdma",
147 "clk-nand",
148 "clk-hva",
149 "clk-proc-stfe",
150 "clk-tp",
151 "clk-rx-icn-dmu",
152 "clk-rx-icn-hva",
153 "clk-icn-cpu",
154 "clk-tx-icn-dmu",
155 "clk-mmc-0",
156 "clk-mmc-1",
157 "clk-jpegdec",
158 "clk-icn-reg",
159 "clk-proc-bdisp-0",
160 "clk-proc-bdisp-1",
161 "clk-pp-dmu",
162 "clk-vid-dmu",
163 "clk-dss-lpc",
164 "clk-st231-aud-0",
165 "clk-st231-gp-1",
166 "clk-st231-dmu",
167 "clk-icn-lmi",
168 "clk-tx-icn-1",
169 "clk-icn-sbc",
170 "clk-stfe-frc2",
171 "clk-eth-phyref",
172 "clk-eth-ref-phyclk",
173 "clk-flash-promip",
174 "clk-main-disp",
175 "clk-aux-disp",
176 "clk-compo-dvp",
177 "clk-tx-icn-hades",
178 "clk-rx-icn-hades",
179 "clk-icn-reg-16",
180 "clk-pp-hevc",
181 "clk-clust-hevc",
182 "clk-hwpe-hevc",
183 "clk-fc-hevc",
184 "clk-proc-mixer",
185 "clk-proc-sc",
186 "clk-avsp-hevc";
187
188 /*
189 * ARM Peripheral clock for timers
190 */
191 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
192 #clock-cells = <0>;
193 compatible = "fixed-factor-clock";
194
195 clocks = <&clk_s_c0_flexgen 13>;
196
197 clock-output-names = "clk-m-a9-ext2f-div2";
198
199 clock-div = <2>;
200 clock-mult = <1>;
201 };
202 };
203 };
204
205 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
206 #clock-cells = <1>;
207 compatible = "st,quadfs";
208 reg = <0x9104000 0x1000>;
209
210 clocks = <&clk_sysin>;
211
212 clock-output-names = "clk-s-d0-fs0-ch0",
213 "clk-s-d0-fs0-ch1",
214 "clk-s-d0-fs0-ch2",
215 "clk-s-d0-fs0-ch3";
216 };
217
218 clockgen-d0@9104000 {
219 compatible = "st,clkgen-c32";
220 reg = <0x9104000 0x1000>;
221
222 clk_s_d0_flexgen: clk-s-d0-flexgen {
223 #clock-cells = <1>;
224 compatible = "st,flexgen-audio", "st,flexgen";
225
226 clocks = <&clk_s_d0_quadfs 0>,
227 <&clk_s_d0_quadfs 1>,
228 <&clk_s_d0_quadfs 2>,
229 <&clk_s_d0_quadfs 3>,
230 <&clk_sysin>;
231
232 clock-output-names = "clk-pcm-0",
233 "clk-pcm-1",
234 "clk-pcm-2",
235 "clk-spdiff",
236 "clk-pcmr10-master",
237 "clk-usb2-phy";
238 };
239 };
240
241 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
242 #clock-cells = <1>;
243 compatible = "st,quadfs";
244 reg = <0x9106000 0x1000>;
245
246 clocks = <&clk_sysin>;
247
248 clock-output-names = "clk-s-d2-fs0-ch0",
249 "clk-s-d2-fs0-ch1",
250 "clk-s-d2-fs0-ch2",
251 "clk-s-d2-fs0-ch3";
252 };
253
254 clockgen-d2@9106000 {
255 compatible = "st,clkgen-c32";
256 reg = <0x9106000 0x1000>;
257
258 clk_s_d2_flexgen: clk-s-d2-flexgen {
259 #clock-cells = <1>;
260 compatible = "st,flexgen-video", "st,flexgen";
261
262 clocks = <&clk_s_d2_quadfs 0>,
263 <&clk_s_d2_quadfs 1>,
264 <&clk_s_d2_quadfs 2>,
265 <&clk_s_d2_quadfs 3>,
266 <&clk_sysin>,
267 <&clk_sysin>,
268 <&clk_tmdsout_hdmi>;
269
270 clock-output-names = "clk-pix-main-disp",
271 "",
272 "",
273 "",
274 "",
275 "clk-tmds-hdmi-div2",
276 "clk-pix-aux-disp",
277 "clk-denc",
278 "clk-pix-hddac",
279 "clk-hddac",
280 "clk-sddac",
281 "clk-pix-dvo",
282 "clk-dvo",
283 "clk-pix-hdmi",
284 "clk-tmds-hdmi",
285 "clk-ref-hdmiphy",
286 "", "", "", "", "",
287 "", "", "", "", "",
288 "", "", "", "", "",
289 "", "", "", "", "",
290 "", "", "", "", "",
291 "", "", "", "", "",
292 "", "clk-vp9";
293 };
294 };
295
296 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
297 #clock-cells = <1>;
298 compatible = "st,quadfs";
299 reg = <0x9107000 0x1000>;
300
301 clocks = <&clk_sysin>;
302
303 clock-output-names = "clk-s-d3-fs0-ch0",
304 "clk-s-d3-fs0-ch1",
305 "clk-s-d3-fs0-ch2",
306 "clk-s-d3-fs0-ch3";
307 };
308
309 clockgen-d3@9107000 {
310 compatible = "st,clkgen-c32";
311 reg = <0x9107000 0x1000>;
312
313 clk_s_d3_flexgen: clk-s-d3-flexgen {
314 #clock-cells = <1>;
315 compatible = "st,flexgen";
316
317 clocks = <&clk_s_d3_quadfs 0>,
318 <&clk_s_d3_quadfs 1>,
319 <&clk_s_d3_quadfs 2>,
320 <&clk_s_d3_quadfs 3>,
321 <&clk_sysin>;
322
323 clock-output-names = "clk-stfe-frc1",
324 "clk-tsout-0",
325 "clk-tsout-1",
326 "clk-mchi",
327 "clk-vsens-compo",
328 "clk-frc1-remote",
329 "clk-lpc-0",
330 "clk-lpc-1";
331 };
332 };
333 };
334};