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1/*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41#include <dt-bindings/gpio/gpio.h>
42#include <dt-bindings/interrupt-controller/irq.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/pinctrl/rockchip.h>
45#include <dt-bindings/clock/rk3288-cru.h>
46#include <dt-bindings/power/rk3288-power.h>
47#include <dt-bindings/thermal/thermal.h>
48#include <dt-bindings/power/rk3288-power.h>
49#include <dt-bindings/soc/rockchip,boot-mode.h>
50
51/ {
52 #address-cells = <2>;
53 #size-cells = <2>;
54
55 compatible = "rockchip,rk3288";
56
57 interrupt-parent = <&gic>;
58
59 aliases {
60 ethernet0 = &gmac;
61 i2c0 = &i2c0;
62 i2c1 = &i2c1;
63 i2c2 = &i2c2;
64 i2c3 = &i2c3;
65 i2c4 = &i2c4;
66 i2c5 = &i2c5;
67 mshc0 = &emmc;
68 mshc1 = &sdmmc;
69 mshc2 = &sdio0;
70 mshc3 = &sdio1;
71 serial0 = &uart0;
72 serial1 = &uart1;
73 serial2 = &uart2;
74 serial3 = &uart3;
75 serial4 = &uart4;
76 spi0 = &spi0;
77 spi1 = &spi1;
78 spi2 = &spi2;
79 };
80
81 arm-pmu {
82 compatible = "arm,cortex-a12-pmu";
83 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
87 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88 };
89
90 cpus {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 enable-method = "rockchip,rk3066-smp";
94 rockchip,pmu = <&pmu>;
95
96 cpu0: cpu@500 {
97 device_type = "cpu";
98 compatible = "arm,cortex-a12";
99 reg = <0x500>;
100 resets = <&cru SRST_CORE0>;
101 operating-points = <
102 /* KHz uV */
103 1608000 1350000
104 1512000 1300000
105 1416000 1200000
106 1200000 1100000
107 1008000 1050000
108 816000 1000000
109 696000 950000
110 600000 900000
111 408000 900000
112 312000 900000
113 216000 900000
114 126000 900000
115 >;
116 #cooling-cells = <2>; /* min followed by max */
117 clock-latency = <40000>;
118 clocks = <&cru ARMCLK>;
119 };
120 cpu1: cpu@501 {
121 device_type = "cpu";
122 compatible = "arm,cortex-a12";
123 reg = <0x501>;
124 resets = <&cru SRST_CORE1>;
125 };
126 cpu2: cpu@502 {
127 device_type = "cpu";
128 compatible = "arm,cortex-a12";
129 reg = <0x502>;
130 resets = <&cru SRST_CORE2>;
131 };
132 cpu3: cpu@503 {
133 device_type = "cpu";
134 compatible = "arm,cortex-a12";
135 reg = <0x503>;
136 resets = <&cru SRST_CORE3>;
137 };
138 };
139
140 amba {
141 compatible = "simple-bus";
142 #address-cells = <2>;
143 #size-cells = <2>;
144 ranges;
145
146 dmac_peri: dma-controller@ff250000 {
147 compatible = "arm,pl330", "arm,primecell";
148 reg = <0x0 0xff250000 0x0 0x4000>;
149 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
151 #dma-cells = <1>;
152 arm,pl330-broken-no-flushp;
153 clocks = <&cru ACLK_DMAC2>;
154 clock-names = "apb_pclk";
155 };
156
157 dmac_bus_ns: dma-controller@ff600000 {
158 compatible = "arm,pl330", "arm,primecell";
159 reg = <0x0 0xff600000 0x0 0x4000>;
160 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
162 #dma-cells = <1>;
163 arm,pl330-broken-no-flushp;
164 clocks = <&cru ACLK_DMAC1>;
165 clock-names = "apb_pclk";
166 status = "disabled";
167 };
168
169 dmac_bus_s: dma-controller@ffb20000 {
170 compatible = "arm,pl330", "arm,primecell";
171 reg = <0x0 0xffb20000 0x0 0x4000>;
172 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
174 #dma-cells = <1>;
175 arm,pl330-broken-no-flushp;
176 clocks = <&cru ACLK_DMAC1>;
177 clock-names = "apb_pclk";
178 };
179 };
180
181 reserved-memory {
182 #address-cells = <2>;
183 #size-cells = <2>;
184 ranges;
185
186 /*
187 * The rk3288 cannot use the memory area above 0xfe000000
188 * for dma operations for some reason. While there is
189 * probably a better solution available somewhere, we
190 * haven't found it yet and while devices with 2GB of ram
191 * are not affected, this issue prevents 4GB from booting.
192 * So to make these devices at least bootable, block
193 * this area for the time being until the real solution
194 * is found.
195 */
196 dma-unusable@fe000000 {
197 reg = <0x0 0xfe000000 0x0 0x1000000>;
198 };
199 };
200
201 xin24m: oscillator {
202 compatible = "fixed-clock";
203 clock-frequency = <24000000>;
204 clock-output-names = "xin24m";
205 #clock-cells = <0>;
206 };
207
208 timer {
209 compatible = "arm,armv7-timer";
210 arm,cpu-registers-not-fw-configured;
211 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
213 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
214 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
215 clock-frequency = <24000000>;
216 };
217
218 timer: timer@ff810000 {
219 compatible = "rockchip,rk3288-timer";
220 reg = <0x0 0xff810000 0x0 0x20>;
221 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&xin24m>, <&cru PCLK_TIMER>;
223 clock-names = "timer", "pclk";
224 };
225
226 display-subsystem {
227 compatible = "rockchip,display-subsystem";
228 ports = <&vopl_out>, <&vopb_out>;
229 };
230
231 sdmmc: dwmmc@ff0c0000 {
232 compatible = "rockchip,rk3288-dw-mshc";
233 max-frequency = <150000000>;
234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
235 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
237 fifo-depth = <0x100>;
238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
239 reg = <0x0 0xff0c0000 0x0 0x4000>;
240 resets = <&cru SRST_MMC0>;
241 reset-names = "reset";
242 status = "disabled";
243 };
244
245 sdio0: dwmmc@ff0d0000 {
246 compatible = "rockchip,rk3288-dw-mshc";
247 max-frequency = <150000000>;
248 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
249 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
250 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
251 fifo-depth = <0x100>;
252 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
253 reg = <0x0 0xff0d0000 0x0 0x4000>;
254 resets = <&cru SRST_SDIO0>;
255 reset-names = "reset";
256 status = "disabled";
257 };
258
259 sdio1: dwmmc@ff0e0000 {
260 compatible = "rockchip,rk3288-dw-mshc";
261 max-frequency = <150000000>;
262 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
263 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
265 fifo-depth = <0x100>;
266 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
267 reg = <0x0 0xff0e0000 0x0 0x4000>;
268 resets = <&cru SRST_SDIO1>;
269 reset-names = "reset";
270 status = "disabled";
271 };
272
273 emmc: dwmmc@ff0f0000 {
274 compatible = "rockchip,rk3288-dw-mshc";
275 max-frequency = <150000000>;
276 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
277 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
278 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
279 fifo-depth = <0x100>;
280 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
281 reg = <0x0 0xff0f0000 0x0 0x4000>;
282 resets = <&cru SRST_EMMC>;
283 reset-names = "reset";
284 status = "disabled";
285 };
286
287 saradc: saradc@ff100000 {
288 compatible = "rockchip,saradc";
289 reg = <0x0 0xff100000 0x0 0x100>;
290 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
291 #io-channel-cells = <1>;
292 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
293 clock-names = "saradc", "apb_pclk";
294 resets = <&cru SRST_SARADC>;
295 reset-names = "saradc-apb";
296 status = "disabled";
297 };
298
299 spi0: spi@ff110000 {
300 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
301 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
302 clock-names = "spiclk", "apb_pclk";
303 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
304 dma-names = "tx", "rx";
305 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
308 reg = <0x0 0xff110000 0x0 0x1000>;
309 #address-cells = <1>;
310 #size-cells = <0>;
311 status = "disabled";
312 };
313
314 spi1: spi@ff120000 {
315 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
316 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
317 clock-names = "spiclk", "apb_pclk";
318 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
319 dma-names = "tx", "rx";
320 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
323 reg = <0x0 0xff120000 0x0 0x1000>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 status = "disabled";
327 };
328
329 spi2: spi@ff130000 {
330 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
331 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
332 clock-names = "spiclk", "apb_pclk";
333 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
334 dma-names = "tx", "rx";
335 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
338 reg = <0x0 0xff130000 0x0 0x1000>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 status = "disabled";
342 };
343
344 i2c1: i2c@ff140000 {
345 compatible = "rockchip,rk3288-i2c";
346 reg = <0x0 0xff140000 0x0 0x1000>;
347 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 clock-names = "i2c";
351 clocks = <&cru PCLK_I2C1>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2c1_xfer>;
354 status = "disabled";
355 };
356
357 i2c3: i2c@ff150000 {
358 compatible = "rockchip,rk3288-i2c";
359 reg = <0x0 0xff150000 0x0 0x1000>;
360 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363 clock-names = "i2c";
364 clocks = <&cru PCLK_I2C3>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c3_xfer>;
367 status = "disabled";
368 };
369
370 i2c4: i2c@ff160000 {
371 compatible = "rockchip,rk3288-i2c";
372 reg = <0x0 0xff160000 0x0 0x1000>;
373 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
374 #address-cells = <1>;
375 #size-cells = <0>;
376 clock-names = "i2c";
377 clocks = <&cru PCLK_I2C4>;
378 pinctrl-names = "default";
379 pinctrl-0 = <&i2c4_xfer>;
380 status = "disabled";
381 };
382
383 i2c5: i2c@ff170000 {
384 compatible = "rockchip,rk3288-i2c";
385 reg = <0x0 0xff170000 0x0 0x1000>;
386 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
387 #address-cells = <1>;
388 #size-cells = <0>;
389 clock-names = "i2c";
390 clocks = <&cru PCLK_I2C5>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&i2c5_xfer>;
393 status = "disabled";
394 };
395
396 uart0: serial@ff180000 {
397 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
398 reg = <0x0 0xff180000 0x0 0x100>;
399 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
400 reg-shift = <2>;
401 reg-io-width = <4>;
402 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
403 clock-names = "baudclk", "apb_pclk";
404 pinctrl-names = "default";
405 pinctrl-0 = <&uart0_xfer>;
406 status = "disabled";
407 };
408
409 uart1: serial@ff190000 {
410 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
411 reg = <0x0 0xff190000 0x0 0x100>;
412 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
413 reg-shift = <2>;
414 reg-io-width = <4>;
415 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
416 clock-names = "baudclk", "apb_pclk";
417 pinctrl-names = "default";
418 pinctrl-0 = <&uart1_xfer>;
419 status = "disabled";
420 };
421
422 uart2: serial@ff690000 {
423 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
424 reg = <0x0 0xff690000 0x0 0x100>;
425 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
426 reg-shift = <2>;
427 reg-io-width = <4>;
428 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
429 clock-names = "baudclk", "apb_pclk";
430 pinctrl-names = "default";
431 pinctrl-0 = <&uart2_xfer>;
432 status = "disabled";
433 };
434
435 uart3: serial@ff1b0000 {
436 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
437 reg = <0x0 0xff1b0000 0x0 0x100>;
438 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
439 reg-shift = <2>;
440 reg-io-width = <4>;
441 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
442 clock-names = "baudclk", "apb_pclk";
443 pinctrl-names = "default";
444 pinctrl-0 = <&uart3_xfer>;
445 status = "disabled";
446 };
447
448 uart4: serial@ff1c0000 {
449 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
450 reg = <0x0 0xff1c0000 0x0 0x100>;
451 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
452 reg-shift = <2>;
453 reg-io-width = <4>;
454 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
455 clock-names = "baudclk", "apb_pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&uart4_xfer>;
458 status = "disabled";
459 };
460
461 thermal-zones {
462 reserve_thermal: reserve_thermal {
463 polling-delay-passive = <1000>; /* milliseconds */
464 polling-delay = <5000>; /* milliseconds */
465
466 thermal-sensors = <&tsadc 0>;
467 };
468
469 cpu_thermal: cpu_thermal {
470 polling-delay-passive = <100>; /* milliseconds */
471 polling-delay = <5000>; /* milliseconds */
472
473 thermal-sensors = <&tsadc 1>;
474
475 trips {
476 cpu_alert0: cpu_alert0 {
477 temperature = <70000>; /* millicelsius */
478 hysteresis = <2000>; /* millicelsius */
479 type = "passive";
480 };
481 cpu_alert1: cpu_alert1 {
482 temperature = <75000>; /* millicelsius */
483 hysteresis = <2000>; /* millicelsius */
484 type = "passive";
485 };
486 cpu_crit: cpu_crit {
487 temperature = <90000>; /* millicelsius */
488 hysteresis = <2000>; /* millicelsius */
489 type = "critical";
490 };
491 };
492
493 cooling-maps {
494 map0 {
495 trip = <&cpu_alert0>;
496 cooling-device =
497 <&cpu0 THERMAL_NO_LIMIT 6>;
498 };
499 map1 {
500 trip = <&cpu_alert1>;
501 cooling-device =
502 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
503 };
504 };
505 };
506
507 gpu_thermal: gpu_thermal {
508 polling-delay-passive = <100>; /* milliseconds */
509 polling-delay = <5000>; /* milliseconds */
510
511 thermal-sensors = <&tsadc 2>;
512
513 trips {
514 gpu_alert0: gpu_alert0 {
515 temperature = <70000>; /* millicelsius */
516 hysteresis = <2000>; /* millicelsius */
517 type = "passive";
518 };
519 gpu_crit: gpu_crit {
520 temperature = <90000>; /* millicelsius */
521 hysteresis = <2000>; /* millicelsius */
522 type = "critical";
523 };
524 };
525
526 cooling-maps {
527 map0 {
528 trip = <&gpu_alert0>;
529 cooling-device =
530 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
531 };
532 };
533 };
534 };
535
536 tsadc: tsadc@ff280000 {
537 compatible = "rockchip,rk3288-tsadc";
538 reg = <0x0 0xff280000 0x0 0x100>;
539 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
541 clock-names = "tsadc", "apb_pclk";
542 resets = <&cru SRST_TSADC>;
543 reset-names = "tsadc-apb";
544 pinctrl-names = "init", "default", "sleep";
545 pinctrl-0 = <&otp_gpio>;
546 pinctrl-1 = <&otp_out>;
547 pinctrl-2 = <&otp_gpio>;
548 #thermal-sensor-cells = <1>;
549 rockchip,hw-tshut-temp = <95000>;
550 status = "disabled";
551 };
552
553 gmac: ethernet@ff290000 {
554 compatible = "rockchip,rk3288-gmac";
555 reg = <0x0 0xff290000 0x0 0x10000>;
556 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
558 interrupt-names = "macirq", "eth_wake_irq";
559 rockchip,grf = <&grf>;
560 clocks = <&cru SCLK_MAC>,
561 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
562 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
563 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
564 clock-names = "stmmaceth",
565 "mac_clk_rx", "mac_clk_tx",
566 "clk_mac_ref", "clk_mac_refout",
567 "aclk_mac", "pclk_mac";
568 resets = <&cru SRST_MAC>;
569 reset-names = "stmmaceth";
570 status = "disabled";
571 };
572
573 usb_host0_ehci: usb@ff500000 {
574 compatible = "generic-ehci";
575 reg = <0x0 0xff500000 0x0 0x100>;
576 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&cru HCLK_USBHOST0>;
578 clock-names = "usbhost";
579 phys = <&usbphy1>;
580 phy-names = "usb";
581 status = "disabled";
582 };
583
584 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
585
586 usb_host1: usb@ff540000 {
587 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
588 "snps,dwc2";
589 reg = <0x0 0xff540000 0x0 0x40000>;
590 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&cru HCLK_USBHOST1>;
592 clock-names = "otg";
593 dr_mode = "host";
594 phys = <&usbphy2>;
595 phy-names = "usb2-phy";
596 status = "disabled";
597 };
598
599 usb_otg: usb@ff580000 {
600 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
601 "snps,dwc2";
602 reg = <0x0 0xff580000 0x0 0x40000>;
603 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cru HCLK_OTG0>;
605 clock-names = "otg";
606 dr_mode = "otg";
607 g-np-tx-fifo-size = <16>;
608 g-rx-fifo-size = <275>;
609 g-tx-fifo-size = <256 128 128 64 64 32>;
610 phys = <&usbphy0>;
611 phy-names = "usb2-phy";
612 status = "disabled";
613 };
614
615 usb_hsic: usb@ff5c0000 {
616 compatible = "generic-ehci";
617 reg = <0x0 0xff5c0000 0x0 0x100>;
618 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cru HCLK_HSIC>;
620 clock-names = "usbhost";
621 status = "disabled";
622 };
623
624 i2c0: i2c@ff650000 {
625 compatible = "rockchip,rk3288-i2c";
626 reg = <0x0 0xff650000 0x0 0x1000>;
627 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
628 #address-cells = <1>;
629 #size-cells = <0>;
630 clock-names = "i2c";
631 clocks = <&cru PCLK_I2C0>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&i2c0_xfer>;
634 status = "disabled";
635 };
636
637 i2c2: i2c@ff660000 {
638 compatible = "rockchip,rk3288-i2c";
639 reg = <0x0 0xff660000 0x0 0x1000>;
640 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
641 #address-cells = <1>;
642 #size-cells = <0>;
643 clock-names = "i2c";
644 clocks = <&cru PCLK_I2C2>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&i2c2_xfer>;
647 status = "disabled";
648 };
649
650 pwm0: pwm@ff680000 {
651 compatible = "rockchip,rk3288-pwm";
652 reg = <0x0 0xff680000 0x0 0x10>;
653 #pwm-cells = <3>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&pwm0_pin>;
656 clocks = <&cru PCLK_PWM>;
657 clock-names = "pwm";
658 status = "disabled";
659 };
660
661 pwm1: pwm@ff680010 {
662 compatible = "rockchip,rk3288-pwm";
663 reg = <0x0 0xff680010 0x0 0x10>;
664 #pwm-cells = <3>;
665 pinctrl-names = "default";
666 pinctrl-0 = <&pwm1_pin>;
667 clocks = <&cru PCLK_PWM>;
668 clock-names = "pwm";
669 status = "disabled";
670 };
671
672 pwm2: pwm@ff680020 {
673 compatible = "rockchip,rk3288-pwm";
674 reg = <0x0 0xff680020 0x0 0x10>;
675 #pwm-cells = <3>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&pwm2_pin>;
678 clocks = <&cru PCLK_PWM>;
679 clock-names = "pwm";
680 status = "disabled";
681 };
682
683 pwm3: pwm@ff680030 {
684 compatible = "rockchip,rk3288-pwm";
685 reg = <0x0 0xff680030 0x0 0x10>;
686 #pwm-cells = <2>;
687 pinctrl-names = "default";
688 pinctrl-0 = <&pwm3_pin>;
689 clocks = <&cru PCLK_PWM>;
690 clock-names = "pwm";
691 status = "disabled";
692 };
693
694 bus_intmem@ff700000 {
695 compatible = "mmio-sram";
696 reg = <0x0 0xff700000 0x0 0x18000>;
697 #address-cells = <1>;
698 #size-cells = <1>;
699 ranges = <0 0x0 0xff700000 0x18000>;
700 smp-sram@0 {
701 compatible = "rockchip,rk3066-smp-sram";
702 reg = <0x00 0x10>;
703 };
704 };
705
706 sram@ff720000 {
707 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
708 reg = <0x0 0xff720000 0x0 0x1000>;
709 };
710
711 pmu: power-management@ff730000 {
712 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
713 reg = <0x0 0xff730000 0x0 0x100>;
714
715 power: power-controller {
716 compatible = "rockchip,rk3288-power-controller";
717 #power-domain-cells = <1>;
718 #address-cells = <1>;
719 #size-cells = <0>;
720
721 assigned-clocks = <&cru SCLK_EDP_24M>;
722 assigned-clock-parents = <&xin24m>;
723
724 /*
725 * Note: Although SCLK_* are the working clocks
726 * of device without including on the NOC, needed for
727 * synchronous reset.
728 *
729 * The clocks on the which NOC:
730 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
731 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
732 * ACLK_RGA is on ACLK_RGA_NIU.
733 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
734 *
735 * Which clock are device clocks:
736 * clocks devices
737 * *_IEP IEP:Image Enhancement Processor
738 * *_ISP ISP:Image Signal Processing
739 * *_VIP VIP:Video Input Processor
740 * *_VOP* VOP:Visual Output Processor
741 * *_RGA RGA
742 * *_EDP* EDP
743 * *_LVDS_* LVDS
744 * *_HDMI HDMI
745 * *_MIPI_* MIPI
746 */
747 pd_vio@RK3288_PD_VIO {
748 reg = <RK3288_PD_VIO>;
749 clocks = <&cru ACLK_IEP>,
750 <&cru ACLK_ISP>,
751 <&cru ACLK_RGA>,
752 <&cru ACLK_VIP>,
753 <&cru ACLK_VOP0>,
754 <&cru ACLK_VOP1>,
755 <&cru DCLK_VOP0>,
756 <&cru DCLK_VOP1>,
757 <&cru HCLK_IEP>,
758 <&cru HCLK_ISP>,
759 <&cru HCLK_RGA>,
760 <&cru HCLK_VIP>,
761 <&cru HCLK_VOP0>,
762 <&cru HCLK_VOP1>,
763 <&cru PCLK_EDP_CTRL>,
764 <&cru PCLK_HDMI_CTRL>,
765 <&cru PCLK_LVDS_PHY>,
766 <&cru PCLK_MIPI_CSI>,
767 <&cru PCLK_MIPI_DSI0>,
768 <&cru PCLK_MIPI_DSI1>,
769 <&cru SCLK_EDP_24M>,
770 <&cru SCLK_EDP>,
771 <&cru SCLK_ISP_JPE>,
772 <&cru SCLK_ISP>,
773 <&cru SCLK_RGA>;
774 pm_qos = <&qos_vio0_iep>,
775 <&qos_vio1_vop>,
776 <&qos_vio1_isp_w0>,
777 <&qos_vio1_isp_w1>,
778 <&qos_vio0_vop>,
779 <&qos_vio0_vip>,
780 <&qos_vio2_rga_r>,
781 <&qos_vio2_rga_w>,
782 <&qos_vio1_isp_r>;
783 };
784
785 /*
786 * Note: The following 3 are HEVC(H.265) clocks,
787 * and on the ACLK_HEVC_NIU (NOC).
788 */
789 pd_hevc@RK3288_PD_HEVC {
790 reg = <RK3288_PD_HEVC>;
791 clocks = <&cru ACLK_HEVC>,
792 <&cru SCLK_HEVC_CABAC>,
793 <&cru SCLK_HEVC_CORE>;
794 pm_qos = <&qos_hevc_r>,
795 <&qos_hevc_w>;
796 };
797
798 /*
799 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
800 * (video endecoder & decoder) clocks that on the
801 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
802 */
803 pd_video@RK3288_PD_VIDEO {
804 reg = <RK3288_PD_VIDEO>;
805 clocks = <&cru ACLK_VCODEC>,
806 <&cru HCLK_VCODEC>;
807 pm_qos = <&qos_video>;
808 };
809
810 /*
811 * Note: ACLK_GPU is the GPU clock,
812 * and on the ACLK_GPU_NIU (NOC).
813 */
814 pd_gpu@RK3288_PD_GPU {
815 reg = <RK3288_PD_GPU>;
816 clocks = <&cru ACLK_GPU>;
817 pm_qos = <&qos_gpu_r>,
818 <&qos_gpu_w>;
819 };
820 };
821
822 reboot-mode {
823 compatible = "syscon-reboot-mode";
824 offset = <0x94>;
825 mode-normal = <BOOT_NORMAL>;
826 mode-recovery = <BOOT_RECOVERY>;
827 mode-bootloader = <BOOT_FASTBOOT>;
828 mode-loader = <BOOT_BL_DOWNLOAD>;
829 };
830 };
831
832 sgrf: syscon@ff740000 {
833 compatible = "rockchip,rk3288-sgrf", "syscon";
834 reg = <0x0 0xff740000 0x0 0x1000>;
835 };
836
837 cru: clock-controller@ff760000 {
838 compatible = "rockchip,rk3288-cru";
839 reg = <0x0 0xff760000 0x0 0x1000>;
840 rockchip,grf = <&grf>;
841 #clock-cells = <1>;
842 #reset-cells = <1>;
843 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
844 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
845 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
846 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
847 <&cru PCLK_PERI>;
848 assigned-clock-rates = <594000000>, <400000000>,
849 <500000000>, <300000000>,
850 <150000000>, <75000000>,
851 <300000000>, <150000000>,
852 <75000000>;
853 };
854
855 grf: syscon@ff770000 {
856 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
857 reg = <0x0 0xff770000 0x0 0x1000>;
858
859 edp_phy: edp-phy {
860 compatible = "rockchip,rk3288-dp-phy";
861 clocks = <&cru SCLK_EDP_24M>;
862 clock-names = "24m";
863 #phy-cells = <0>;
864 status = "disabled";
865 };
866
867 io_domains: io-domains {
868 compatible = "rockchip,rk3288-io-voltage-domain";
869 status = "disabled";
870 };
871
872 usbphy: usbphy {
873 compatible = "rockchip,rk3288-usb-phy";
874 #address-cells = <1>;
875 #size-cells = <0>;
876 status = "disabled";
877
878 usbphy0: usb-phy@320 {
879 #phy-cells = <0>;
880 reg = <0x320>;
881 clocks = <&cru SCLK_OTGPHY0>;
882 clock-names = "phyclk";
883 #clock-cells = <0>;
884 };
885
886 usbphy1: usb-phy@334 {
887 #phy-cells = <0>;
888 reg = <0x334>;
889 clocks = <&cru SCLK_OTGPHY1>;
890 clock-names = "phyclk";
891 #clock-cells = <0>;
892 };
893
894 usbphy2: usb-phy@348 {
895 #phy-cells = <0>;
896 reg = <0x348>;
897 clocks = <&cru SCLK_OTGPHY2>;
898 clock-names = "phyclk";
899 #clock-cells = <0>;
900 };
901 };
902 };
903
904 wdt: watchdog@ff800000 {
905 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
906 reg = <0x0 0xff800000 0x0 0x100>;
907 clocks = <&cru PCLK_WDT>;
908 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
909 status = "disabled";
910 };
911
912 spdif: sound@ff88b0000 {
913 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
914 reg = <0x0 0xff8b0000 0x0 0x10000>;
915 #sound-dai-cells = <0>;
916 clock-names = "hclk", "mclk";
917 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
918 dmas = <&dmac_bus_s 3>;
919 dma-names = "tx";
920 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&spdif_tx>;
923 rockchip,grf = <&grf>;
924 status = "disabled";
925 };
926
927 i2s: i2s@ff890000 {
928 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
929 reg = <0x0 0xff890000 0x0 0x10000>;
930 #sound-dai-cells = <0>;
931 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
932 #address-cells = <1>;
933 #size-cells = <0>;
934 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
935 dma-names = "tx", "rx";
936 clock-names = "i2s_hclk", "i2s_clk";
937 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
938 pinctrl-names = "default";
939 pinctrl-0 = <&i2s0_bus>;
940 rockchip,playback-channels = <8>;
941 rockchip,capture-channels = <2>;
942 status = "disabled";
943 };
944
945 crypto: cypto-controller@ff8a0000 {
946 compatible = "rockchip,rk3288-crypto";
947 reg = <0x0 0xff8a0000 0x0 0x4000>;
948 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
950 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
951 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
952 resets = <&cru SRST_CRYPTO>;
953 reset-names = "crypto-rst";
954 status = "okay";
955 };
956
957 iep_mmu: iommu@ff900800 {
958 compatible = "rockchip,iommu";
959 reg = <0x0 0xff900800 0x0 0x40>;
960 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
961 interrupt-names = "iep_mmu";
962 #iommu-cells = <0>;
963 status = "disabled";
964 };
965
966 isp_mmu: iommu@ff914000 {
967 compatible = "rockchip,iommu";
968 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
969 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
970 interrupt-names = "isp_mmu";
971 #iommu-cells = <0>;
972 rockchip,disable-mmu-reset;
973 status = "disabled";
974 };
975
976 rga: rga@ff920000 {
977 compatible = "rockchip,rk3288-rga";
978 reg = <0x0 0xff920000 0x0 0x180>;
979 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
981 clock-names = "aclk", "hclk", "sclk";
982 power-domains = <&power RK3288_PD_VIO>;
983 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
984 reset-names = "core", "axi", "ahb";
985 };
986
987 vopb: vop@ff930000 {
988 compatible = "rockchip,rk3288-vop";
989 reg = <0x0 0xff930000 0x0 0x19c>;
990 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
991 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
992 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
993 power-domains = <&power RK3288_PD_VIO>;
994 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
995 reset-names = "axi", "ahb", "dclk";
996 iommus = <&vopb_mmu>;
997 status = "disabled";
998
999 vopb_out: port {
1000 #address-cells = <1>;
1001 #size-cells = <0>;
1002
1003 vopb_out_hdmi: endpoint@0 {
1004 reg = <0>;
1005 remote-endpoint = <&hdmi_in_vopb>;
1006 };
1007
1008 vopb_out_edp: endpoint@1 {
1009 reg = <1>;
1010 remote-endpoint = <&edp_in_vopb>;
1011 };
1012
1013 vopb_out_mipi: endpoint@2 {
1014 reg = <2>;
1015 remote-endpoint = <&mipi_in_vopb>;
1016 };
1017
1018 vopb_out_lvds: endpoint@3 {
1019 reg = <3>;
1020 remote-endpoint = <&lvds_in_vopb>;
1021 };
1022 };
1023 };
1024
1025 vopb_mmu: iommu@ff930300 {
1026 compatible = "rockchip,iommu";
1027 reg = <0x0 0xff930300 0x0 0x100>;
1028 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1029 interrupt-names = "vopb_mmu";
1030 power-domains = <&power RK3288_PD_VIO>;
1031 #iommu-cells = <0>;
1032 status = "disabled";
1033 };
1034
1035 vopl: vop@ff940000 {
1036 compatible = "rockchip,rk3288-vop";
1037 reg = <0x0 0xff940000 0x0 0x19c>;
1038 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1039 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1040 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1041 power-domains = <&power RK3288_PD_VIO>;
1042 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1043 reset-names = "axi", "ahb", "dclk";
1044 iommus = <&vopl_mmu>;
1045 status = "disabled";
1046
1047 vopl_out: port {
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1050
1051 vopl_out_hdmi: endpoint@0 {
1052 reg = <0>;
1053 remote-endpoint = <&hdmi_in_vopl>;
1054 };
1055
1056 vopl_out_edp: endpoint@1 {
1057 reg = <1>;
1058 remote-endpoint = <&edp_in_vopl>;
1059 };
1060
1061 vopl_out_mipi: endpoint@2 {
1062 reg = <2>;
1063 remote-endpoint = <&mipi_in_vopl>;
1064 };
1065
1066 vopl_out_lvds: endpoint@3 {
1067 reg = <3>;
1068 remote-endpoint = <&lvds_in_vopl>;
1069 };
1070 };
1071 };
1072
1073 vopl_mmu: iommu@ff940300 {
1074 compatible = "rockchip,iommu";
1075 reg = <0x0 0xff940300 0x0 0x100>;
1076 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1077 interrupt-names = "vopl_mmu";
1078 power-domains = <&power RK3288_PD_VIO>;
1079 #iommu-cells = <0>;
1080 status = "disabled";
1081 };
1082
1083 mipi_dsi: mipi@ff960000 {
1084 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1085 reg = <0x0 0xff960000 0x0 0x4000>;
1086 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1087 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1088 clock-names = "ref", "pclk";
1089 power-domains = <&power RK3288_PD_VIO>;
1090 rockchip,grf = <&grf>;
1091 #address-cells = <1>;
1092 #size-cells = <0>;
1093 status = "disabled";
1094
1095 ports {
1096 mipi_in: port {
1097 #address-cells = <1>;
1098 #size-cells = <0>;
1099 mipi_in_vopb: endpoint@0 {
1100 reg = <0>;
1101 remote-endpoint = <&vopb_out_mipi>;
1102 };
1103 mipi_in_vopl: endpoint@1 {
1104 reg = <1>;
1105 remote-endpoint = <&vopl_out_mipi>;
1106 };
1107 };
1108 };
1109 };
1110
1111 lvds: lvds@ff96c000 {
1112 compatible = "rockchip,rk3288-lvds";
1113 reg = <0x0 0xff96c000 0x0 0x4000>;
1114 clocks = <&cru PCLK_LVDS_PHY>;
1115 clock-names = "pclk_lvds";
1116 pinctrl-names = "lcdc";
1117 pinctrl-0 = <&lcdc_ctl>;
1118 power-domains = <&power RK3288_PD_VIO>;
1119 rockchip,grf = <&grf>;
1120 status = "disabled";
1121
1122 ports {
1123 #address-cells = <1>;
1124 #size-cells = <0>;
1125
1126 lvds_in: port@0 {
1127 reg = <0>;
1128
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1131
1132 lvds_in_vopb: endpoint@0 {
1133 reg = <0>;
1134 remote-endpoint = <&vopb_out_lvds>;
1135 };
1136 lvds_in_vopl: endpoint@1 {
1137 reg = <1>;
1138 remote-endpoint = <&vopl_out_lvds>;
1139 };
1140 };
1141 };
1142 };
1143
1144 edp: dp@ff970000 {
1145 compatible = "rockchip,rk3288-dp";
1146 reg = <0x0 0xff970000 0x0 0x4000>;
1147 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1149 clock-names = "dp", "pclk";
1150 phys = <&edp_phy>;
1151 phy-names = "dp";
1152 resets = <&cru SRST_EDP>;
1153 reset-names = "dp";
1154 rockchip,grf = <&grf>;
1155 status = "disabled";
1156
1157 ports {
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1160 edp_in: port@0 {
1161 reg = <0>;
1162 #address-cells = <1>;
1163 #size-cells = <0>;
1164 edp_in_vopb: endpoint@0 {
1165 reg = <0>;
1166 remote-endpoint = <&vopb_out_edp>;
1167 };
1168 edp_in_vopl: endpoint@1 {
1169 reg = <1>;
1170 remote-endpoint = <&vopl_out_edp>;
1171 };
1172 };
1173 };
1174 };
1175
1176 hdmi: hdmi@ff980000 {
1177 compatible = "rockchip,rk3288-dw-hdmi";
1178 reg = <0x0 0xff980000 0x0 0x20000>;
1179 reg-io-width = <4>;
1180 #sound-dai-cells = <0>;
1181 rockchip,grf = <&grf>;
1182 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1184 clock-names = "iahb", "isfr", "cec";
1185 power-domains = <&power RK3288_PD_VIO>;
1186 status = "disabled";
1187
1188 ports {
1189 hdmi_in: port {
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1192 hdmi_in_vopb: endpoint@0 {
1193 reg = <0>;
1194 remote-endpoint = <&vopb_out_hdmi>;
1195 };
1196 hdmi_in_vopl: endpoint@1 {
1197 reg = <1>;
1198 remote-endpoint = <&vopl_out_hdmi>;
1199 };
1200 };
1201 };
1202 };
1203
1204 vpu_mmu: iommu@ff9a0800 {
1205 compatible = "rockchip,iommu";
1206 reg = <0x0 0xff9a0800 0x0 0x100>;
1207 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1208 interrupt-names = "vpu_mmu";
1209 #iommu-cells = <0>;
1210 status = "disabled";
1211 };
1212
1213 hevc_mmu: iommu@ff9c0440 {
1214 compatible = "rockchip,iommu";
1215 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1216 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1217 interrupt-names = "hevc_mmu";
1218 #iommu-cells = <0>;
1219 status = "disabled";
1220 };
1221
1222 gpu: gpu@ffa30000 {
1223 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1224 reg = <0x0 0xffa30000 0x0 0x10000>;
1225 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1228 interrupt-names = "job", "mmu", "gpu";
1229 clocks = <&cru ACLK_GPU>;
1230 operating-points-v2 = <&gpu_opp_table>;
1231 power-domains = <&power RK3288_PD_GPU>;
1232 status = "disabled";
1233 };
1234
1235 gpu_opp_table: gpu-opp-table {
1236 compatible = "operating-points-v2";
1237
1238 opp@100000000 {
1239 opp-hz = /bits/ 64 <100000000>;
1240 opp-microvolt = <950000>;
1241 };
1242 opp@200000000 {
1243 opp-hz = /bits/ 64 <200000000>;
1244 opp-microvolt = <950000>;
1245 };
1246 opp@300000000 {
1247 opp-hz = /bits/ 64 <300000000>;
1248 opp-microvolt = <1000000>;
1249 };
1250 opp@400000000 {
1251 opp-hz = /bits/ 64 <400000000>;
1252 opp-microvolt = <1100000>;
1253 };
1254 opp@500000000 {
1255 opp-hz = /bits/ 64 <500000000>;
1256 opp-microvolt = <1200000>;
1257 };
1258 opp@600000000 {
1259 opp-hz = /bits/ 64 <600000000>;
1260 opp-microvolt = <1250000>;
1261 };
1262 };
1263
1264 qos_gpu_r: qos@ffaa0000 {
1265 compatible = "syscon";
1266 reg = <0x0 0xffaa0000 0x0 0x20>;
1267 };
1268
1269 qos_gpu_w: qos@ffaa0080 {
1270 compatible = "syscon";
1271 reg = <0x0 0xffaa0080 0x0 0x20>;
1272 };
1273
1274 qos_vio1_vop: qos@ffad0000 {
1275 compatible = "syscon";
1276 reg = <0x0 0xffad0000 0x0 0x20>;
1277 };
1278
1279 qos_vio1_isp_w0: qos@ffad0100 {
1280 compatible = "syscon";
1281 reg = <0x0 0xffad0100 0x0 0x20>;
1282 };
1283
1284 qos_vio1_isp_w1: qos@ffad0180 {
1285 compatible = "syscon";
1286 reg = <0x0 0xffad0180 0x0 0x20>;
1287 };
1288
1289 qos_vio0_vop: qos@ffad0400 {
1290 compatible = "syscon";
1291 reg = <0x0 0xffad0400 0x0 0x20>;
1292 };
1293
1294 qos_vio0_vip: qos@ffad0480 {
1295 compatible = "syscon";
1296 reg = <0x0 0xffad0480 0x0 0x20>;
1297 };
1298
1299 qos_vio0_iep: qos@ffad0500 {
1300 compatible = "syscon";
1301 reg = <0x0 0xffad0500 0x0 0x20>;
1302 };
1303
1304 qos_vio2_rga_r: qos@ffad0800 {
1305 compatible = "syscon";
1306 reg = <0x0 0xffad0800 0x0 0x20>;
1307 };
1308
1309 qos_vio2_rga_w: qos@ffad0880 {
1310 compatible = "syscon";
1311 reg = <0x0 0xffad0880 0x0 0x20>;
1312 };
1313
1314 qos_vio1_isp_r: qos@ffad0900 {
1315 compatible = "syscon";
1316 reg = <0x0 0xffad0900 0x0 0x20>;
1317 };
1318
1319 qos_video: qos@ffae0000 {
1320 compatible = "syscon";
1321 reg = <0x0 0xffae0000 0x0 0x20>;
1322 };
1323
1324 qos_hevc_r: qos@ffaf0000 {
1325 compatible = "syscon";
1326 reg = <0x0 0xffaf0000 0x0 0x20>;
1327 };
1328
1329 qos_hevc_w: qos@ffaf0080 {
1330 compatible = "syscon";
1331 reg = <0x0 0xffaf0080 0x0 0x20>;
1332 };
1333
1334 gic: interrupt-controller@ffc01000 {
1335 compatible = "arm,gic-400";
1336 interrupt-controller;
1337 #interrupt-cells = <3>;
1338 #address-cells = <0>;
1339
1340 reg = <0x0 0xffc01000 0x0 0x1000>,
1341 <0x0 0xffc02000 0x0 0x2000>,
1342 <0x0 0xffc04000 0x0 0x2000>,
1343 <0x0 0xffc06000 0x0 0x2000>;
1344 interrupts = <GIC_PPI 9 0xf04>;
1345 };
1346
1347 efuse: efuse@ffb40000 {
1348 compatible = "rockchip,rk3288-efuse";
1349 reg = <0x0 0xffb40000 0x0 0x20>;
1350 #address-cells = <1>;
1351 #size-cells = <1>;
1352 clocks = <&cru PCLK_EFUSE256>;
1353 clock-names = "pclk_efuse";
1354
1355 cpu_leakage: cpu_leakage@17 {
1356 reg = <0x17 0x1>;
1357 };
1358 };
1359
1360 pinctrl: pinctrl {
1361 compatible = "rockchip,rk3288-pinctrl";
1362 rockchip,grf = <&grf>;
1363 rockchip,pmu = <&pmu>;
1364 #address-cells = <2>;
1365 #size-cells = <2>;
1366 ranges;
1367
1368 gpio0: gpio0@ff750000 {
1369 compatible = "rockchip,gpio-bank";
1370 reg = <0x0 0xff750000 0x0 0x100>;
1371 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1372 clocks = <&cru PCLK_GPIO0>;
1373
1374 gpio-controller;
1375 #gpio-cells = <2>;
1376
1377 interrupt-controller;
1378 #interrupt-cells = <2>;
1379 };
1380
1381 gpio1: gpio1@ff780000 {
1382 compatible = "rockchip,gpio-bank";
1383 reg = <0x0 0xff780000 0x0 0x100>;
1384 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1385 clocks = <&cru PCLK_GPIO1>;
1386
1387 gpio-controller;
1388 #gpio-cells = <2>;
1389
1390 interrupt-controller;
1391 #interrupt-cells = <2>;
1392 };
1393
1394 gpio2: gpio2@ff790000 {
1395 compatible = "rockchip,gpio-bank";
1396 reg = <0x0 0xff790000 0x0 0x100>;
1397 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1398 clocks = <&cru PCLK_GPIO2>;
1399
1400 gpio-controller;
1401 #gpio-cells = <2>;
1402
1403 interrupt-controller;
1404 #interrupt-cells = <2>;
1405 };
1406
1407 gpio3: gpio3@ff7a0000 {
1408 compatible = "rockchip,gpio-bank";
1409 reg = <0x0 0xff7a0000 0x0 0x100>;
1410 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1411 clocks = <&cru PCLK_GPIO3>;
1412
1413 gpio-controller;
1414 #gpio-cells = <2>;
1415
1416 interrupt-controller;
1417 #interrupt-cells = <2>;
1418 };
1419
1420 gpio4: gpio4@ff7b0000 {
1421 compatible = "rockchip,gpio-bank";
1422 reg = <0x0 0xff7b0000 0x0 0x100>;
1423 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1424 clocks = <&cru PCLK_GPIO4>;
1425
1426 gpio-controller;
1427 #gpio-cells = <2>;
1428
1429 interrupt-controller;
1430 #interrupt-cells = <2>;
1431 };
1432
1433 gpio5: gpio5@ff7c0000 {
1434 compatible = "rockchip,gpio-bank";
1435 reg = <0x0 0xff7c0000 0x0 0x100>;
1436 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1437 clocks = <&cru PCLK_GPIO5>;
1438
1439 gpio-controller;
1440 #gpio-cells = <2>;
1441
1442 interrupt-controller;
1443 #interrupt-cells = <2>;
1444 };
1445
1446 gpio6: gpio6@ff7d0000 {
1447 compatible = "rockchip,gpio-bank";
1448 reg = <0x0 0xff7d0000 0x0 0x100>;
1449 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1450 clocks = <&cru PCLK_GPIO6>;
1451
1452 gpio-controller;
1453 #gpio-cells = <2>;
1454
1455 interrupt-controller;
1456 #interrupt-cells = <2>;
1457 };
1458
1459 gpio7: gpio7@ff7e0000 {
1460 compatible = "rockchip,gpio-bank";
1461 reg = <0x0 0xff7e0000 0x0 0x100>;
1462 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1463 clocks = <&cru PCLK_GPIO7>;
1464
1465 gpio-controller;
1466 #gpio-cells = <2>;
1467
1468 interrupt-controller;
1469 #interrupt-cells = <2>;
1470 };
1471
1472 gpio8: gpio8@ff7f0000 {
1473 compatible = "rockchip,gpio-bank";
1474 reg = <0x0 0xff7f0000 0x0 0x100>;
1475 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1476 clocks = <&cru PCLK_GPIO8>;
1477
1478 gpio-controller;
1479 #gpio-cells = <2>;
1480
1481 interrupt-controller;
1482 #interrupt-cells = <2>;
1483 };
1484
1485 hdmi {
1486 hdmi_cec_c0: hdmi-cec-c0 {
1487 rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
1488 };
1489
1490 hdmi_cec_c7: hdmi-cec-c7 {
1491 rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>;
1492 };
1493
1494 hdmi_ddc: hdmi-ddc {
1495 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1496 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1497 };
1498 };
1499
1500 pcfg_pull_up: pcfg-pull-up {
1501 bias-pull-up;
1502 };
1503
1504 pcfg_pull_down: pcfg-pull-down {
1505 bias-pull-down;
1506 };
1507
1508 pcfg_pull_none: pcfg-pull-none {
1509 bias-disable;
1510 };
1511
1512 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1513 bias-disable;
1514 drive-strength = <12>;
1515 };
1516
1517 sleep {
1518 global_pwroff: global-pwroff {
1519 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1520 };
1521
1522 ddrio_pwroff: ddrio-pwroff {
1523 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1524 };
1525
1526 ddr0_retention: ddr0-retention {
1527 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1528 };
1529
1530 ddr1_retention: ddr1-retention {
1531 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1532 };
1533 };
1534
1535 edp {
1536 edp_hpd: edp-hpd {
1537 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1538 };
1539 };
1540
1541 i2c0 {
1542 i2c0_xfer: i2c0-xfer {
1543 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1544 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1545 };
1546 };
1547
1548 i2c1 {
1549 i2c1_xfer: i2c1-xfer {
1550 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1551 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1552 };
1553 };
1554
1555 i2c2 {
1556 i2c2_xfer: i2c2-xfer {
1557 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1558 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1559 };
1560 };
1561
1562 i2c3 {
1563 i2c3_xfer: i2c3-xfer {
1564 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1565 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1566 };
1567 };
1568
1569 i2c4 {
1570 i2c4_xfer: i2c4-xfer {
1571 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1572 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1573 };
1574 };
1575
1576 i2c5 {
1577 i2c5_xfer: i2c5-xfer {
1578 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1579 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1580 };
1581 };
1582
1583 i2s0 {
1584 i2s0_bus: i2s0-bus {
1585 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1586 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1587 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1588 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1589 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1590 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1591 };
1592 };
1593
1594 lcdc {
1595 lcdc_ctl: lcdc-ctl {
1596 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1597 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1598 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1599 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1600 };
1601 };
1602
1603 sdmmc {
1604 sdmmc_clk: sdmmc-clk {
1605 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1606 };
1607
1608 sdmmc_cmd: sdmmc-cmd {
1609 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1610 };
1611
1612 sdmmc_cd: sdmmc-cd {
1613 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1614 };
1615
1616 sdmmc_bus1: sdmmc-bus1 {
1617 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1618 };
1619
1620 sdmmc_bus4: sdmmc-bus4 {
1621 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1622 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1623 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1624 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1625 };
1626 };
1627
1628 sdio0 {
1629 sdio0_bus1: sdio0-bus1 {
1630 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1631 };
1632
1633 sdio0_bus4: sdio0-bus4 {
1634 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1635 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1636 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1637 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1638 };
1639
1640 sdio0_cmd: sdio0-cmd {
1641 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1642 };
1643
1644 sdio0_clk: sdio0-clk {
1645 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1646 };
1647
1648 sdio0_cd: sdio0-cd {
1649 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1650 };
1651
1652 sdio0_wp: sdio0-wp {
1653 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1654 };
1655
1656 sdio0_pwr: sdio0-pwr {
1657 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1658 };
1659
1660 sdio0_bkpwr: sdio0-bkpwr {
1661 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1662 };
1663
1664 sdio0_int: sdio0-int {
1665 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1666 };
1667 };
1668
1669 sdio1 {
1670 sdio1_bus1: sdio1-bus1 {
1671 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1672 };
1673
1674 sdio1_bus4: sdio1-bus4 {
1675 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1676 <3 25 4 &pcfg_pull_up>,
1677 <3 26 4 &pcfg_pull_up>,
1678 <3 27 4 &pcfg_pull_up>;
1679 };
1680
1681 sdio1_cd: sdio1-cd {
1682 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1683 };
1684
1685 sdio1_wp: sdio1-wp {
1686 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1687 };
1688
1689 sdio1_bkpwr: sdio1-bkpwr {
1690 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1691 };
1692
1693 sdio1_int: sdio1-int {
1694 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1695 };
1696
1697 sdio1_cmd: sdio1-cmd {
1698 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1699 };
1700
1701 sdio1_clk: sdio1-clk {
1702 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1703 };
1704
1705 sdio1_pwr: sdio1-pwr {
1706 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1707 };
1708 };
1709
1710 emmc {
1711 emmc_clk: emmc-clk {
1712 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1713 };
1714
1715 emmc_cmd: emmc-cmd {
1716 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1717 };
1718
1719 emmc_pwr: emmc-pwr {
1720 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1721 };
1722
1723 emmc_bus1: emmc-bus1 {
1724 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1725 };
1726
1727 emmc_bus4: emmc-bus4 {
1728 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1729 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1730 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1731 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1732 };
1733
1734 emmc_bus8: emmc-bus8 {
1735 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1736 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1737 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1738 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1739 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1740 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1741 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1742 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1743 };
1744 };
1745
1746 spi0 {
1747 spi0_clk: spi0-clk {
1748 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1749 };
1750 spi0_cs0: spi0-cs0 {
1751 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1752 };
1753 spi0_tx: spi0-tx {
1754 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1755 };
1756 spi0_rx: spi0-rx {
1757 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1758 };
1759 spi0_cs1: spi0-cs1 {
1760 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1761 };
1762 };
1763 spi1 {
1764 spi1_clk: spi1-clk {
1765 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1766 };
1767 spi1_cs0: spi1-cs0 {
1768 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1769 };
1770 spi1_rx: spi1-rx {
1771 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1772 };
1773 spi1_tx: spi1-tx {
1774 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1775 };
1776 };
1777
1778 spi2 {
1779 spi2_cs1: spi2-cs1 {
1780 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1781 };
1782 spi2_clk: spi2-clk {
1783 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1784 };
1785 spi2_cs0: spi2-cs0 {
1786 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1787 };
1788 spi2_rx: spi2-rx {
1789 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1790 };
1791 spi2_tx: spi2-tx {
1792 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1793 };
1794 };
1795
1796 uart0 {
1797 uart0_xfer: uart0-xfer {
1798 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1799 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1800 };
1801
1802 uart0_cts: uart0-cts {
1803 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1804 };
1805
1806 uart0_rts: uart0-rts {
1807 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1808 };
1809 };
1810
1811 uart1 {
1812 uart1_xfer: uart1-xfer {
1813 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1814 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1815 };
1816
1817 uart1_cts: uart1-cts {
1818 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1819 };
1820
1821 uart1_rts: uart1-rts {
1822 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1823 };
1824 };
1825
1826 uart2 {
1827 uart2_xfer: uart2-xfer {
1828 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1829 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1830 };
1831 /* no rts / cts for uart2 */
1832 };
1833
1834 uart3 {
1835 uart3_xfer: uart3-xfer {
1836 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1837 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1838 };
1839
1840 uart3_cts: uart3-cts {
1841 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1842 };
1843
1844 uart3_rts: uart3-rts {
1845 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1846 };
1847 };
1848
1849 uart4 {
1850 uart4_xfer: uart4-xfer {
1851 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1852 <5 13 3 &pcfg_pull_none>;
1853 };
1854
1855 uart4_cts: uart4-cts {
1856 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1857 };
1858
1859 uart4_rts: uart4-rts {
1860 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1861 };
1862 };
1863
1864 tsadc {
1865 otp_gpio: otp-gpio {
1866 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1867 };
1868
1869 otp_out: otp-out {
1870 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1871 };
1872 };
1873
1874 pwm0 {
1875 pwm0_pin: pwm0-pin {
1876 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1877 };
1878 };
1879
1880 pwm1 {
1881 pwm1_pin: pwm1-pin {
1882 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1883 };
1884 };
1885
1886 pwm2 {
1887 pwm2_pin: pwm2-pin {
1888 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1889 };
1890 };
1891
1892 pwm3 {
1893 pwm3_pin: pwm3-pin {
1894 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1895 };
1896 };
1897
1898 gmac {
1899 rgmii_pins: rgmii-pins {
1900 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1901 <3 31 3 &pcfg_pull_none>,
1902 <3 26 3 &pcfg_pull_none>,
1903 <3 27 3 &pcfg_pull_none>,
1904 <3 28 3 &pcfg_pull_none_12ma>,
1905 <3 29 3 &pcfg_pull_none_12ma>,
1906 <3 24 3 &pcfg_pull_none_12ma>,
1907 <3 25 3 &pcfg_pull_none_12ma>,
1908 <4 0 3 &pcfg_pull_none>,
1909 <4 5 3 &pcfg_pull_none>,
1910 <4 6 3 &pcfg_pull_none>,
1911 <4 9 3 &pcfg_pull_none_12ma>,
1912 <4 4 3 &pcfg_pull_none_12ma>,
1913 <4 1 3 &pcfg_pull_none>,
1914 <4 3 3 &pcfg_pull_none>;
1915 };
1916
1917 rmii_pins: rmii-pins {
1918 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1919 <3 31 3 &pcfg_pull_none>,
1920 <3 28 3 &pcfg_pull_none>,
1921 <3 29 3 &pcfg_pull_none>,
1922 <4 0 3 &pcfg_pull_none>,
1923 <4 5 3 &pcfg_pull_none>,
1924 <4 4 3 &pcfg_pull_none>,
1925 <4 1 3 &pcfg_pull_none>,
1926 <4 2 3 &pcfg_pull_none>,
1927 <4 3 3 &pcfg_pull_none>;
1928 };
1929 };
1930
1931 spdif {
1932 spdif_tx: spdif-tx {
1933 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1934 };
1935 };
1936 };
1937};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/pinctrl/rockchip.h>
7#include <dt-bindings/clock/rk3288-cru.h>
8#include <dt-bindings/power/rk3288-power.h>
9#include <dt-bindings/thermal/thermal.h>
10#include <dt-bindings/soc/rockchip,boot-mode.h>
11
12/ {
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 compatible = "rockchip,rk3288";
17
18 interrupt-parent = <&gic>;
19
20 aliases {
21 ethernet0 = &gmac;
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 i2c4 = &i2c4;
27 i2c5 = &i2c5;
28 mshc0 = &emmc;
29 mshc1 = &sdmmc;
30 mshc2 = &sdio0;
31 mshc3 = &sdio1;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 spi0 = &spi0;
38 spi1 = &spi1;
39 spi2 = &spi2;
40 };
41
42 arm-pmu {
43 compatible = "arm,cortex-a12-pmu";
44 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
48 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "rockchip,rk3066-smp";
55 rockchip,pmu = <&pmu>;
56
57 cpu0: cpu@500 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a12";
60 reg = <0x500>;
61 resets = <&cru SRST_CORE0>;
62 operating-points-v2 = <&cpu_opp_table>;
63 #cooling-cells = <2>; /* min followed by max */
64 clock-latency = <40000>;
65 clocks = <&cru ARMCLK>;
66 dynamic-power-coefficient = <370>;
67 };
68 cpu1: cpu@501 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a12";
71 reg = <0x501>;
72 resets = <&cru SRST_CORE1>;
73 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>; /* min followed by max */
75 clock-latency = <40000>;
76 clocks = <&cru ARMCLK>;
77 dynamic-power-coefficient = <370>;
78 };
79 cpu2: cpu@502 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a12";
82 reg = <0x502>;
83 resets = <&cru SRST_CORE2>;
84 operating-points-v2 = <&cpu_opp_table>;
85 #cooling-cells = <2>; /* min followed by max */
86 clock-latency = <40000>;
87 clocks = <&cru ARMCLK>;
88 dynamic-power-coefficient = <370>;
89 };
90 cpu3: cpu@503 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a12";
93 reg = <0x503>;
94 resets = <&cru SRST_CORE3>;
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>; /* min followed by max */
97 clock-latency = <40000>;
98 clocks = <&cru ARMCLK>;
99 dynamic-power-coefficient = <370>;
100 };
101 };
102
103 cpu_opp_table: cpu-opp-table {
104 compatible = "operating-points-v2";
105 opp-shared;
106
107 opp-126000000 {
108 opp-hz = /bits/ 64 <126000000>;
109 opp-microvolt = <900000>;
110 };
111 opp-216000000 {
112 opp-hz = /bits/ 64 <216000000>;
113 opp-microvolt = <900000>;
114 };
115 opp-312000000 {
116 opp-hz = /bits/ 64 <312000000>;
117 opp-microvolt = <900000>;
118 };
119 opp-408000000 {
120 opp-hz = /bits/ 64 <408000000>;
121 opp-microvolt = <900000>;
122 };
123 opp-600000000 {
124 opp-hz = /bits/ 64 <600000000>;
125 opp-microvolt = <900000>;
126 };
127 opp-696000000 {
128 opp-hz = /bits/ 64 <696000000>;
129 opp-microvolt = <950000>;
130 };
131 opp-816000000 {
132 opp-hz = /bits/ 64 <816000000>;
133 opp-microvolt = <1000000>;
134 };
135 opp-1008000000 {
136 opp-hz = /bits/ 64 <1008000000>;
137 opp-microvolt = <1050000>;
138 };
139 opp-1200000000 {
140 opp-hz = /bits/ 64 <1200000000>;
141 opp-microvolt = <1100000>;
142 };
143 opp-1416000000 {
144 opp-hz = /bits/ 64 <1416000000>;
145 opp-microvolt = <1200000>;
146 };
147 opp-1512000000 {
148 opp-hz = /bits/ 64 <1512000000>;
149 opp-microvolt = <1300000>;
150 };
151 opp-1608000000 {
152 opp-hz = /bits/ 64 <1608000000>;
153 opp-microvolt = <1350000>;
154 };
155 };
156
157 reserved-memory {
158 #address-cells = <2>;
159 #size-cells = <2>;
160 ranges;
161
162 /*
163 * The rk3288 cannot use the memory area above 0xfe000000
164 * for dma operations for some reason. While there is
165 * probably a better solution available somewhere, we
166 * haven't found it yet and while devices with 2GB of ram
167 * are not affected, this issue prevents 4GB from booting.
168 * So to make these devices at least bootable, block
169 * this area for the time being until the real solution
170 * is found.
171 */
172 dma-unusable@fe000000 {
173 reg = <0x0 0xfe000000 0x0 0x1000000>;
174 };
175 };
176
177 xin24m: oscillator {
178 compatible = "fixed-clock";
179 clock-frequency = <24000000>;
180 clock-output-names = "xin24m";
181 #clock-cells = <0>;
182 };
183
184 timer {
185 compatible = "arm,armv7-timer";
186 arm,cpu-registers-not-fw-configured;
187 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
188 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
189 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
190 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
191 clock-frequency = <24000000>;
192 arm,no-tick-in-suspend;
193 };
194
195 timer: timer@ff810000 {
196 compatible = "rockchip,rk3288-timer";
197 reg = <0x0 0xff810000 0x0 0x20>;
198 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&cru PCLK_TIMER>, <&xin24m>;
200 clock-names = "pclk", "timer";
201 };
202
203 display-subsystem {
204 compatible = "rockchip,display-subsystem";
205 ports = <&vopl_out>, <&vopb_out>;
206 };
207
208 sdmmc: mmc@ff0c0000 {
209 compatible = "rockchip,rk3288-dw-mshc";
210 max-frequency = <150000000>;
211 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
212 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
215 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
216 reg = <0x0 0xff0c0000 0x0 0x4000>;
217 resets = <&cru SRST_MMC0>;
218 reset-names = "reset";
219 status = "disabled";
220 };
221
222 sdio0: mmc@ff0d0000 {
223 compatible = "rockchip,rk3288-dw-mshc";
224 max-frequency = <150000000>;
225 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
226 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
227 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
228 fifo-depth = <0x100>;
229 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
230 reg = <0x0 0xff0d0000 0x0 0x4000>;
231 resets = <&cru SRST_SDIO0>;
232 reset-names = "reset";
233 status = "disabled";
234 };
235
236 sdio1: mmc@ff0e0000 {
237 compatible = "rockchip,rk3288-dw-mshc";
238 max-frequency = <150000000>;
239 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
240 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
242 fifo-depth = <0x100>;
243 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
244 reg = <0x0 0xff0e0000 0x0 0x4000>;
245 resets = <&cru SRST_SDIO1>;
246 reset-names = "reset";
247 status = "disabled";
248 };
249
250 emmc: mmc@ff0f0000 {
251 compatible = "rockchip,rk3288-dw-mshc";
252 max-frequency = <150000000>;
253 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
254 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
255 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
256 fifo-depth = <0x100>;
257 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
258 reg = <0x0 0xff0f0000 0x0 0x4000>;
259 resets = <&cru SRST_EMMC>;
260 reset-names = "reset";
261 status = "disabled";
262 };
263
264 saradc: saradc@ff100000 {
265 compatible = "rockchip,saradc";
266 reg = <0x0 0xff100000 0x0 0x100>;
267 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
268 #io-channel-cells = <1>;
269 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
270 clock-names = "saradc", "apb_pclk";
271 resets = <&cru SRST_SARADC>;
272 reset-names = "saradc-apb";
273 status = "disabled";
274 };
275
276 spi0: spi@ff110000 {
277 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
278 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
279 clock-names = "spiclk", "apb_pclk";
280 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
281 dma-names = "tx", "rx";
282 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
285 reg = <0x0 0xff110000 0x0 0x1000>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288 status = "disabled";
289 };
290
291 spi1: spi@ff120000 {
292 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
293 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
294 clock-names = "spiclk", "apb_pclk";
295 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
296 dma-names = "tx", "rx";
297 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
300 reg = <0x0 0xff120000 0x0 0x1000>;
301 #address-cells = <1>;
302 #size-cells = <0>;
303 status = "disabled";
304 };
305
306 spi2: spi@ff130000 {
307 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
308 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
309 clock-names = "spiclk", "apb_pclk";
310 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
311 dma-names = "tx", "rx";
312 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
315 reg = <0x0 0xff130000 0x0 0x1000>;
316 #address-cells = <1>;
317 #size-cells = <0>;
318 status = "disabled";
319 };
320
321 i2c1: i2c@ff140000 {
322 compatible = "rockchip,rk3288-i2c";
323 reg = <0x0 0xff140000 0x0 0x1000>;
324 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327 clock-names = "i2c";
328 clocks = <&cru PCLK_I2C1>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&i2c1_xfer>;
331 status = "disabled";
332 };
333
334 i2c3: i2c@ff150000 {
335 compatible = "rockchip,rk3288-i2c";
336 reg = <0x0 0xff150000 0x0 0x1000>;
337 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
339 #size-cells = <0>;
340 clock-names = "i2c";
341 clocks = <&cru PCLK_I2C3>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&i2c3_xfer>;
344 status = "disabled";
345 };
346
347 i2c4: i2c@ff160000 {
348 compatible = "rockchip,rk3288-i2c";
349 reg = <0x0 0xff160000 0x0 0x1000>;
350 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353 clock-names = "i2c";
354 clocks = <&cru PCLK_I2C4>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c4_xfer>;
357 status = "disabled";
358 };
359
360 i2c5: i2c@ff170000 {
361 compatible = "rockchip,rk3288-i2c";
362 reg = <0x0 0xff170000 0x0 0x1000>;
363 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
365 #size-cells = <0>;
366 clock-names = "i2c";
367 clocks = <&cru PCLK_I2C5>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&i2c5_xfer>;
370 status = "disabled";
371 };
372
373 uart0: serial@ff180000 {
374 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
375 reg = <0x0 0xff180000 0x0 0x100>;
376 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
377 reg-shift = <2>;
378 reg-io-width = <4>;
379 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
380 clock-names = "baudclk", "apb_pclk";
381 dmas = <&dmac_peri 1>, <&dmac_peri 2>;
382 dma-names = "tx", "rx";
383 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer>;
385 status = "disabled";
386 };
387
388 uart1: serial@ff190000 {
389 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
390 reg = <0x0 0xff190000 0x0 0x100>;
391 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
392 reg-shift = <2>;
393 reg-io-width = <4>;
394 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
395 clock-names = "baudclk", "apb_pclk";
396 dmas = <&dmac_peri 3>, <&dmac_peri 4>;
397 dma-names = "tx", "rx";
398 pinctrl-names = "default";
399 pinctrl-0 = <&uart1_xfer>;
400 status = "disabled";
401 };
402
403 uart2: serial@ff690000 {
404 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
405 reg = <0x0 0xff690000 0x0 0x100>;
406 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
407 reg-shift = <2>;
408 reg-io-width = <4>;
409 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
410 clock-names = "baudclk", "apb_pclk";
411 pinctrl-names = "default";
412 pinctrl-0 = <&uart2_xfer>;
413 status = "disabled";
414 };
415
416 uart3: serial@ff1b0000 {
417 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
418 reg = <0x0 0xff1b0000 0x0 0x100>;
419 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
420 reg-shift = <2>;
421 reg-io-width = <4>;
422 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
423 clock-names = "baudclk", "apb_pclk";
424 dmas = <&dmac_peri 7>, <&dmac_peri 8>;
425 dma-names = "tx", "rx";
426 pinctrl-names = "default";
427 pinctrl-0 = <&uart3_xfer>;
428 status = "disabled";
429 };
430
431 uart4: serial@ff1c0000 {
432 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
433 reg = <0x0 0xff1c0000 0x0 0x100>;
434 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
435 reg-shift = <2>;
436 reg-io-width = <4>;
437 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
438 clock-names = "baudclk", "apb_pclk";
439 dmas = <&dmac_peri 9>, <&dmac_peri 10>;
440 dma-names = "tx", "rx";
441 pinctrl-names = "default";
442 pinctrl-0 = <&uart4_xfer>;
443 status = "disabled";
444 };
445
446 dmac_peri: dma-controller@ff250000 {
447 compatible = "arm,pl330", "arm,primecell";
448 reg = <0x0 0xff250000 0x0 0x4000>;
449 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
451 #dma-cells = <1>;
452 arm,pl330-broken-no-flushp;
453 arm,pl330-periph-burst;
454 clocks = <&cru ACLK_DMAC2>;
455 clock-names = "apb_pclk";
456 };
457
458 thermal-zones {
459 reserve_thermal: reserve-thermal {
460 polling-delay-passive = <1000>; /* milliseconds */
461 polling-delay = <5000>; /* milliseconds */
462
463 thermal-sensors = <&tsadc 0>;
464 };
465
466 cpu_thermal: cpu-thermal {
467 polling-delay-passive = <100>; /* milliseconds */
468 polling-delay = <5000>; /* milliseconds */
469
470 thermal-sensors = <&tsadc 1>;
471
472 trips {
473 cpu_alert0: cpu_alert0 {
474 temperature = <70000>; /* millicelsius */
475 hysteresis = <2000>; /* millicelsius */
476 type = "passive";
477 };
478 cpu_alert1: cpu_alert1 {
479 temperature = <75000>; /* millicelsius */
480 hysteresis = <2000>; /* millicelsius */
481 type = "passive";
482 };
483 cpu_crit: cpu_crit {
484 temperature = <90000>; /* millicelsius */
485 hysteresis = <2000>; /* millicelsius */
486 type = "critical";
487 };
488 };
489
490 cooling-maps {
491 map0 {
492 trip = <&cpu_alert0>;
493 cooling-device =
494 <&cpu0 THERMAL_NO_LIMIT 6>,
495 <&cpu1 THERMAL_NO_LIMIT 6>,
496 <&cpu2 THERMAL_NO_LIMIT 6>,
497 <&cpu3 THERMAL_NO_LIMIT 6>;
498 };
499 map1 {
500 trip = <&cpu_alert1>;
501 cooling-device =
502 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
503 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
504 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
505 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
506 };
507 };
508 };
509
510 gpu_thermal: gpu-thermal {
511 polling-delay-passive = <100>; /* milliseconds */
512 polling-delay = <5000>; /* milliseconds */
513
514 thermal-sensors = <&tsadc 2>;
515
516 trips {
517 gpu_alert0: gpu_alert0 {
518 temperature = <70000>; /* millicelsius */
519 hysteresis = <2000>; /* millicelsius */
520 type = "passive";
521 };
522 gpu_crit: gpu_crit {
523 temperature = <90000>; /* millicelsius */
524 hysteresis = <2000>; /* millicelsius */
525 type = "critical";
526 };
527 };
528
529 cooling-maps {
530 map0 {
531 trip = <&gpu_alert0>;
532 cooling-device =
533 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
534 };
535 };
536 };
537 };
538
539 tsadc: tsadc@ff280000 {
540 compatible = "rockchip,rk3288-tsadc";
541 reg = <0x0 0xff280000 0x0 0x100>;
542 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
544 clock-names = "tsadc", "apb_pclk";
545 resets = <&cru SRST_TSADC>;
546 reset-names = "tsadc-apb";
547 pinctrl-names = "init", "default", "sleep";
548 pinctrl-0 = <&otp_pin>;
549 pinctrl-1 = <&otp_out>;
550 pinctrl-2 = <&otp_pin>;
551 #thermal-sensor-cells = <1>;
552 rockchip,grf = <&grf>;
553 rockchip,hw-tshut-temp = <95000>;
554 status = "disabled";
555 };
556
557 gmac: ethernet@ff290000 {
558 compatible = "rockchip,rk3288-gmac";
559 reg = <0x0 0xff290000 0x0 0x10000>;
560 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
562 interrupt-names = "macirq", "eth_wake_irq";
563 rockchip,grf = <&grf>;
564 clocks = <&cru SCLK_MAC>,
565 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
566 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
567 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
568 clock-names = "stmmaceth",
569 "mac_clk_rx", "mac_clk_tx",
570 "clk_mac_ref", "clk_mac_refout",
571 "aclk_mac", "pclk_mac";
572 resets = <&cru SRST_MAC>;
573 reset-names = "stmmaceth";
574 status = "disabled";
575 };
576
577 usb_host0_ehci: usb@ff500000 {
578 compatible = "generic-ehci";
579 reg = <0x0 0xff500000 0x0 0x100>;
580 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&cru HCLK_USBHOST0>;
582 phys = <&usbphy1>;
583 phy-names = "usb";
584 status = "disabled";
585 };
586
587 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */
588 usb_host0_ohci: usb@ff520000 {
589 compatible = "generic-ohci";
590 reg = <0x0 0xff520000 0x0 0x100>;
591 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&cru HCLK_USBHOST0>;
593 phys = <&usbphy1>;
594 phy-names = "usb";
595 status = "disabled";
596 };
597
598 usb_host1: usb@ff540000 {
599 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
600 "snps,dwc2";
601 reg = <0x0 0xff540000 0x0 0x40000>;
602 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cru HCLK_USBHOST1>;
604 clock-names = "otg";
605 dr_mode = "host";
606 phys = <&usbphy2>;
607 phy-names = "usb2-phy";
608 snps,reset-phy-on-wake;
609 status = "disabled";
610 };
611
612 usb_otg: usb@ff580000 {
613 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
614 "snps,dwc2";
615 reg = <0x0 0xff580000 0x0 0x40000>;
616 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&cru HCLK_OTG0>;
618 clock-names = "otg";
619 dr_mode = "otg";
620 g-np-tx-fifo-size = <16>;
621 g-rx-fifo-size = <275>;
622 g-tx-fifo-size = <256 128 128 64 64 32>;
623 phys = <&usbphy0>;
624 phy-names = "usb2-phy";
625 status = "disabled";
626 };
627
628 usb_hsic: usb@ff5c0000 {
629 compatible = "generic-ehci";
630 reg = <0x0 0xff5c0000 0x0 0x100>;
631 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&cru HCLK_HSIC>;
633 status = "disabled";
634 };
635
636 dmac_bus_ns: dma-controller@ff600000 {
637 compatible = "arm,pl330", "arm,primecell";
638 reg = <0x0 0xff600000 0x0 0x4000>;
639 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
641 #dma-cells = <1>;
642 arm,pl330-broken-no-flushp;
643 arm,pl330-periph-burst;
644 clocks = <&cru ACLK_DMAC1>;
645 clock-names = "apb_pclk";
646 status = "disabled";
647 };
648
649 i2c0: i2c@ff650000 {
650 compatible = "rockchip,rk3288-i2c";
651 reg = <0x0 0xff650000 0x0 0x1000>;
652 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
653 #address-cells = <1>;
654 #size-cells = <0>;
655 clock-names = "i2c";
656 clocks = <&cru PCLK_I2C0>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&i2c0_xfer>;
659 status = "disabled";
660 };
661
662 i2c2: i2c@ff660000 {
663 compatible = "rockchip,rk3288-i2c";
664 reg = <0x0 0xff660000 0x0 0x1000>;
665 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
666 #address-cells = <1>;
667 #size-cells = <0>;
668 clock-names = "i2c";
669 clocks = <&cru PCLK_I2C2>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&i2c2_xfer>;
672 status = "disabled";
673 };
674
675 pwm0: pwm@ff680000 {
676 compatible = "rockchip,rk3288-pwm";
677 reg = <0x0 0xff680000 0x0 0x10>;
678 #pwm-cells = <3>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pwm0_pin>;
681 clocks = <&cru PCLK_RKPWM>;
682 status = "disabled";
683 };
684
685 pwm1: pwm@ff680010 {
686 compatible = "rockchip,rk3288-pwm";
687 reg = <0x0 0xff680010 0x0 0x10>;
688 #pwm-cells = <3>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&pwm1_pin>;
691 clocks = <&cru PCLK_RKPWM>;
692 status = "disabled";
693 };
694
695 pwm2: pwm@ff680020 {
696 compatible = "rockchip,rk3288-pwm";
697 reg = <0x0 0xff680020 0x0 0x10>;
698 #pwm-cells = <3>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&pwm2_pin>;
701 clocks = <&cru PCLK_RKPWM>;
702 status = "disabled";
703 };
704
705 pwm3: pwm@ff680030 {
706 compatible = "rockchip,rk3288-pwm";
707 reg = <0x0 0xff680030 0x0 0x10>;
708 #pwm-cells = <3>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&pwm3_pin>;
711 clocks = <&cru PCLK_RKPWM>;
712 status = "disabled";
713 };
714
715 bus_intmem: sram@ff700000 {
716 compatible = "mmio-sram";
717 reg = <0x0 0xff700000 0x0 0x18000>;
718 #address-cells = <1>;
719 #size-cells = <1>;
720 ranges = <0 0x0 0xff700000 0x18000>;
721 smp-sram@0 {
722 compatible = "rockchip,rk3066-smp-sram";
723 reg = <0x00 0x10>;
724 };
725 };
726
727 pmu_sram: sram@ff720000 {
728 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
729 reg = <0x0 0xff720000 0x0 0x1000>;
730 };
731
732 pmu: power-management@ff730000 {
733 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
734 reg = <0x0 0xff730000 0x0 0x100>;
735
736 power: power-controller {
737 compatible = "rockchip,rk3288-power-controller";
738 #power-domain-cells = <1>;
739 #address-cells = <1>;
740 #size-cells = <0>;
741
742 assigned-clocks = <&cru SCLK_EDP_24M>;
743 assigned-clock-parents = <&xin24m>;
744
745 /*
746 * Note: Although SCLK_* are the working clocks
747 * of device without including on the NOC, needed for
748 * synchronous reset.
749 *
750 * The clocks on the which NOC:
751 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
752 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
753 * ACLK_RGA is on ACLK_RGA_NIU.
754 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
755 *
756 * Which clock are device clocks:
757 * clocks devices
758 * *_IEP IEP:Image Enhancement Processor
759 * *_ISP ISP:Image Signal Processing
760 * *_VIP VIP:Video Input Processor
761 * *_VOP* VOP:Visual Output Processor
762 * *_RGA RGA
763 * *_EDP* EDP
764 * *_LVDS_* LVDS
765 * *_HDMI HDMI
766 * *_MIPI_* MIPI
767 */
768 power-domain@RK3288_PD_VIO {
769 reg = <RK3288_PD_VIO>;
770 clocks = <&cru ACLK_IEP>,
771 <&cru ACLK_ISP>,
772 <&cru ACLK_RGA>,
773 <&cru ACLK_VIP>,
774 <&cru ACLK_VOP0>,
775 <&cru ACLK_VOP1>,
776 <&cru DCLK_VOP0>,
777 <&cru DCLK_VOP1>,
778 <&cru HCLK_IEP>,
779 <&cru HCLK_ISP>,
780 <&cru HCLK_RGA>,
781 <&cru HCLK_VIP>,
782 <&cru HCLK_VOP0>,
783 <&cru HCLK_VOP1>,
784 <&cru PCLK_EDP_CTRL>,
785 <&cru PCLK_HDMI_CTRL>,
786 <&cru PCLK_LVDS_PHY>,
787 <&cru PCLK_MIPI_CSI>,
788 <&cru PCLK_MIPI_DSI0>,
789 <&cru PCLK_MIPI_DSI1>,
790 <&cru SCLK_EDP_24M>,
791 <&cru SCLK_EDP>,
792 <&cru SCLK_ISP_JPE>,
793 <&cru SCLK_ISP>,
794 <&cru SCLK_RGA>;
795 pm_qos = <&qos_vio0_iep>,
796 <&qos_vio1_vop>,
797 <&qos_vio1_isp_w0>,
798 <&qos_vio1_isp_w1>,
799 <&qos_vio0_vop>,
800 <&qos_vio0_vip>,
801 <&qos_vio2_rga_r>,
802 <&qos_vio2_rga_w>,
803 <&qos_vio1_isp_r>;
804 #power-domain-cells = <0>;
805 };
806
807 /*
808 * Note: The following 3 are HEVC(H.265) clocks,
809 * and on the ACLK_HEVC_NIU (NOC).
810 */
811 power-domain@RK3288_PD_HEVC {
812 reg = <RK3288_PD_HEVC>;
813 clocks = <&cru ACLK_HEVC>,
814 <&cru SCLK_HEVC_CABAC>,
815 <&cru SCLK_HEVC_CORE>;
816 pm_qos = <&qos_hevc_r>,
817 <&qos_hevc_w>;
818 #power-domain-cells = <0>;
819 };
820
821 /*
822 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
823 * (video endecoder & decoder) clocks that on the
824 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
825 */
826 power-domain@RK3288_PD_VIDEO {
827 reg = <RK3288_PD_VIDEO>;
828 clocks = <&cru ACLK_VCODEC>,
829 <&cru HCLK_VCODEC>;
830 pm_qos = <&qos_video>;
831 #power-domain-cells = <0>;
832 };
833
834 /*
835 * Note: ACLK_GPU is the GPU clock,
836 * and on the ACLK_GPU_NIU (NOC).
837 */
838 power-domain@RK3288_PD_GPU {
839 reg = <RK3288_PD_GPU>;
840 clocks = <&cru ACLK_GPU>;
841 pm_qos = <&qos_gpu_r>,
842 <&qos_gpu_w>;
843 #power-domain-cells = <0>;
844 };
845 };
846
847 reboot-mode {
848 compatible = "syscon-reboot-mode";
849 offset = <0x94>;
850 mode-normal = <BOOT_NORMAL>;
851 mode-recovery = <BOOT_RECOVERY>;
852 mode-bootloader = <BOOT_FASTBOOT>;
853 mode-loader = <BOOT_BL_DOWNLOAD>;
854 };
855 };
856
857 sgrf: syscon@ff740000 {
858 compatible = "rockchip,rk3288-sgrf", "syscon";
859 reg = <0x0 0xff740000 0x0 0x1000>;
860 };
861
862 cru: clock-controller@ff760000 {
863 compatible = "rockchip,rk3288-cru";
864 reg = <0x0 0xff760000 0x0 0x1000>;
865 rockchip,grf = <&grf>;
866 #clock-cells = <1>;
867 #reset-cells = <1>;
868 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
869 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
870 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
871 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
872 <&cru PCLK_PERI>;
873 assigned-clock-rates = <594000000>, <400000000>,
874 <500000000>, <300000000>,
875 <150000000>, <75000000>,
876 <300000000>, <150000000>,
877 <75000000>;
878 };
879
880 grf: syscon@ff770000 {
881 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
882 reg = <0x0 0xff770000 0x0 0x1000>;
883
884 edp_phy: edp-phy {
885 compatible = "rockchip,rk3288-dp-phy";
886 clocks = <&cru SCLK_EDP_24M>;
887 clock-names = "24m";
888 #phy-cells = <0>;
889 status = "disabled";
890 };
891
892 io_domains: io-domains {
893 compatible = "rockchip,rk3288-io-voltage-domain";
894 status = "disabled";
895 };
896
897 usbphy: usbphy {
898 compatible = "rockchip,rk3288-usb-phy";
899 #address-cells = <1>;
900 #size-cells = <0>;
901 status = "disabled";
902
903 usbphy0: usb-phy@320 {
904 #phy-cells = <0>;
905 reg = <0x320>;
906 clocks = <&cru SCLK_OTGPHY0>;
907 clock-names = "phyclk";
908 #clock-cells = <0>;
909 resets = <&cru SRST_USBOTG_PHY>;
910 reset-names = "phy-reset";
911 };
912
913 usbphy1: usb-phy@334 {
914 #phy-cells = <0>;
915 reg = <0x334>;
916 clocks = <&cru SCLK_OTGPHY1>;
917 clock-names = "phyclk";
918 #clock-cells = <0>;
919 resets = <&cru SRST_USBHOST0_PHY>;
920 reset-names = "phy-reset";
921 };
922
923 usbphy2: usb-phy@348 {
924 #phy-cells = <0>;
925 reg = <0x348>;
926 clocks = <&cru SCLK_OTGPHY2>;
927 clock-names = "phyclk";
928 #clock-cells = <0>;
929 resets = <&cru SRST_USBHOST1_PHY>;
930 reset-names = "phy-reset";
931 };
932 };
933 };
934
935 wdt: watchdog@ff800000 {
936 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
937 reg = <0x0 0xff800000 0x0 0x100>;
938 clocks = <&cru PCLK_WDT>;
939 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
940 status = "disabled";
941 };
942
943 spdif: sound@ff88b0000 {
944 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
945 reg = <0x0 0xff8b0000 0x0 0x10000>;
946 #sound-dai-cells = <0>;
947 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>;
948 clock-names = "mclk", "hclk";
949 dmas = <&dmac_bus_s 3>;
950 dma-names = "tx";
951 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
952 pinctrl-names = "default";
953 pinctrl-0 = <&spdif_tx>;
954 rockchip,grf = <&grf>;
955 status = "disabled";
956 };
957
958 i2s: i2s@ff890000 {
959 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
960 reg = <0x0 0xff890000 0x0 0x10000>;
961 #sound-dai-cells = <0>;
962 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;
964 clock-names = "i2s_clk", "i2s_hclk";
965 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
966 dma-names = "tx", "rx";
967 pinctrl-names = "default";
968 pinctrl-0 = <&i2s0_bus>;
969 rockchip,playback-channels = <8>;
970 rockchip,capture-channels = <2>;
971 status = "disabled";
972 };
973
974 crypto: cypto-controller@ff8a0000 {
975 compatible = "rockchip,rk3288-crypto";
976 reg = <0x0 0xff8a0000 0x0 0x4000>;
977 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
979 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
980 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
981 resets = <&cru SRST_CRYPTO>;
982 reset-names = "crypto-rst";
983 status = "okay";
984 };
985
986 iep_mmu: iommu@ff900800 {
987 compatible = "rockchip,iommu";
988 reg = <0x0 0xff900800 0x0 0x40>;
989 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
990 interrupt-names = "iep_mmu";
991 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
992 clock-names = "aclk", "iface";
993 #iommu-cells = <0>;
994 status = "disabled";
995 };
996
997 isp_mmu: iommu@ff914000 {
998 compatible = "rockchip,iommu";
999 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1000 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1001 interrupt-names = "isp_mmu";
1002 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1003 clock-names = "aclk", "iface";
1004 #iommu-cells = <0>;
1005 rockchip,disable-mmu-reset;
1006 status = "disabled";
1007 };
1008
1009 rga: rga@ff920000 {
1010 compatible = "rockchip,rk3288-rga";
1011 reg = <0x0 0xff920000 0x0 0x180>;
1012 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1014 clock-names = "aclk", "hclk", "sclk";
1015 power-domains = <&power RK3288_PD_VIO>;
1016 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1017 reset-names = "core", "axi", "ahb";
1018 };
1019
1020 vopb: vop@ff930000 {
1021 compatible = "rockchip,rk3288-vop";
1022 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1023 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1025 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1026 power-domains = <&power RK3288_PD_VIO>;
1027 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1028 reset-names = "axi", "ahb", "dclk";
1029 iommus = <&vopb_mmu>;
1030 status = "disabled";
1031
1032 vopb_out: port {
1033 #address-cells = <1>;
1034 #size-cells = <0>;
1035
1036 vopb_out_hdmi: endpoint@0 {
1037 reg = <0>;
1038 remote-endpoint = <&hdmi_in_vopb>;
1039 };
1040
1041 vopb_out_edp: endpoint@1 {
1042 reg = <1>;
1043 remote-endpoint = <&edp_in_vopb>;
1044 };
1045
1046 vopb_out_mipi: endpoint@2 {
1047 reg = <2>;
1048 remote-endpoint = <&mipi_in_vopb>;
1049 };
1050
1051 vopb_out_lvds: endpoint@3 {
1052 reg = <3>;
1053 remote-endpoint = <&lvds_in_vopb>;
1054 };
1055 };
1056 };
1057
1058 vopb_mmu: iommu@ff930300 {
1059 compatible = "rockchip,iommu";
1060 reg = <0x0 0xff930300 0x0 0x100>;
1061 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1062 interrupt-names = "vopb_mmu";
1063 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1064 clock-names = "aclk", "iface";
1065 power-domains = <&power RK3288_PD_VIO>;
1066 #iommu-cells = <0>;
1067 status = "disabled";
1068 };
1069
1070 vopl: vop@ff940000 {
1071 compatible = "rockchip,rk3288-vop";
1072 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1073 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1075 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1076 power-domains = <&power RK3288_PD_VIO>;
1077 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1078 reset-names = "axi", "ahb", "dclk";
1079 iommus = <&vopl_mmu>;
1080 status = "disabled";
1081
1082 vopl_out: port {
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1085
1086 vopl_out_hdmi: endpoint@0 {
1087 reg = <0>;
1088 remote-endpoint = <&hdmi_in_vopl>;
1089 };
1090
1091 vopl_out_edp: endpoint@1 {
1092 reg = <1>;
1093 remote-endpoint = <&edp_in_vopl>;
1094 };
1095
1096 vopl_out_mipi: endpoint@2 {
1097 reg = <2>;
1098 remote-endpoint = <&mipi_in_vopl>;
1099 };
1100
1101 vopl_out_lvds: endpoint@3 {
1102 reg = <3>;
1103 remote-endpoint = <&lvds_in_vopl>;
1104 };
1105 };
1106 };
1107
1108 vopl_mmu: iommu@ff940300 {
1109 compatible = "rockchip,iommu";
1110 reg = <0x0 0xff940300 0x0 0x100>;
1111 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1112 interrupt-names = "vopl_mmu";
1113 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1114 clock-names = "aclk", "iface";
1115 power-domains = <&power RK3288_PD_VIO>;
1116 #iommu-cells = <0>;
1117 status = "disabled";
1118 };
1119
1120 mipi_dsi: mipi@ff960000 {
1121 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1122 reg = <0x0 0xff960000 0x0 0x4000>;
1123 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1125 clock-names = "ref", "pclk";
1126 power-domains = <&power RK3288_PD_VIO>;
1127 rockchip,grf = <&grf>;
1128 status = "disabled";
1129
1130 ports {
1131 mipi_in: port {
1132 #address-cells = <1>;
1133 #size-cells = <0>;
1134 mipi_in_vopb: endpoint@0 {
1135 reg = <0>;
1136 remote-endpoint = <&vopb_out_mipi>;
1137 };
1138 mipi_in_vopl: endpoint@1 {
1139 reg = <1>;
1140 remote-endpoint = <&vopl_out_mipi>;
1141 };
1142 };
1143 };
1144 };
1145
1146 lvds: lvds@ff96c000 {
1147 compatible = "rockchip,rk3288-lvds";
1148 reg = <0x0 0xff96c000 0x0 0x4000>;
1149 clocks = <&cru PCLK_LVDS_PHY>;
1150 clock-names = "pclk_lvds";
1151 pinctrl-names = "lcdc";
1152 pinctrl-0 = <&lcdc_ctl>;
1153 power-domains = <&power RK3288_PD_VIO>;
1154 rockchip,grf = <&grf>;
1155 status = "disabled";
1156
1157 ports {
1158 #address-cells = <1>;
1159 #size-cells = <0>;
1160
1161 lvds_in: port@0 {
1162 reg = <0>;
1163
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1166
1167 lvds_in_vopb: endpoint@0 {
1168 reg = <0>;
1169 remote-endpoint = <&vopb_out_lvds>;
1170 };
1171 lvds_in_vopl: endpoint@1 {
1172 reg = <1>;
1173 remote-endpoint = <&vopl_out_lvds>;
1174 };
1175 };
1176 };
1177 };
1178
1179 edp: dp@ff970000 {
1180 compatible = "rockchip,rk3288-dp";
1181 reg = <0x0 0xff970000 0x0 0x4000>;
1182 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1184 clock-names = "dp", "pclk";
1185 phys = <&edp_phy>;
1186 phy-names = "dp";
1187 resets = <&cru SRST_EDP>;
1188 reset-names = "dp";
1189 rockchip,grf = <&grf>;
1190 status = "disabled";
1191
1192 ports {
1193 #address-cells = <1>;
1194 #size-cells = <0>;
1195 edp_in: port@0 {
1196 reg = <0>;
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 edp_in_vopb: endpoint@0 {
1200 reg = <0>;
1201 remote-endpoint = <&vopb_out_edp>;
1202 };
1203 edp_in_vopl: endpoint@1 {
1204 reg = <1>;
1205 remote-endpoint = <&vopl_out_edp>;
1206 };
1207 };
1208 };
1209 };
1210
1211 hdmi: hdmi@ff980000 {
1212 compatible = "rockchip,rk3288-dw-hdmi";
1213 reg = <0x0 0xff980000 0x0 0x20000>;
1214 reg-io-width = <4>;
1215 #sound-dai-cells = <0>;
1216 rockchip,grf = <&grf>;
1217 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1218 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1219 clock-names = "iahb", "isfr", "cec";
1220 power-domains = <&power RK3288_PD_VIO>;
1221 status = "disabled";
1222
1223 ports {
1224 hdmi_in: port {
1225 #address-cells = <1>;
1226 #size-cells = <0>;
1227 hdmi_in_vopb: endpoint@0 {
1228 reg = <0>;
1229 remote-endpoint = <&vopb_out_hdmi>;
1230 };
1231 hdmi_in_vopl: endpoint@1 {
1232 reg = <1>;
1233 remote-endpoint = <&vopl_out_hdmi>;
1234 };
1235 };
1236 };
1237 };
1238
1239 vpu: video-codec@ff9a0000 {
1240 compatible = "rockchip,rk3288-vpu";
1241 reg = <0x0 0xff9a0000 0x0 0x800>;
1242 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1244 interrupt-names = "vepu", "vdpu";
1245 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1246 clock-names = "aclk", "hclk";
1247 iommus = <&vpu_mmu>;
1248 power-domains = <&power RK3288_PD_VIDEO>;
1249 };
1250
1251 vpu_mmu: iommu@ff9a0800 {
1252 compatible = "rockchip,iommu";
1253 reg = <0x0 0xff9a0800 0x0 0x100>;
1254 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1255 interrupt-names = "vpu_mmu";
1256 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1257 clock-names = "aclk", "iface";
1258 #iommu-cells = <0>;
1259 power-domains = <&power RK3288_PD_VIDEO>;
1260 };
1261
1262 hevc_mmu: iommu@ff9c0440 {
1263 compatible = "rockchip,iommu";
1264 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1265 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1266 interrupt-names = "hevc_mmu";
1267 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1268 clock-names = "aclk", "iface";
1269 #iommu-cells = <0>;
1270 status = "disabled";
1271 };
1272
1273 gpu: gpu@ffa30000 {
1274 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1275 reg = <0x0 0xffa30000 0x0 0x10000>;
1276 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1279 interrupt-names = "job", "mmu", "gpu";
1280 clocks = <&cru ACLK_GPU>;
1281 operating-points-v2 = <&gpu_opp_table>;
1282 #cooling-cells = <2>; /* min followed by max */
1283 power-domains = <&power RK3288_PD_GPU>;
1284 status = "disabled";
1285 };
1286
1287 gpu_opp_table: gpu-opp-table {
1288 compatible = "operating-points-v2";
1289
1290 opp-100000000 {
1291 opp-hz = /bits/ 64 <100000000>;
1292 opp-microvolt = <950000>;
1293 };
1294 opp-200000000 {
1295 opp-hz = /bits/ 64 <200000000>;
1296 opp-microvolt = <950000>;
1297 };
1298 opp-300000000 {
1299 opp-hz = /bits/ 64 <300000000>;
1300 opp-microvolt = <1000000>;
1301 };
1302 opp-400000000 {
1303 opp-hz = /bits/ 64 <400000000>;
1304 opp-microvolt = <1100000>;
1305 };
1306 opp-600000000 {
1307 opp-hz = /bits/ 64 <600000000>;
1308 opp-microvolt = <1250000>;
1309 };
1310 };
1311
1312 qos_gpu_r: qos@ffaa0000 {
1313 compatible = "rockchip,rk3288-qos", "syscon";
1314 reg = <0x0 0xffaa0000 0x0 0x20>;
1315 };
1316
1317 qos_gpu_w: qos@ffaa0080 {
1318 compatible = "rockchip,rk3288-qos", "syscon";
1319 reg = <0x0 0xffaa0080 0x0 0x20>;
1320 };
1321
1322 qos_vio1_vop: qos@ffad0000 {
1323 compatible = "rockchip,rk3288-qos", "syscon";
1324 reg = <0x0 0xffad0000 0x0 0x20>;
1325 };
1326
1327 qos_vio1_isp_w0: qos@ffad0100 {
1328 compatible = "rockchip,rk3288-qos", "syscon";
1329 reg = <0x0 0xffad0100 0x0 0x20>;
1330 };
1331
1332 qos_vio1_isp_w1: qos@ffad0180 {
1333 compatible = "rockchip,rk3288-qos", "syscon";
1334 reg = <0x0 0xffad0180 0x0 0x20>;
1335 };
1336
1337 qos_vio0_vop: qos@ffad0400 {
1338 compatible = "rockchip,rk3288-qos", "syscon";
1339 reg = <0x0 0xffad0400 0x0 0x20>;
1340 };
1341
1342 qos_vio0_vip: qos@ffad0480 {
1343 compatible = "rockchip,rk3288-qos", "syscon";
1344 reg = <0x0 0xffad0480 0x0 0x20>;
1345 };
1346
1347 qos_vio0_iep: qos@ffad0500 {
1348 compatible = "rockchip,rk3288-qos", "syscon";
1349 reg = <0x0 0xffad0500 0x0 0x20>;
1350 };
1351
1352 qos_vio2_rga_r: qos@ffad0800 {
1353 compatible = "rockchip,rk3288-qos", "syscon";
1354 reg = <0x0 0xffad0800 0x0 0x20>;
1355 };
1356
1357 qos_vio2_rga_w: qos@ffad0880 {
1358 compatible = "rockchip,rk3288-qos", "syscon";
1359 reg = <0x0 0xffad0880 0x0 0x20>;
1360 };
1361
1362 qos_vio1_isp_r: qos@ffad0900 {
1363 compatible = "rockchip,rk3288-qos", "syscon";
1364 reg = <0x0 0xffad0900 0x0 0x20>;
1365 };
1366
1367 qos_video: qos@ffae0000 {
1368 compatible = "rockchip,rk3288-qos", "syscon";
1369 reg = <0x0 0xffae0000 0x0 0x20>;
1370 };
1371
1372 qos_hevc_r: qos@ffaf0000 {
1373 compatible = "rockchip,rk3288-qos", "syscon";
1374 reg = <0x0 0xffaf0000 0x0 0x20>;
1375 };
1376
1377 qos_hevc_w: qos@ffaf0080 {
1378 compatible = "rockchip,rk3288-qos", "syscon";
1379 reg = <0x0 0xffaf0080 0x0 0x20>;
1380 };
1381
1382 dmac_bus_s: dma-controller@ffb20000 {
1383 compatible = "arm,pl330", "arm,primecell";
1384 reg = <0x0 0xffb20000 0x0 0x4000>;
1385 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1387 #dma-cells = <1>;
1388 arm,pl330-broken-no-flushp;
1389 arm,pl330-periph-burst;
1390 clocks = <&cru ACLK_DMAC1>;
1391 clock-names = "apb_pclk";
1392 };
1393
1394 efuse: efuse@ffb40000 {
1395 compatible = "rockchip,rk3288-efuse";
1396 reg = <0x0 0xffb40000 0x0 0x20>;
1397 #address-cells = <1>;
1398 #size-cells = <1>;
1399 clocks = <&cru PCLK_EFUSE256>;
1400 clock-names = "pclk_efuse";
1401
1402 cpu_id: cpu-id@7 {
1403 reg = <0x07 0x10>;
1404 };
1405 cpu_leakage: cpu_leakage@17 {
1406 reg = <0x17 0x1>;
1407 };
1408 };
1409
1410 gic: interrupt-controller@ffc01000 {
1411 compatible = "arm,gic-400";
1412 interrupt-controller;
1413 #interrupt-cells = <3>;
1414 #address-cells = <0>;
1415
1416 reg = <0x0 0xffc01000 0x0 0x1000>,
1417 <0x0 0xffc02000 0x0 0x2000>,
1418 <0x0 0xffc04000 0x0 0x2000>,
1419 <0x0 0xffc06000 0x0 0x2000>;
1420 interrupts = <GIC_PPI 9 0xf04>;
1421 };
1422
1423 pinctrl: pinctrl {
1424 compatible = "rockchip,rk3288-pinctrl";
1425 rockchip,grf = <&grf>;
1426 rockchip,pmu = <&pmu>;
1427 #address-cells = <2>;
1428 #size-cells = <2>;
1429 ranges;
1430
1431 gpio0: gpio0@ff750000 {
1432 compatible = "rockchip,gpio-bank";
1433 reg = <0x0 0xff750000 0x0 0x100>;
1434 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1435 clocks = <&cru PCLK_GPIO0>;
1436
1437 gpio-controller;
1438 #gpio-cells = <2>;
1439
1440 interrupt-controller;
1441 #interrupt-cells = <2>;
1442 };
1443
1444 gpio1: gpio1@ff780000 {
1445 compatible = "rockchip,gpio-bank";
1446 reg = <0x0 0xff780000 0x0 0x100>;
1447 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1448 clocks = <&cru PCLK_GPIO1>;
1449
1450 gpio-controller;
1451 #gpio-cells = <2>;
1452
1453 interrupt-controller;
1454 #interrupt-cells = <2>;
1455 };
1456
1457 gpio2: gpio2@ff790000 {
1458 compatible = "rockchip,gpio-bank";
1459 reg = <0x0 0xff790000 0x0 0x100>;
1460 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1461 clocks = <&cru PCLK_GPIO2>;
1462
1463 gpio-controller;
1464 #gpio-cells = <2>;
1465
1466 interrupt-controller;
1467 #interrupt-cells = <2>;
1468 };
1469
1470 gpio3: gpio3@ff7a0000 {
1471 compatible = "rockchip,gpio-bank";
1472 reg = <0x0 0xff7a0000 0x0 0x100>;
1473 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1474 clocks = <&cru PCLK_GPIO3>;
1475
1476 gpio-controller;
1477 #gpio-cells = <2>;
1478
1479 interrupt-controller;
1480 #interrupt-cells = <2>;
1481 };
1482
1483 gpio4: gpio4@ff7b0000 {
1484 compatible = "rockchip,gpio-bank";
1485 reg = <0x0 0xff7b0000 0x0 0x100>;
1486 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1487 clocks = <&cru PCLK_GPIO4>;
1488
1489 gpio-controller;
1490 #gpio-cells = <2>;
1491
1492 interrupt-controller;
1493 #interrupt-cells = <2>;
1494 };
1495
1496 gpio5: gpio5@ff7c0000 {
1497 compatible = "rockchip,gpio-bank";
1498 reg = <0x0 0xff7c0000 0x0 0x100>;
1499 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1500 clocks = <&cru PCLK_GPIO5>;
1501
1502 gpio-controller;
1503 #gpio-cells = <2>;
1504
1505 interrupt-controller;
1506 #interrupt-cells = <2>;
1507 };
1508
1509 gpio6: gpio6@ff7d0000 {
1510 compatible = "rockchip,gpio-bank";
1511 reg = <0x0 0xff7d0000 0x0 0x100>;
1512 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1513 clocks = <&cru PCLK_GPIO6>;
1514
1515 gpio-controller;
1516 #gpio-cells = <2>;
1517
1518 interrupt-controller;
1519 #interrupt-cells = <2>;
1520 };
1521
1522 gpio7: gpio7@ff7e0000 {
1523 compatible = "rockchip,gpio-bank";
1524 reg = <0x0 0xff7e0000 0x0 0x100>;
1525 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1526 clocks = <&cru PCLK_GPIO7>;
1527
1528 gpio-controller;
1529 #gpio-cells = <2>;
1530
1531 interrupt-controller;
1532 #interrupt-cells = <2>;
1533 };
1534
1535 gpio8: gpio8@ff7f0000 {
1536 compatible = "rockchip,gpio-bank";
1537 reg = <0x0 0xff7f0000 0x0 0x100>;
1538 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1539 clocks = <&cru PCLK_GPIO8>;
1540
1541 gpio-controller;
1542 #gpio-cells = <2>;
1543
1544 interrupt-controller;
1545 #interrupt-cells = <2>;
1546 };
1547
1548 hdmi {
1549 hdmi_cec_c0: hdmi-cec-c0 {
1550 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1551 };
1552
1553 hdmi_cec_c7: hdmi-cec-c7 {
1554 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1555 };
1556
1557 hdmi_ddc: hdmi-ddc {
1558 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1559 <7 RK_PC4 2 &pcfg_pull_none>;
1560 };
1561
1562 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1563 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>,
1564 <7 RK_PC4 2 &pcfg_pull_none>;
1565 };
1566 };
1567
1568 pcfg_output_low: pcfg-output-low {
1569 output-low;
1570 };
1571
1572 pcfg_pull_up: pcfg-pull-up {
1573 bias-pull-up;
1574 };
1575
1576 pcfg_pull_down: pcfg-pull-down {
1577 bias-pull-down;
1578 };
1579
1580 pcfg_pull_none: pcfg-pull-none {
1581 bias-disable;
1582 };
1583
1584 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1585 bias-disable;
1586 drive-strength = <12>;
1587 };
1588
1589 suspend {
1590 global_pwroff: global-pwroff {
1591 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1592 };
1593
1594 ddrio_pwroff: ddrio-pwroff {
1595 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1596 };
1597
1598 ddr0_retention: ddr0-retention {
1599 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1600 };
1601
1602 ddr1_retention: ddr1-retention {
1603 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1604 };
1605 };
1606
1607 edp {
1608 edp_hpd: edp-hpd {
1609 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1610 };
1611 };
1612
1613 i2c0 {
1614 i2c0_xfer: i2c0-xfer {
1615 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1616 <0 RK_PC0 1 &pcfg_pull_none>;
1617 };
1618 };
1619
1620 i2c1 {
1621 i2c1_xfer: i2c1-xfer {
1622 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1623 <8 RK_PA5 1 &pcfg_pull_none>;
1624 };
1625 };
1626
1627 i2c2 {
1628 i2c2_xfer: i2c2-xfer {
1629 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1630 <6 RK_PB2 1 &pcfg_pull_none>;
1631 };
1632 };
1633
1634 i2c3 {
1635 i2c3_xfer: i2c3-xfer {
1636 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1637 <2 RK_PC1 1 &pcfg_pull_none>;
1638 };
1639 };
1640
1641 i2c4 {
1642 i2c4_xfer: i2c4-xfer {
1643 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1644 <7 RK_PC2 1 &pcfg_pull_none>;
1645 };
1646 };
1647
1648 i2c5 {
1649 i2c5_xfer: i2c5-xfer {
1650 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1651 <7 RK_PC4 1 &pcfg_pull_none>;
1652 };
1653 };
1654
1655 i2s0 {
1656 i2s0_bus: i2s0-bus {
1657 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1658 <6 RK_PA1 1 &pcfg_pull_none>,
1659 <6 RK_PA2 1 &pcfg_pull_none>,
1660 <6 RK_PA3 1 &pcfg_pull_none>,
1661 <6 RK_PA4 1 &pcfg_pull_none>,
1662 <6 RK_PB0 1 &pcfg_pull_none>;
1663 };
1664 };
1665
1666 lcdc {
1667 lcdc_ctl: lcdc-ctl {
1668 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1669 <1 RK_PD1 1 &pcfg_pull_none>,
1670 <1 RK_PD2 1 &pcfg_pull_none>,
1671 <1 RK_PD3 1 &pcfg_pull_none>;
1672 };
1673 };
1674
1675 sdmmc {
1676 sdmmc_clk: sdmmc-clk {
1677 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1678 };
1679
1680 sdmmc_cmd: sdmmc-cmd {
1681 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1682 };
1683
1684 sdmmc_cd: sdmmc-cd {
1685 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1686 };
1687
1688 sdmmc_bus1: sdmmc-bus1 {
1689 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1690 };
1691
1692 sdmmc_bus4: sdmmc-bus4 {
1693 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1694 <6 RK_PC1 1 &pcfg_pull_up>,
1695 <6 RK_PC2 1 &pcfg_pull_up>,
1696 <6 RK_PC3 1 &pcfg_pull_up>;
1697 };
1698 };
1699
1700 sdio0 {
1701 sdio0_bus1: sdio0-bus1 {
1702 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1703 };
1704
1705 sdio0_bus4: sdio0-bus4 {
1706 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1707 <4 RK_PC5 1 &pcfg_pull_up>,
1708 <4 RK_PC6 1 &pcfg_pull_up>,
1709 <4 RK_PC7 1 &pcfg_pull_up>;
1710 };
1711
1712 sdio0_cmd: sdio0-cmd {
1713 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1714 };
1715
1716 sdio0_clk: sdio0-clk {
1717 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1718 };
1719
1720 sdio0_cd: sdio0-cd {
1721 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1722 };
1723
1724 sdio0_wp: sdio0-wp {
1725 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1726 };
1727
1728 sdio0_pwr: sdio0-pwr {
1729 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1730 };
1731
1732 sdio0_bkpwr: sdio0-bkpwr {
1733 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1734 };
1735
1736 sdio0_int: sdio0-int {
1737 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1738 };
1739 };
1740
1741 sdio1 {
1742 sdio1_bus1: sdio1-bus1 {
1743 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1744 };
1745
1746 sdio1_bus4: sdio1-bus4 {
1747 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1748 <3 RK_PD1 4 &pcfg_pull_up>,
1749 <3 RK_PD2 4 &pcfg_pull_up>,
1750 <3 RK_PD3 4 &pcfg_pull_up>;
1751 };
1752
1753 sdio1_cd: sdio1-cd {
1754 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1755 };
1756
1757 sdio1_wp: sdio1-wp {
1758 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1759 };
1760
1761 sdio1_bkpwr: sdio1-bkpwr {
1762 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1763 };
1764
1765 sdio1_int: sdio1-int {
1766 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1767 };
1768
1769 sdio1_cmd: sdio1-cmd {
1770 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1771 };
1772
1773 sdio1_clk: sdio1-clk {
1774 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1775 };
1776
1777 sdio1_pwr: sdio1-pwr {
1778 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1779 };
1780 };
1781
1782 emmc {
1783 emmc_clk: emmc-clk {
1784 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1785 };
1786
1787 emmc_cmd: emmc-cmd {
1788 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1789 };
1790
1791 emmc_pwr: emmc-pwr {
1792 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1793 };
1794
1795 emmc_bus1: emmc-bus1 {
1796 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1797 };
1798
1799 emmc_bus4: emmc-bus4 {
1800 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1801 <3 RK_PA1 2 &pcfg_pull_up>,
1802 <3 RK_PA2 2 &pcfg_pull_up>,
1803 <3 RK_PA3 2 &pcfg_pull_up>;
1804 };
1805
1806 emmc_bus8: emmc-bus8 {
1807 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1808 <3 RK_PA1 2 &pcfg_pull_up>,
1809 <3 RK_PA2 2 &pcfg_pull_up>,
1810 <3 RK_PA3 2 &pcfg_pull_up>,
1811 <3 RK_PA4 2 &pcfg_pull_up>,
1812 <3 RK_PA5 2 &pcfg_pull_up>,
1813 <3 RK_PA6 2 &pcfg_pull_up>,
1814 <3 RK_PA7 2 &pcfg_pull_up>;
1815 };
1816 };
1817
1818 spi0 {
1819 spi0_clk: spi0-clk {
1820 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1821 };
1822 spi0_cs0: spi0-cs0 {
1823 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1824 };
1825 spi0_tx: spi0-tx {
1826 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1827 };
1828 spi0_rx: spi0-rx {
1829 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1830 };
1831 spi0_cs1: spi0-cs1 {
1832 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1833 };
1834 };
1835 spi1 {
1836 spi1_clk: spi1-clk {
1837 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1838 };
1839 spi1_cs0: spi1-cs0 {
1840 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1841 };
1842 spi1_rx: spi1-rx {
1843 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1844 };
1845 spi1_tx: spi1-tx {
1846 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1847 };
1848 };
1849
1850 spi2 {
1851 spi2_cs1: spi2-cs1 {
1852 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1853 };
1854 spi2_clk: spi2-clk {
1855 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1856 };
1857 spi2_cs0: spi2-cs0 {
1858 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1859 };
1860 spi2_rx: spi2-rx {
1861 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1862 };
1863 spi2_tx: spi2-tx {
1864 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1865 };
1866 };
1867
1868 uart0 {
1869 uart0_xfer: uart0-xfer {
1870 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1871 <4 RK_PC1 1 &pcfg_pull_none>;
1872 };
1873
1874 uart0_cts: uart0-cts {
1875 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1876 };
1877
1878 uart0_rts: uart0-rts {
1879 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1880 };
1881 };
1882
1883 uart1 {
1884 uart1_xfer: uart1-xfer {
1885 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1886 <5 RK_PB1 1 &pcfg_pull_none>;
1887 };
1888
1889 uart1_cts: uart1-cts {
1890 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1891 };
1892
1893 uart1_rts: uart1-rts {
1894 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1895 };
1896 };
1897
1898 uart2 {
1899 uart2_xfer: uart2-xfer {
1900 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1901 <7 RK_PC7 1 &pcfg_pull_none>;
1902 };
1903 /* no rts / cts for uart2 */
1904 };
1905
1906 uart3 {
1907 uart3_xfer: uart3-xfer {
1908 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1909 <7 RK_PB0 1 &pcfg_pull_none>;
1910 };
1911
1912 uart3_cts: uart3-cts {
1913 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1914 };
1915
1916 uart3_rts: uart3-rts {
1917 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1918 };
1919 };
1920
1921 uart4 {
1922 uart4_xfer: uart4-xfer {
1923 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1924 <5 RK_PB6 3 &pcfg_pull_none>;
1925 };
1926
1927 uart4_cts: uart4-cts {
1928 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1929 };
1930
1931 uart4_rts: uart4-rts {
1932 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1933 };
1934 };
1935
1936 tsadc {
1937 otp_pin: otp-pin {
1938 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1939 };
1940
1941 otp_out: otp-out {
1942 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1943 };
1944 };
1945
1946 pwm0 {
1947 pwm0_pin: pwm0-pin {
1948 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1949 };
1950 };
1951
1952 pwm1 {
1953 pwm1_pin: pwm1-pin {
1954 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1955 };
1956 };
1957
1958 pwm2 {
1959 pwm2_pin: pwm2-pin {
1960 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1961 };
1962 };
1963
1964 pwm3 {
1965 pwm3_pin: pwm3-pin {
1966 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
1967 };
1968 };
1969
1970 gmac {
1971 rgmii_pins: rgmii-pins {
1972 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1973 <3 RK_PD7 3 &pcfg_pull_none>,
1974 <3 RK_PD2 3 &pcfg_pull_none>,
1975 <3 RK_PD3 3 &pcfg_pull_none>,
1976 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
1977 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
1978 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
1979 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
1980 <4 RK_PA0 3 &pcfg_pull_none>,
1981 <4 RK_PA5 3 &pcfg_pull_none>,
1982 <4 RK_PA6 3 &pcfg_pull_none>,
1983 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
1984 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
1985 <4 RK_PA1 3 &pcfg_pull_none>,
1986 <4 RK_PA3 3 &pcfg_pull_none>;
1987 };
1988
1989 rmii_pins: rmii-pins {
1990 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1991 <3 RK_PD7 3 &pcfg_pull_none>,
1992 <3 RK_PD4 3 &pcfg_pull_none>,
1993 <3 RK_PD5 3 &pcfg_pull_none>,
1994 <4 RK_PA0 3 &pcfg_pull_none>,
1995 <4 RK_PA5 3 &pcfg_pull_none>,
1996 <4 RK_PA4 3 &pcfg_pull_none>,
1997 <4 RK_PA1 3 &pcfg_pull_none>,
1998 <4 RK_PA2 3 &pcfg_pull_none>,
1999 <4 RK_PA3 3 &pcfg_pull_none>;
2000 };
2001 };
2002
2003 spdif {
2004 spdif_tx: spdif-tx {
2005 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
2006 };
2007 };
2008 };
2009};