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1/*
2 * Device Tree Source for Renesas r8a7779
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <dt-bindings/clock/r8a7779-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/power/r8a7779-sysc.h>
16
17/ {
18 compatible = "renesas,r8a7779";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a9";
30 reg = <0>;
31 clock-frequency = <1000000000>;
32 clocks = <&cpg_clocks R8A7779_CLK_Z>;
33 };
34 cpu@1 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a9";
37 reg = <1>;
38 clock-frequency = <1000000000>;
39 clocks = <&cpg_clocks R8A7779_CLK_Z>;
40 power-domains = <&sysc R8A7779_PD_ARM1>;
41 };
42 cpu@2 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a9";
45 reg = <2>;
46 clock-frequency = <1000000000>;
47 clocks = <&cpg_clocks R8A7779_CLK_Z>;
48 power-domains = <&sysc R8A7779_PD_ARM2>;
49 };
50 cpu@3 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a9";
53 reg = <3>;
54 clock-frequency = <1000000000>;
55 clocks = <&cpg_clocks R8A7779_CLK_Z>;
56 power-domains = <&sysc R8A7779_PD_ARM3>;
57 };
58 };
59
60 aliases {
61 spi0 = &hspi0;
62 spi1 = &hspi1;
63 spi2 = &hspi2;
64 };
65
66 gic: interrupt-controller@f0001000 {
67 compatible = "arm,cortex-a9-gic";
68 #interrupt-cells = <3>;
69 interrupt-controller;
70 reg = <0xf0001000 0x1000>,
71 <0xf0000100 0x100>;
72 };
73
74 timer@f0000600 {
75 compatible = "arm,cortex-a9-twd-timer";
76 reg = <0xf0000600 0x20>;
77 interrupts = <GIC_PPI 13
78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
79 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
80 };
81
82 gpio0: gpio@ffc40000 {
83 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
84 reg = <0xffc40000 0x2c>;
85 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
86 #gpio-cells = <2>;
87 gpio-controller;
88 gpio-ranges = <&pfc 0 0 32>;
89 #interrupt-cells = <2>;
90 interrupt-controller;
91 };
92
93 gpio1: gpio@ffc41000 {
94 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
95 reg = <0xffc41000 0x2c>;
96 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
97 #gpio-cells = <2>;
98 gpio-controller;
99 gpio-ranges = <&pfc 0 32 32>;
100 #interrupt-cells = <2>;
101 interrupt-controller;
102 };
103
104 gpio2: gpio@ffc42000 {
105 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
106 reg = <0xffc42000 0x2c>;
107 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
108 #gpio-cells = <2>;
109 gpio-controller;
110 gpio-ranges = <&pfc 0 64 32>;
111 #interrupt-cells = <2>;
112 interrupt-controller;
113 };
114
115 gpio3: gpio@ffc43000 {
116 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
117 reg = <0xffc43000 0x2c>;
118 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
119 #gpio-cells = <2>;
120 gpio-controller;
121 gpio-ranges = <&pfc 0 96 32>;
122 #interrupt-cells = <2>;
123 interrupt-controller;
124 };
125
126 gpio4: gpio@ffc44000 {
127 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
128 reg = <0xffc44000 0x2c>;
129 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
130 #gpio-cells = <2>;
131 gpio-controller;
132 gpio-ranges = <&pfc 0 128 32>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
135 };
136
137 gpio5: gpio@ffc45000 {
138 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
139 reg = <0xffc45000 0x2c>;
140 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
141 #gpio-cells = <2>;
142 gpio-controller;
143 gpio-ranges = <&pfc 0 160 32>;
144 #interrupt-cells = <2>;
145 interrupt-controller;
146 };
147
148 gpio6: gpio@ffc46000 {
149 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
150 reg = <0xffc46000 0x2c>;
151 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
152 #gpio-cells = <2>;
153 gpio-controller;
154 gpio-ranges = <&pfc 0 192 9>;
155 #interrupt-cells = <2>;
156 interrupt-controller;
157 };
158
159 irqpin0: interrupt-controller@fe78001c {
160 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
161 #interrupt-cells = <2>;
162 status = "disabled";
163 interrupt-controller;
164 reg = <0xfe78001c 4>,
165 <0xfe780010 4>,
166 <0xfe780024 4>,
167 <0xfe780044 4>,
168 <0xfe780064 4>,
169 <0xfe780000 4>;
170 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
171 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
172 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
173 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
174 sense-bitfield-width = <2>;
175 };
176
177 i2c0: i2c@ffc70000 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
181 reg = <0xffc70000 0x1000>;
182 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
184 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
185 status = "disabled";
186 };
187
188 i2c1: i2c@ffc71000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
192 reg = <0xffc71000 0x1000>;
193 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
195 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
196 status = "disabled";
197 };
198
199 i2c2: i2c@ffc72000 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
203 reg = <0xffc72000 0x1000>;
204 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
206 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
207 status = "disabled";
208 };
209
210 i2c3: i2c@ffc73000 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
214 reg = <0xffc73000 0x1000>;
215 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
217 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
218 status = "disabled";
219 };
220
221 scif0: serial@ffe40000 {
222 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
223 "renesas,scif";
224 reg = <0xffe40000 0x100>;
225 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
227 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
228 clock-names = "fck", "brg_int", "scif_clk";
229 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
230 status = "disabled";
231 };
232
233 scif1: serial@ffe41000 {
234 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
235 "renesas,scif";
236 reg = <0xffe41000 0x100>;
237 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
239 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
240 clock-names = "fck", "brg_int", "scif_clk";
241 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
242 status = "disabled";
243 };
244
245 scif2: serial@ffe42000 {
246 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
247 "renesas,scif";
248 reg = <0xffe42000 0x100>;
249 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
251 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
252 clock-names = "fck", "brg_int", "scif_clk";
253 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
254 status = "disabled";
255 };
256
257 scif3: serial@ffe43000 {
258 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
259 "renesas,scif";
260 reg = <0xffe43000 0x100>;
261 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
263 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
264 clock-names = "fck", "brg_int", "scif_clk";
265 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
266 status = "disabled";
267 };
268
269 scif4: serial@ffe44000 {
270 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
271 "renesas,scif";
272 reg = <0xffe44000 0x100>;
273 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
275 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
276 clock-names = "fck", "brg_int", "scif_clk";
277 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
278 status = "disabled";
279 };
280
281 scif5: serial@ffe45000 {
282 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
283 "renesas,scif";
284 reg = <0xffe45000 0x100>;
285 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
287 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
288 clock-names = "fck", "brg_int", "scif_clk";
289 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
290 status = "disabled";
291 };
292
293 pfc: pin-controller@fffc0000 {
294 compatible = "renesas,pfc-r8a7779";
295 reg = <0xfffc0000 0x23c>;
296 };
297
298 thermal@ffc48000 {
299 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
300 reg = <0xffc48000 0x38>;
301 };
302
303 tmu0: timer@ffd80000 {
304 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
305 reg = <0xffd80000 0x30>;
306 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
310 clock-names = "fck";
311 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
312
313 #renesas,channels = <3>;
314
315 status = "disabled";
316 };
317
318 tmu1: timer@ffd81000 {
319 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
320 reg = <0xffd81000 0x30>;
321 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
325 clock-names = "fck";
326 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
327
328 #renesas,channels = <3>;
329
330 status = "disabled";
331 };
332
333 tmu2: timer@ffd82000 {
334 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
335 reg = <0xffd82000 0x30>;
336 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
340 clock-names = "fck";
341 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
342
343 #renesas,channels = <3>;
344
345 status = "disabled";
346 };
347
348 sata: sata@fc600000 {
349 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
350 reg = <0xfc600000 0x2000>;
351 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
353 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
354 status = "disabled";
355 };
356
357 sdhi0: sd@ffe4c000 {
358 compatible = "renesas,sdhi-r8a7779",
359 "renesas,rcar-gen1-sdhi";
360 reg = <0xffe4c000 0x100>;
361 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
363 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
364 status = "disabled";
365 };
366
367 sdhi1: sd@ffe4d000 {
368 compatible = "renesas,sdhi-r8a7779",
369 "renesas,rcar-gen1-sdhi";
370 reg = <0xffe4d000 0x100>;
371 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
373 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
374 status = "disabled";
375 };
376
377 sdhi2: sd@ffe4e000 {
378 compatible = "renesas,sdhi-r8a7779",
379 "renesas,rcar-gen1-sdhi";
380 reg = <0xffe4e000 0x100>;
381 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
383 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
384 status = "disabled";
385 };
386
387 sdhi3: sd@ffe4f000 {
388 compatible = "renesas,sdhi-r8a7779",
389 "renesas,rcar-gen1-sdhi";
390 reg = <0xffe4f000 0x100>;
391 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
393 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
394 status = "disabled";
395 };
396
397 hspi0: spi@fffc7000 {
398 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
399 reg = <0xfffc7000 0x18>;
400 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
401 #address-cells = <1>;
402 #size-cells = <0>;
403 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
404 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
405 status = "disabled";
406 };
407
408 hspi1: spi@fffc8000 {
409 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
410 reg = <0xfffc8000 0x18>;
411 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
412 #address-cells = <1>;
413 #size-cells = <0>;
414 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
415 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
416 status = "disabled";
417 };
418
419 hspi2: spi@fffc6000 {
420 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
421 reg = <0xfffc6000 0x18>;
422 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
423 #address-cells = <1>;
424 #size-cells = <0>;
425 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
426 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
427 status = "disabled";
428 };
429
430 du: display@fff80000 {
431 compatible = "renesas,du-r8a7779";
432 reg = <0xfff80000 0x40000>;
433 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&mstp1_clks R8A7779_CLK_DU>;
435 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
436 status = "disabled";
437
438 ports {
439 #address-cells = <1>;
440 #size-cells = <0>;
441
442 port@0 {
443 reg = <0>;
444 du_out_rgb0: endpoint {
445 };
446 };
447 port@1 {
448 reg = <1>;
449 du_out_rgb1: endpoint {
450 };
451 };
452 };
453 };
454
455 clocks {
456 #address-cells = <1>;
457 #size-cells = <1>;
458 ranges;
459
460 /* External root clock */
461 extal_clk: extal {
462 compatible = "fixed-clock";
463 #clock-cells = <0>;
464 /* This value must be overriden by the board. */
465 clock-frequency = <0>;
466 };
467
468 /* External SCIF clock */
469 scif_clk: scif {
470 compatible = "fixed-clock";
471 #clock-cells = <0>;
472 /* This value must be overridden by the board. */
473 clock-frequency = <0>;
474 };
475
476 /* Special CPG clocks */
477 cpg_clocks: clocks@ffc80000 {
478 compatible = "renesas,r8a7779-cpg-clocks";
479 reg = <0xffc80000 0x30>;
480 clocks = <&extal_clk>;
481 #clock-cells = <1>;
482 clock-output-names = "plla", "z", "zs", "s",
483 "s1", "p", "b", "out";
484 #power-domain-cells = <0>;
485 };
486
487 /* Fixed factor clocks */
488 i_clk: i {
489 compatible = "fixed-factor-clock";
490 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
491 #clock-cells = <0>;
492 clock-div = <2>;
493 clock-mult = <1>;
494 };
495 s3_clk: s3 {
496 compatible = "fixed-factor-clock";
497 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
498 #clock-cells = <0>;
499 clock-div = <8>;
500 clock-mult = <1>;
501 };
502 s4_clk: s4 {
503 compatible = "fixed-factor-clock";
504 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
505 #clock-cells = <0>;
506 clock-div = <16>;
507 clock-mult = <1>;
508 };
509 g_clk: g {
510 compatible = "fixed-factor-clock";
511 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
512 #clock-cells = <0>;
513 clock-div = <24>;
514 clock-mult = <1>;
515 };
516
517 /* Gate clocks */
518 mstp0_clks: clocks@ffc80030 {
519 compatible = "renesas,r8a7779-mstp-clocks",
520 "renesas,cpg-mstp-clocks";
521 reg = <0xffc80030 4>;
522 clocks = <&cpg_clocks R8A7779_CLK_S>,
523 <&cpg_clocks R8A7779_CLK_P>,
524 <&cpg_clocks R8A7779_CLK_P>,
525 <&cpg_clocks R8A7779_CLK_P>,
526 <&cpg_clocks R8A7779_CLK_S>,
527 <&cpg_clocks R8A7779_CLK_S>,
528 <&cpg_clocks R8A7779_CLK_P>,
529 <&cpg_clocks R8A7779_CLK_P>,
530 <&cpg_clocks R8A7779_CLK_P>,
531 <&cpg_clocks R8A7779_CLK_P>,
532 <&cpg_clocks R8A7779_CLK_P>,
533 <&cpg_clocks R8A7779_CLK_P>,
534 <&cpg_clocks R8A7779_CLK_P>,
535 <&cpg_clocks R8A7779_CLK_P>,
536 <&cpg_clocks R8A7779_CLK_P>,
537 <&cpg_clocks R8A7779_CLK_P>;
538 #clock-cells = <1>;
539 clock-indices = <
540 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
541 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
542 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
543 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
544 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
545 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
546 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
547 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
548 >;
549 clock-output-names =
550 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
551 "hscif0", "scif5", "scif4", "scif3", "scif2",
552 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
553 "i2c0";
554 };
555 mstp1_clks: clocks@ffc80034 {
556 compatible = "renesas,r8a7779-mstp-clocks",
557 "renesas,cpg-mstp-clocks";
558 reg = <0xffc80034 4>, <0xffc80044 4>;
559 clocks = <&cpg_clocks R8A7779_CLK_P>,
560 <&cpg_clocks R8A7779_CLK_P>,
561 <&cpg_clocks R8A7779_CLK_S>,
562 <&cpg_clocks R8A7779_CLK_S>,
563 <&cpg_clocks R8A7779_CLK_S>,
564 <&cpg_clocks R8A7779_CLK_S>,
565 <&cpg_clocks R8A7779_CLK_P>,
566 <&cpg_clocks R8A7779_CLK_P>,
567 <&cpg_clocks R8A7779_CLK_P>,
568 <&cpg_clocks R8A7779_CLK_S>;
569 #clock-cells = <1>;
570 clock-indices = <
571 R8A7779_CLK_USB01 R8A7779_CLK_USB2
572 R8A7779_CLK_DU R8A7779_CLK_VIN2
573 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
574 R8A7779_CLK_ETHER R8A7779_CLK_SATA
575 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
576 >;
577 clock-output-names =
578 "usb01", "usb2",
579 "du", "vin2",
580 "vin1", "vin0",
581 "ether", "sata",
582 "pcie", "vin3";
583 };
584 mstp3_clks: clocks@ffc8003c {
585 compatible = "renesas,r8a7779-mstp-clocks",
586 "renesas,cpg-mstp-clocks";
587 reg = <0xffc8003c 4>;
588 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
589 <&s4_clk>, <&s4_clk>;
590 #clock-cells = <1>;
591 clock-indices = <
592 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
593 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
594 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
595 >;
596 clock-output-names =
597 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
598 "mmc1", "mmc0";
599 };
600 };
601
602 prr: chipid@ff000044 {
603 compatible = "renesas,prr";
604 reg = <0xff000044 4>;
605 };
606
607 rst: reset-controller@ffcc0000 {
608 compatible = "renesas,r8a7779-reset-wdt";
609 reg = <0xffcc0000 0x48>;
610 };
611
612 sysc: system-controller@ffd85000 {
613 compatible = "renesas,r8a7779-sysc";
614 reg = <0xffd85000 0x0200>;
615 #power-domain-cells = <1>;
616 };
617};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
4 *
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Simon Horman
7 */
8
9#include <dt-bindings/clock/r8a7779-clock.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/power/r8a7779-sysc.h>
13
14/ {
15 compatible = "renesas,r8a7779";
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a9";
27 reg = <0>;
28 clock-frequency = <1000000000>;
29 clocks = <&cpg_clocks R8A7779_CLK_Z>;
30 };
31 cpu@1 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 reg = <1>;
35 clock-frequency = <1000000000>;
36 clocks = <&cpg_clocks R8A7779_CLK_Z>;
37 power-domains = <&sysc R8A7779_PD_ARM1>;
38 };
39 cpu@2 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a9";
42 reg = <2>;
43 clock-frequency = <1000000000>;
44 clocks = <&cpg_clocks R8A7779_CLK_Z>;
45 power-domains = <&sysc R8A7779_PD_ARM2>;
46 };
47 cpu@3 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a9";
50 reg = <3>;
51 clock-frequency = <1000000000>;
52 clocks = <&cpg_clocks R8A7779_CLK_Z>;
53 power-domains = <&sysc R8A7779_PD_ARM3>;
54 };
55 };
56
57 aliases {
58 spi0 = &hspi0;
59 spi1 = &hspi1;
60 spi2 = &hspi2;
61 };
62
63 gic: interrupt-controller@f0001000 {
64 compatible = "arm,cortex-a9-gic";
65 #interrupt-cells = <3>;
66 interrupt-controller;
67 reg = <0xf0001000 0x1000>,
68 <0xf0000100 0x100>;
69 };
70
71 timer@f0000200 {
72 compatible = "arm,cortex-a9-global-timer";
73 reg = <0xf0000200 0x100>;
74 interrupts = <GIC_PPI 11
75 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
76 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
77 };
78
79 timer@f0000600 {
80 compatible = "arm,cortex-a9-twd-timer";
81 reg = <0xf0000600 0x20>;
82 interrupts = <GIC_PPI 13
83 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
84 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
85 };
86
87 gpio0: gpio@ffc40000 {
88 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
89 reg = <0xffc40000 0x2c>;
90 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
91 #gpio-cells = <2>;
92 gpio-controller;
93 gpio-ranges = <&pfc 0 0 32>;
94 #interrupt-cells = <2>;
95 interrupt-controller;
96 };
97
98 gpio1: gpio@ffc41000 {
99 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
100 reg = <0xffc41000 0x2c>;
101 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
102 #gpio-cells = <2>;
103 gpio-controller;
104 gpio-ranges = <&pfc 0 32 32>;
105 #interrupt-cells = <2>;
106 interrupt-controller;
107 };
108
109 gpio2: gpio@ffc42000 {
110 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
111 reg = <0xffc42000 0x2c>;
112 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
113 #gpio-cells = <2>;
114 gpio-controller;
115 gpio-ranges = <&pfc 0 64 32>;
116 #interrupt-cells = <2>;
117 interrupt-controller;
118 };
119
120 gpio3: gpio@ffc43000 {
121 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
122 reg = <0xffc43000 0x2c>;
123 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
124 #gpio-cells = <2>;
125 gpio-controller;
126 gpio-ranges = <&pfc 0 96 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
129 };
130
131 gpio4: gpio@ffc44000 {
132 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
133 reg = <0xffc44000 0x2c>;
134 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
135 #gpio-cells = <2>;
136 gpio-controller;
137 gpio-ranges = <&pfc 0 128 32>;
138 #interrupt-cells = <2>;
139 interrupt-controller;
140 };
141
142 gpio5: gpio@ffc45000 {
143 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
144 reg = <0xffc45000 0x2c>;
145 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
146 #gpio-cells = <2>;
147 gpio-controller;
148 gpio-ranges = <&pfc 0 160 32>;
149 #interrupt-cells = <2>;
150 interrupt-controller;
151 };
152
153 gpio6: gpio@ffc46000 {
154 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio";
155 reg = <0xffc46000 0x2c>;
156 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
157 #gpio-cells = <2>;
158 gpio-controller;
159 gpio-ranges = <&pfc 0 192 9>;
160 #interrupt-cells = <2>;
161 interrupt-controller;
162 };
163
164 irqpin0: interrupt-controller@fe78001c {
165 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
166 #interrupt-cells = <2>;
167 status = "disabled";
168 interrupt-controller;
169 reg = <0xfe78001c 4>,
170 <0xfe780010 4>,
171 <0xfe780024 4>,
172 <0xfe780044 4>,
173 <0xfe780064 4>,
174 <0xfe780000 4>;
175 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
179 sense-bitfield-width = <2>;
180 };
181
182 i2c0: i2c@ffc70000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
186 reg = <0xffc70000 0x1000>;
187 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
189 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
190 status = "disabled";
191 };
192
193 i2c1: i2c@ffc71000 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
197 reg = <0xffc71000 0x1000>;
198 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
200 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
201 i2c-scl-internal-delay-ns = <5>;
202 status = "disabled";
203 };
204
205 i2c2: i2c@ffc72000 {
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
209 reg = <0xffc72000 0x1000>;
210 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
212 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
213 i2c-scl-internal-delay-ns = <5>;
214 status = "disabled";
215 };
216
217 i2c3: i2c@ffc73000 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
221 reg = <0xffc73000 0x1000>;
222 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
224 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
225 i2c-scl-internal-delay-ns = <5>;
226 status = "disabled";
227 };
228
229 scif0: serial@ffe40000 {
230 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
231 "renesas,scif";
232 reg = <0xffe40000 0x100>;
233 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
235 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
236 clock-names = "fck", "brg_int", "scif_clk";
237 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
238 status = "disabled";
239 };
240
241 scif1: serial@ffe41000 {
242 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
243 "renesas,scif";
244 reg = <0xffe41000 0x100>;
245 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
247 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
248 clock-names = "fck", "brg_int", "scif_clk";
249 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
250 status = "disabled";
251 };
252
253 scif2: serial@ffe42000 {
254 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
255 "renesas,scif";
256 reg = <0xffe42000 0x100>;
257 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
259 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
260 clock-names = "fck", "brg_int", "scif_clk";
261 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
262 status = "disabled";
263 };
264
265 scif3: serial@ffe43000 {
266 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
267 "renesas,scif";
268 reg = <0xffe43000 0x100>;
269 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
271 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
272 clock-names = "fck", "brg_int", "scif_clk";
273 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
274 status = "disabled";
275 };
276
277 scif4: serial@ffe44000 {
278 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
279 "renesas,scif";
280 reg = <0xffe44000 0x100>;
281 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
283 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
284 clock-names = "fck", "brg_int", "scif_clk";
285 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
286 status = "disabled";
287 };
288
289 scif5: serial@ffe45000 {
290 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
291 "renesas,scif";
292 reg = <0xffe45000 0x100>;
293 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
295 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
296 clock-names = "fck", "brg_int", "scif_clk";
297 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
298 status = "disabled";
299 };
300
301 hscif0: serial@ffe48000 {
302 compatible = "renesas,hscif-r8a7779",
303 "renesas,rcar-gen1-hscif", "renesas,hscif";
304 reg = <0xffe48000 96>;
305 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>,
307 <&cpg_clocks R8A7779_CLK_S>,
308 <&scif_clk>;
309 clock-names = "fck", "brg_int", "scif_clk";
310 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
311 status = "disabled";
312 };
313
314 hscif1: serial@ffe49000 {
315 compatible = "renesas,hscif-r8a7779",
316 "renesas,rcar-gen1-hscif", "renesas,hscif";
317 reg = <0xffe49000 96>;
318 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>,
320 <&cpg_clocks R8A7779_CLK_S>,
321 <&scif_clk>;
322 clock-names = "fck", "brg_int", "scif_clk";
323 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
324 status = "disabled";
325 };
326
327 pfc: pinctrl@fffc0000 {
328 compatible = "renesas,pfc-r8a7779";
329 reg = <0xfffc0000 0x23c>;
330 };
331
332 thermal@ffc48000 {
333 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
334 reg = <0xffc48000 0x38>;
335 };
336
337 tmu0: timer@ffd80000 {
338 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
339 reg = <0xffd80000 0x30>;
340 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
344 clock-names = "fck";
345 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
346
347 #renesas,channels = <3>;
348
349 status = "disabled";
350 };
351
352 tmu1: timer@ffd81000 {
353 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
354 reg = <0xffd81000 0x30>;
355 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
359 clock-names = "fck";
360 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
361
362 #renesas,channels = <3>;
363
364 status = "disabled";
365 };
366
367 tmu2: timer@ffd82000 {
368 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
369 reg = <0xffd82000 0x30>;
370 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
374 clock-names = "fck";
375 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
376
377 #renesas,channels = <3>;
378
379 status = "disabled";
380 };
381
382 sata: sata@fc600000 {
383 compatible = "renesas,sata-r8a7779";
384 reg = <0xfc600000 0x200000>;
385 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
387 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
388 status = "disabled";
389 };
390
391 sdhi0: mmc@ffe4c000 {
392 compatible = "renesas,sdhi-r8a7779",
393 "renesas,rcar-gen1-sdhi";
394 reg = <0xffe4c000 0x100>;
395 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
397 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
398 status = "disabled";
399 };
400
401 sdhi1: mmc@ffe4d000 {
402 compatible = "renesas,sdhi-r8a7779",
403 "renesas,rcar-gen1-sdhi";
404 reg = <0xffe4d000 0x100>;
405 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
407 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
408 status = "disabled";
409 };
410
411 sdhi2: mmc@ffe4e000 {
412 compatible = "renesas,sdhi-r8a7779",
413 "renesas,rcar-gen1-sdhi";
414 reg = <0xffe4e000 0x100>;
415 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
417 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
418 status = "disabled";
419 };
420
421 sdhi3: mmc@ffe4f000 {
422 compatible = "renesas,sdhi-r8a7779",
423 "renesas,rcar-gen1-sdhi";
424 reg = <0xffe4f000 0x100>;
425 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
427 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
428 status = "disabled";
429 };
430
431 hspi0: spi@fffc7000 {
432 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
433 reg = <0xfffc7000 0x18>;
434 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
435 #address-cells = <1>;
436 #size-cells = <0>;
437 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
438 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
439 status = "disabled";
440 };
441
442 hspi1: spi@fffc8000 {
443 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
444 reg = <0xfffc8000 0x18>;
445 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
446 #address-cells = <1>;
447 #size-cells = <0>;
448 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
449 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
450 status = "disabled";
451 };
452
453 hspi2: spi@fffc6000 {
454 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
455 reg = <0xfffc6000 0x18>;
456 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
457 #address-cells = <1>;
458 #size-cells = <0>;
459 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
460 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
461 status = "disabled";
462 };
463
464 du: display@fff80000 {
465 compatible = "renesas,du-r8a7779";
466 reg = <0xfff80000 0x40000>;
467 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&mstp1_clks R8A7779_CLK_DU>;
469 clock-names = "du.0";
470 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
471 status = "disabled";
472
473 ports {
474 #address-cells = <1>;
475 #size-cells = <0>;
476
477 port@0 {
478 reg = <0>;
479 du_out_rgb0: endpoint {
480 };
481 };
482 port@1 {
483 reg = <1>;
484 du_out_rgb1: endpoint {
485 };
486 };
487 };
488 };
489
490 clocks {
491 #address-cells = <1>;
492 #size-cells = <1>;
493 ranges;
494
495 /* External root clock */
496 extal_clk: extal {
497 compatible = "fixed-clock";
498 #clock-cells = <0>;
499 /* This value must be overriden by the board. */
500 clock-frequency = <0>;
501 };
502
503 /* External SCIF clock */
504 scif_clk: scif {
505 compatible = "fixed-clock";
506 #clock-cells = <0>;
507 /* This value must be overridden by the board. */
508 clock-frequency = <0>;
509 };
510
511 /* Special CPG clocks */
512 cpg_clocks: clocks@ffc80000 {
513 compatible = "renesas,r8a7779-cpg-clocks";
514 reg = <0xffc80000 0x30>;
515 clocks = <&extal_clk>;
516 #clock-cells = <1>;
517 clock-output-names = "plla", "z", "zs", "s",
518 "s1", "p", "b", "out";
519 #power-domain-cells = <0>;
520 };
521
522 /* Fixed factor clocks */
523 i_clk: i {
524 compatible = "fixed-factor-clock";
525 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
526 #clock-cells = <0>;
527 clock-div = <2>;
528 clock-mult = <1>;
529 };
530 s3_clk: s3 {
531 compatible = "fixed-factor-clock";
532 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
533 #clock-cells = <0>;
534 clock-div = <8>;
535 clock-mult = <1>;
536 };
537 s4_clk: s4 {
538 compatible = "fixed-factor-clock";
539 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
540 #clock-cells = <0>;
541 clock-div = <16>;
542 clock-mult = <1>;
543 };
544 g_clk: g {
545 compatible = "fixed-factor-clock";
546 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
547 #clock-cells = <0>;
548 clock-div = <24>;
549 clock-mult = <1>;
550 };
551
552 /* Gate clocks */
553 mstp0_clks: clocks@ffc80030 {
554 compatible = "renesas,r8a7779-mstp-clocks",
555 "renesas,cpg-mstp-clocks";
556 reg = <0xffc80030 4>;
557 clocks = <&cpg_clocks R8A7779_CLK_S>,
558 <&cpg_clocks R8A7779_CLK_P>,
559 <&cpg_clocks R8A7779_CLK_P>,
560 <&cpg_clocks R8A7779_CLK_P>,
561 <&cpg_clocks R8A7779_CLK_S>,
562 <&cpg_clocks R8A7779_CLK_S>,
563 <&cpg_clocks R8A7779_CLK_P>,
564 <&cpg_clocks R8A7779_CLK_P>,
565 <&cpg_clocks R8A7779_CLK_P>,
566 <&cpg_clocks R8A7779_CLK_P>,
567 <&cpg_clocks R8A7779_CLK_P>,
568 <&cpg_clocks R8A7779_CLK_P>,
569 <&cpg_clocks R8A7779_CLK_P>,
570 <&cpg_clocks R8A7779_CLK_P>,
571 <&cpg_clocks R8A7779_CLK_P>,
572 <&cpg_clocks R8A7779_CLK_P>;
573 #clock-cells = <1>;
574 clock-indices = <
575 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
576 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
577 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
578 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
579 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
580 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
581 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
582 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
583 >;
584 clock-output-names =
585 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
586 "hscif0", "scif5", "scif4", "scif3", "scif2",
587 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
588 "i2c0";
589 };
590 mstp1_clks: clocks@ffc80034 {
591 compatible = "renesas,r8a7779-mstp-clocks",
592 "renesas,cpg-mstp-clocks";
593 reg = <0xffc80034 4>, <0xffc80044 4>;
594 clocks = <&cpg_clocks R8A7779_CLK_P>,
595 <&cpg_clocks R8A7779_CLK_P>,
596 <&cpg_clocks R8A7779_CLK_S>,
597 <&cpg_clocks R8A7779_CLK_S>,
598 <&cpg_clocks R8A7779_CLK_S>,
599 <&cpg_clocks R8A7779_CLK_S>,
600 <&cpg_clocks R8A7779_CLK_P>,
601 <&cpg_clocks R8A7779_CLK_P>,
602 <&cpg_clocks R8A7779_CLK_P>,
603 <&cpg_clocks R8A7779_CLK_S>;
604 #clock-cells = <1>;
605 clock-indices = <
606 R8A7779_CLK_USB01 R8A7779_CLK_USB2
607 R8A7779_CLK_DU R8A7779_CLK_VIN2
608 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
609 R8A7779_CLK_ETHER R8A7779_CLK_SATA
610 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
611 >;
612 clock-output-names =
613 "usb01", "usb2",
614 "du", "vin2",
615 "vin1", "vin0",
616 "ether", "sata",
617 "pcie", "vin3";
618 };
619 mstp3_clks: clocks@ffc8003c {
620 compatible = "renesas,r8a7779-mstp-clocks",
621 "renesas,cpg-mstp-clocks";
622 reg = <0xffc8003c 4>;
623 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
624 <&s4_clk>, <&s4_clk>;
625 #clock-cells = <1>;
626 clock-indices = <
627 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
628 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
629 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
630 >;
631 clock-output-names =
632 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
633 "mmc1", "mmc0";
634 };
635 };
636
637 prr: chipid@ff000044 {
638 compatible = "renesas,prr";
639 reg = <0xff000044 4>;
640 };
641
642 rst: reset-controller@ffcc0000 {
643 compatible = "renesas,r8a7779-reset-wdt";
644 reg = <0xffcc0000 0x48>;
645 };
646
647 sysc: system-controller@ffd85000 {
648 compatible = "renesas,r8a7779-sysc";
649 reg = <0xffd85000 0x0200>;
650 #power-domain-cells = <1>;
651 };
652};