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1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <dt-bindings/clock/mt8135-clk.h>
16#include <dt-bindings/interrupt-controller/irq.h>
17#include <dt-bindings/interrupt-controller/arm-gic.h>
18#include <dt-bindings/reset/mt8135-resets.h>
19#include "skeleton64.dtsi"
20#include "mt8135-pinfunc.h"
21
22/ {
23 compatible = "mediatek,mt8135";
24 interrupt-parent = <&sysirq>;
25
26 cpu-map {
27 cluster0 {
28 core0 {
29 cpu = <&cpu0>;
30 };
31 core1 {
32 cpu = <&cpu1>;
33 };
34 };
35
36 cluster1 {
37 core0 {
38 cpu = <&cpu2>;
39 };
40 core1 {
41 cpu = <&cpu3>;
42 };
43 };
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49 enable-method = "mediatek,mt81xx-tz-smp";
50
51 cpu0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a7";
54 reg = <0x000>;
55 };
56
57 cpu1: cpu@1 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a7";
60 reg = <0x001>;
61 };
62
63 cpu2: cpu@100 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a15";
66 reg = <0x100>;
67 };
68
69 cpu3: cpu@101 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a15";
72 reg = <0x101>;
73 };
74 };
75
76 reserved-memory {
77 #address-cells = <2>;
78 #size-cells = <2>;
79 ranges;
80
81 trustzone-bootinfo@80002000 {
82 compatible = "mediatek,trustzone-bootinfo";
83 reg = <0 0x80002000 0 0x1000>;
84 };
85 };
86
87 clocks {
88 #address-cells = <2>;
89 #size-cells = <2>;
90 compatible = "simple-bus";
91 ranges;
92
93 system_clk: dummy13m {
94 compatible = "fixed-clock";
95 clock-frequency = <13000000>;
96 #clock-cells = <0>;
97 };
98
99 rtc_clk: dummy32k {
100 compatible = "fixed-clock";
101 clock-frequency = <32000>;
102 #clock-cells = <0>;
103 };
104
105 clk26m: clk26m {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <26000000>;
109 };
110 };
111
112 timer {
113 compatible = "arm,armv7-timer";
114 interrupt-parent = <&gic>;
115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
116 IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
118 IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
120 IRQ_TYPE_LEVEL_LOW)>,
121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
122 IRQ_TYPE_LEVEL_LOW)>;
123 clock-frequency = <13000000>;
124 arm,cpu-registers-not-fw-configured;
125 };
126
127 soc {
128 #address-cells = <2>;
129 #size-cells = <2>;
130 compatible = "simple-bus";
131 ranges;
132
133 topckgen: topckgen@10000000 {
134 compatible = "mediatek,mt8135-topckgen";
135 reg = <0 0x10000000 0 0x1000>;
136 #clock-cells = <1>;
137 };
138
139 infracfg: infracfg@10001000 {
140 #reset-cells = <1>;
141 #clock-cells = <1>;
142 compatible = "mediatek,mt8135-infracfg", "syscon";
143 reg = <0 0x10001000 0 0x1000>;
144 };
145
146 pericfg: pericfg@10003000 {
147 #reset-cells = <1>;
148 #clock-cells = <1>;
149 compatible = "mediatek,mt8135-pericfg", "syscon";
150 reg = <0 0x10003000 0 0x1000>;
151 };
152
153 /*
154 * Pinctrl access register at 0x10005000 and 0x1020c000 through
155 * regmap. Register 0x1000b000 is used by EINT.
156 */
157 pio: pinctrl@10005000 {
158 compatible = "mediatek,mt8135-pinctrl";
159 reg = <0 0x1000b000 0 0x1000>;
160 mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
161 pins-are-numbered;
162 gpio-controller;
163 #gpio-cells = <2>;
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
169 };
170
171 syscfg_pctl_a: syscfg_pctl_a@10005000 {
172 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
173 reg = <0 0x10005000 0 0x1000>;
174 };
175
176 timer: timer@10008000 {
177 compatible = "mediatek,mt8135-timer",
178 "mediatek,mt6577-timer";
179 reg = <0 0x10008000 0 0x80>;
180 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
181 clocks = <&system_clk>, <&rtc_clk>;
182 clock-names = "system-clk", "rtc-clk";
183 };
184
185 pwrap: pwrap@1000f000 {
186 compatible = "mediatek,mt8135-pwrap";
187 reg = <0 0x1000f000 0 0x1000>,
188 <0 0x11017000 0 0x1000>;
189 reg-names = "pwrap", "pwrap-bridge";
190 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
191 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
192 <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
193 reset-names = "pwrap", "pwrap-bridge";
194 clocks = <&clk26m>, <&clk26m>;
195 clock-names = "spi", "wrap";
196 };
197
198 sysirq: interrupt-controller@10200030 {
199 compatible = "mediatek,mt8135-sysirq",
200 "mediatek,mt6577-sysirq";
201 interrupt-controller;
202 #interrupt-cells = <3>;
203 interrupt-parent = <&gic>;
204 reg = <0 0x10200030 0 0x1c>;
205 };
206
207 apmixedsys: apmixedsys@10209000 {
208 compatible = "mediatek,mt8135-apmixedsys";
209 reg = <0 0x10209000 0 0x1000>;
210 #clock-cells = <1>;
211 };
212
213 syscfg_pctl_b: syscfg_pctl_b@1020c000 {
214 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
215 reg = <0 0x1020c000 0 0x1000>;
216 };
217
218 gic: interrupt-controller@10211000 {
219 compatible = "arm,cortex-a15-gic";
220 interrupt-controller;
221 #interrupt-cells = <3>;
222 interrupt-parent = <&gic>;
223 reg = <0 0x10211000 0 0x1000>,
224 <0 0x10212000 0 0x2000>,
225 <0 0x10214000 0 0x2000>,
226 <0 0x10216000 0 0x2000>;
227 };
228
229 uart0: serial@11006000 {
230 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
231 reg = <0 0x11006000 0 0x400>;
232 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
233 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
234 clock-names = "baud", "bus";
235 status = "disabled";
236 };
237
238 uart1: serial@11007000 {
239 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
240 reg = <0 0x11007000 0 0x400>;
241 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
242 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
243 clock-names = "baud", "bus";
244 status = "disabled";
245 };
246
247 uart2: serial@11008000 {
248 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
249 reg = <0 0x11008000 0 0x400>;
250 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
251 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
252 clock-names = "baud", "bus";
253 status = "disabled";
254 };
255
256 uart3: serial@11009000 {
257 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
258 reg = <0 0x11009000 0 0x400>;
259 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
260 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
261 clock-names = "baud", "bus";
262 status = "disabled";
263 };
264
265 };
266};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Joe.C <yingjoe.chen@mediatek.com>
5 *
6 */
7
8#include <dt-bindings/clock/mt8135-clk.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/reset/mt8135-resets.h>
12#include "mt8135-pinfunc.h"
13
14/ {
15 #address-cells = <2>;
16 #size-cells = <2>;
17 compatible = "mediatek,mt8135";
18 interrupt-parent = <&sysirq>;
19
20 cpu-map {
21 cluster0 {
22 core0 {
23 cpu = <&cpu0>;
24 };
25 core1 {
26 cpu = <&cpu1>;
27 };
28 };
29
30 cluster1 {
31 core0 {
32 cpu = <&cpu2>;
33 };
34 core1 {
35 cpu = <&cpu3>;
36 };
37 };
38 };
39
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 enable-method = "mediatek,mt81xx-tz-smp";
44
45 cpu0: cpu@0 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a7";
48 reg = <0x000>;
49 };
50
51 cpu1: cpu@1 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a7";
54 reg = <0x001>;
55 };
56
57 cpu2: cpu@100 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a15";
60 reg = <0x100>;
61 };
62
63 cpu3: cpu@101 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a15";
66 reg = <0x101>;
67 };
68 };
69
70 reserved-memory {
71 #address-cells = <2>;
72 #size-cells = <2>;
73 ranges;
74
75 trustzone-bootinfo@80002000 {
76 compatible = "mediatek,trustzone-bootinfo";
77 reg = <0 0x80002000 0 0x1000>;
78 };
79 };
80
81 clocks {
82 #address-cells = <2>;
83 #size-cells = <2>;
84 compatible = "simple-bus";
85 ranges;
86
87 system_clk: dummy13m {
88 compatible = "fixed-clock";
89 clock-frequency = <13000000>;
90 #clock-cells = <0>;
91 };
92
93 rtc_clk: dummy32k {
94 compatible = "fixed-clock";
95 clock-frequency = <32000>;
96 #clock-cells = <0>;
97 };
98
99 clk26m: clk26m {
100 compatible = "fixed-clock";
101 #clock-cells = <0>;
102 clock-frequency = <26000000>;
103 };
104 };
105
106 timer {
107 compatible = "arm,armv7-timer";
108 interrupt-parent = <&gic>;
109 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
110 IRQ_TYPE_LEVEL_LOW)>,
111 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
112 IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
114 IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
116 IRQ_TYPE_LEVEL_LOW)>;
117 clock-frequency = <13000000>;
118 arm,cpu-registers-not-fw-configured;
119 };
120
121 soc {
122 #address-cells = <2>;
123 #size-cells = <2>;
124 compatible = "simple-bus";
125 ranges;
126
127 topckgen: topckgen@10000000 {
128 compatible = "mediatek,mt8135-topckgen";
129 reg = <0 0x10000000 0 0x1000>;
130 #clock-cells = <1>;
131 };
132
133 infracfg: infracfg@10001000 {
134 #reset-cells = <1>;
135 #clock-cells = <1>;
136 compatible = "mediatek,mt8135-infracfg", "syscon";
137 reg = <0 0x10001000 0 0x1000>;
138 };
139
140 pericfg: pericfg@10003000 {
141 #reset-cells = <1>;
142 #clock-cells = <1>;
143 compatible = "mediatek,mt8135-pericfg", "syscon";
144 reg = <0 0x10003000 0 0x1000>;
145 };
146
147 /*
148 * Pinctrl access register at 0x10005000 and 0x1020c000 through
149 * regmap. Register 0x1000b000 is used by EINT.
150 */
151 pio: pinctrl@10005000 {
152 compatible = "mediatek,mt8135-pinctrl";
153 reg = <0 0x1000b000 0 0x1000>;
154 mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
155 pins-are-numbered;
156 gpio-controller;
157 #gpio-cells = <2>;
158 interrupt-controller;
159 #interrupt-cells = <2>;
160 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
163 };
164
165 syscfg_pctl_a: syscfg_pctl_a@10005000 {
166 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
167 reg = <0 0x10005000 0 0x1000>;
168 };
169
170 timer: timer@10008000 {
171 compatible = "mediatek,mt8135-timer",
172 "mediatek,mt6577-timer";
173 reg = <0 0x10008000 0 0x80>;
174 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
175 clocks = <&system_clk>, <&rtc_clk>;
176 clock-names = "system-clk", "rtc-clk";
177 };
178
179 pwrap: pwrap@1000f000 {
180 compatible = "mediatek,mt8135-pwrap";
181 reg = <0 0x1000f000 0 0x1000>,
182 <0 0x11017000 0 0x1000>;
183 reg-names = "pwrap", "pwrap-bridge";
184 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
185 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
186 <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
187 reset-names = "pwrap", "pwrap-bridge";
188 clocks = <&clk26m>, <&clk26m>;
189 clock-names = "spi", "wrap";
190 };
191
192 sysirq: interrupt-controller@10200030 {
193 compatible = "mediatek,mt8135-sysirq",
194 "mediatek,mt6577-sysirq";
195 interrupt-controller;
196 #interrupt-cells = <3>;
197 interrupt-parent = <&gic>;
198 reg = <0 0x10200030 0 0x1c>;
199 };
200
201 apmixedsys: apmixedsys@10209000 {
202 compatible = "mediatek,mt8135-apmixedsys";
203 reg = <0 0x10209000 0 0x1000>;
204 #clock-cells = <1>;
205 };
206
207 syscfg_pctl_b: syscfg_pctl_b@1020c000 {
208 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
209 reg = <0 0x1020c000 0 0x1000>;
210 };
211
212 gic: interrupt-controller@10211000 {
213 compatible = "arm,cortex-a15-gic";
214 interrupt-controller;
215 #interrupt-cells = <3>;
216 interrupt-parent = <&gic>;
217 reg = <0 0x10211000 0 0x1000>,
218 <0 0x10212000 0 0x2000>,
219 <0 0x10214000 0 0x2000>,
220 <0 0x10216000 0 0x2000>;
221 };
222
223 uart0: serial@11006000 {
224 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
225 reg = <0 0x11006000 0 0x400>;
226 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
227 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
228 clock-names = "baud", "bus";
229 status = "disabled";
230 };
231
232 uart1: serial@11007000 {
233 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
234 reg = <0 0x11007000 0 0x400>;
235 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
236 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
237 clock-names = "baud", "bus";
238 status = "disabled";
239 };
240
241 uart2: serial@11008000 {
242 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
243 reg = <0 0x11008000 0 0x400>;
244 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
245 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
246 clock-names = "baud", "bus";
247 status = "disabled";
248 };
249
250 uart3: serial@11009000 {
251 compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
252 reg = <0 0x11009000 0 0x400>;
253 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
254 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
255 clock-names = "baud", "bus";
256 status = "disabled";
257 };
258
259 };
260};