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1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 */
6
7#include <dt-bindings/input/input.h>
8
9/ {
10 cpus {
11 cpu@0 {
12 cpu0-supply = <&vcc>;
13 };
14 };
15
16 memory@80000000 {
17 device_type = "memory";
18 reg = <0x80000000 0>;
19 };
20
21 wl12xx_vmmc: wl12xx_vmmc {
22 compatible = "regulator-fixed";
23 regulator-name = "vwl1271";
24 regulator-min-microvolt = <1800000>;
25 regulator-max-microvolt = <1800000>;
26 gpio = <&gpio1 3 0>; /* gpio_3 */
27 startup-delay-us = <70000>;
28 enable-active-high;
29 vin-supply = <&vaux3>;
30 };
31
32 /* HS USB Host PHY on PORT 1 */
33 hsusb2_phy: hsusb2_phy {
34 compatible = "usb-nop-xceiv";
35 reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
36 #phy-cells = <0>;
37 };
38};
39
40&gpmc {
41 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
42
43 nand@0,0 {
44 compatible = "ti,omap2-nand";
45 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
46 interrupt-parent = <&gpmc>;
47 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
48 <1 IRQ_TYPE_NONE>; /* termcount */
49 linux,mtd-name = "micron,mt29f4g16abbda3w";
50 nand-bus-width = <16>;
51 ti,nand-ecc-opt = "bch8";
52 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
53 gpmc,sync-clk-ps = <0>;
54 gpmc,cs-on-ns = <0>;
55 gpmc,cs-rd-off-ns = <44>;
56 gpmc,cs-wr-off-ns = <44>;
57 gpmc,adv-on-ns = <6>;
58 gpmc,adv-rd-off-ns = <34>;
59 gpmc,adv-wr-off-ns = <44>;
60 gpmc,we-off-ns = <40>;
61 gpmc,oe-off-ns = <54>;
62 gpmc,access-ns = <64>;
63 gpmc,rd-cycle-ns = <82>;
64 gpmc,wr-cycle-ns = <82>;
65 gpmc,wr-access-ns = <40>;
66 gpmc,wr-data-mux-bus-ns = <0>;
67 gpmc,device-width = <2>;
68 #address-cells = <1>;
69 #size-cells = <1>;
70 };
71};
72
73&i2c1 {
74 pinctrl-names = "default";
75 pinctrl-0 = <&i2c1_pins>;
76 clock-frequency = <2600000>;
77
78 twl: twl@48 {
79 reg = <0x48>;
80 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
81 interrupt-parent = <&intc>;
82 twl_audio: audio {
83 compatible = "ti,twl4030-audio";
84 codec {
85 ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
86 };
87 };
88 };
89};
90
91&i2c2 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&i2c2_pins>;
94 clock-frequency = <400000>;
95};
96
97&i2c3 {
98 pinctrl-names = "default";
99 pinctrl-0 = <&i2c3_pins>;
100 clock-frequency = <400000>;
101};
102
103&mmc3 {
104 interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
105 pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
106 pinctrl-names = "default";
107 vmmc-supply = <&wl12xx_vmmc>;
108 non-removable;
109 bus-width = <4>;
110 cap-power-off-card;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 wlcore: wlcore@2 {
114 compatible = "ti,wl1273";
115 reg = <2>;
116 interrupt-parent = <&gpio1>;
117 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; /* gpio 2 */
118 ref-clock-frequency = <26000000>;
119 };
120};
121
122&usbhshost {
123 port2-mode = "ehci-phy";
124};
125
126&usbhsehci {
127 phys = <0 &hsusb2_phy>;
128};
129
130
131&omap3_pmx_core {
132 pinctrl-names = "default";
133 pinctrl-0 = <&hsusb2_pins>;
134
135 mmc3_pins: pinmux_mm3_pins {
136 pinctrl-single,pins = <
137 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
138 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
139 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
140 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
141 OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
142 OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */
143 >;
144 };
145 mcbsp2_pins: pinmux_mcbsp2_pins {
146 pinctrl-single,pins = <
147 OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
148 OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
149 OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
150 OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
151 >;
152 };
153 uart2_pins: pinmux_uart2_pins {
154 pinctrl-single,pins = <
155 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
156 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
157 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
158 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
159 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */
160 >;
161 };
162 mcspi1_pins: pinmux_mcspi1_pins {
163 pinctrl-single,pins = <
164 OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
165 OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
166 OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
167 OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
168 >;
169 };
170
171 hsusb2_pins: pinmux_hsusb2_pins {
172 pinctrl-single,pins = <
173 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
174 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
175 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
176 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
177 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
178 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
179 >;
180 };
181
182 hsusb_otg_pins: pinmux_hsusb_otg_pins {
183 pinctrl-single,pins = <
184 OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
185 OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
186 OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
187 OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
188 OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
189 OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
190 OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
191 OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
192 OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
193 OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
194 OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
195 OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
196 >;
197 };
198
199 i2c1_pins: pinmux_i2c1_pins {
200 pinctrl-single,pins = <
201 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
202 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
203 OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
204 >;
205 };
206};
207
208&omap3_pmx_wkup {
209 pinctrl-names = "default";
210 pinctrl-0 = <&hsusb2_reset_pin>;
211 hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
212 pinctrl-single,pins = <
213 OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
214 >;
215 };
216 wl127x_gpio: pinmux_wl127x_gpio_pin {
217 pinctrl-single,pins = <
218 OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
219 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
220 >;
221 };
222 i2c2_pins: pinmux_i2c2_pins {
223 pinctrl-single,pins = <
224 OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
225 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
226 >;
227 };
228 i2c3_pins: pinmux_i2c3_pins {
229 pinctrl-single,pins = <
230 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
231 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
232 >;
233 };
234};
235
236&omap3_pmx_core2 {
237 pinctrl-names = "default";
238 pinctrl-0 = <&hsusb2_2_pins>;
239 hsusb2_2_pins: pinmux_hsusb2_2_pins {
240 pinctrl-single,pins = <
241 OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
242 OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
243 OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
244 OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
245 OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
246 OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
247 >;
248 };
249};
250
251&uart2 {
252 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
253 pinctrl-names = "default";
254 pinctrl-0 = <&uart2_pins>;
255};
256
257&mcspi1 {
258 pinctrl-names = "default";
259 pinctrl-0 = <&mcspi1_pins>;
260};
261
262#include "twl4030.dtsi"
263#include "twl4030_omap3.dtsi"
264
265&vaux3 {
266 regulator-min-microvolt = <2800000>;
267 regulator-max-microvolt = <2800000>;
268};
269
270&twl {
271 twl_power: power {
272 compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
273 ti,use_poweroff;
274 };
275};
276
277&twl_gpio {
278 ti,use-leds;
279};
1// SPDX-License-Identifier: GPL-2.0-only
2
3#include <dt-bindings/input/input.h>
4
5/ {
6 cpus {
7 cpu@0 {
8 cpu0-supply = <&vcc>;
9 };
10 };
11
12 memory@80000000 {
13 device_type = "memory";
14 reg = <0x80000000 0>;
15 };
16
17 wl12xx_vmmc: wl12xx_vmmc {
18 compatible = "regulator-fixed";
19 regulator-name = "vwl1271";
20 regulator-min-microvolt = <1800000>;
21 regulator-max-microvolt = <1800000>;
22 gpio = <&gpio1 3 0>; /* gpio_3 */
23 startup-delay-us = <70000>;
24 enable-active-high;
25 vin-supply = <&vaux3>;
26 };
27
28 /* HS USB Host PHY on PORT 1 */
29 hsusb2_phy: hsusb2_phy {
30 compatible = "usb-nop-xceiv";
31 reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* gpio_4 */
32 #phy-cells = <0>;
33 };
34
35 /* fixed 26MHz oscillator */
36 hfclk_26m: oscillator {
37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-frequency = <26000000>;
40 };
41};
42
43&gpmc {
44 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
45
46 nand@0,0 {
47 compatible = "ti,omap2-nand";
48 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
49 interrupt-parent = <&gpmc>;
50 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
51 <1 IRQ_TYPE_NONE>; /* termcount */
52 linux,mtd-name = "micron,mt29f4g16abbda3w";
53 nand-bus-width = <16>;
54 ti,nand-ecc-opt = "bch8";
55 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
56 gpmc,sync-clk-ps = <0>;
57 gpmc,cs-on-ns = <0>;
58 gpmc,cs-rd-off-ns = <44>;
59 gpmc,cs-wr-off-ns = <44>;
60 gpmc,adv-on-ns = <6>;
61 gpmc,adv-rd-off-ns = <34>;
62 gpmc,adv-wr-off-ns = <44>;
63 gpmc,we-off-ns = <40>;
64 gpmc,oe-off-ns = <54>;
65 gpmc,access-ns = <64>;
66 gpmc,rd-cycle-ns = <82>;
67 gpmc,wr-cycle-ns = <82>;
68 gpmc,wr-access-ns = <40>;
69 gpmc,wr-data-mux-bus-ns = <0>;
70 gpmc,device-width = <2>;
71 #address-cells = <1>;
72 #size-cells = <1>;
73 };
74};
75
76&i2c1 {
77 pinctrl-names = "default";
78 pinctrl-0 = <&i2c1_pins>;
79 clock-frequency = <2600000>;
80
81 twl: twl@48 {
82 reg = <0x48>;
83 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
84 interrupt-parent = <&intc>;
85 clocks = <&hfclk_26m>;
86 clock-names = "fck";
87 twl_audio: audio {
88 compatible = "ti,twl4030-audio";
89 codec {
90 ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
91 };
92 };
93 };
94};
95
96&i2c2 {
97 pinctrl-names = "default";
98 pinctrl-0 = <&i2c2_pins>;
99 clock-frequency = <400000>;
100};
101
102&i2c3 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&i2c3_pins>;
105 clock-frequency = <400000>;
106
107 touchscreen: tsc2004@48 {
108 compatible = "ti,tsc2004";
109 reg = <0x48>;
110 vio-supply = <&vaux1>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&tsc2004_pins>;
113 interrupts-extended = <&gpio5 25 IRQ_TYPE_EDGE_RISING>; /* gpio 153 */
114
115 touchscreen-fuzz-x = <4>;
116 touchscreen-fuzz-y = <7>;
117 touchscreen-fuzz-pressure = <2>;
118 touchscreen-size-x = <4096>;
119 touchscreen-size-y = <4096>;
120 touchscreen-max-pressure = <2048>;
121
122 ti,x-plate-ohms = <280>;
123 ti,esd-recovery-timeout-ms = <8000>;
124 };
125};
126
127&mmc3 {
128 interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
129 pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
130 pinctrl-names = "default";
131 vmmc-supply = <&wl12xx_vmmc>;
132 non-removable;
133 bus-width = <4>;
134 cap-power-off-card;
135 #address-cells = <1>;
136 #size-cells = <0>;
137 wlcore: wlcore@2 {
138 compatible = "ti,wl1273";
139 reg = <2>;
140 interrupt-parent = <&gpio1>;
141 interrupts = <2 IRQ_TYPE_EDGE_RISING>; /* gpio 2 */
142 ref-clock-frequency = <26000000>;
143 };
144};
145
146&usbhshost {
147 port2-mode = "ehci-phy";
148};
149
150&usbhsehci {
151 phys = <0 &hsusb2_phy>;
152};
153
154
155&omap3_pmx_core {
156 pinctrl-names = "default";
157 pinctrl-0 = <&hsusb2_pins>;
158
159 mmc3_pins: pinmux_mm3_pins {
160 pinctrl-single,pins = <
161 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
162 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
163 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
164 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
165 OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
166 OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs2.sdmmc_clk */
167 >;
168 };
169 mcbsp2_pins: pinmux_mcbsp2_pins {
170 pinctrl-single,pins = <
171 OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
172 OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
173 OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
174 OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
175 >;
176 };
177 uart2_pins: pinmux_uart2_pins {
178 pinctrl-single,pins = <
179 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
180 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
181 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
182 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
183 OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4) /* GPIO_162,BT_EN */
184 >;
185 };
186 mcspi1_pins: pinmux_mcspi1_pins {
187 pinctrl-single,pins = <
188 OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
189 OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
190 OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
191 OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
192 >;
193 };
194
195 hsusb2_pins: pinmux_hsusb2_pins {
196 pinctrl-single,pins = <
197 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
198 OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
199 OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
200 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
201 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
202 OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
203 >;
204 };
205
206 hsusb_otg_pins: pinmux_hsusb_otg_pins {
207 pinctrl-single,pins = <
208 OMAP3_CORE1_IOPAD(0x21a2, PIN_INPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */
209 OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */
210 OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT | MUX_MODE0) /* hsusb0_dir.hsusb0_dir */
211 OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT | MUX_MODE0) /* hsusb0_nxt.hsusb0_nxt */
212 OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT | MUX_MODE0) /* hsusb0_data0.hsusb0_data0 */
213 OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT | MUX_MODE0) /* hsusb0_data1.hsusb0_data1 */
214 OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT | MUX_MODE0) /* hsusb0_data2.hsusb0_data2 */
215 OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT | MUX_MODE0) /* hsusb0_data3.hsusb0_data3 */
216 OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT | MUX_MODE0) /* hsusb0_data4.hsusb0_data4 */
217 OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT | MUX_MODE0) /* hsusb0_data5.hsusb0_data5 */
218 OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
219 OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
220 >;
221 };
222
223 i2c1_pins: pinmux_i2c1_pins {
224 pinctrl-single,pins = <
225 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
226 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
227 OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
228 >;
229 };
230
231 i2c2_pins: pinmux_i2c2_pins {
232 pinctrl-single,pins = <
233 OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
234 OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
235 >;
236 };
237
238 i2c3_pins: pinmux_i2c3_pins {
239 pinctrl-single,pins = <
240 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
241 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
242 >;
243 };
244
245 tsc2004_pins: pinmux_tsc2004_pins {
246 pinctrl-single,pins = <
247 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */
248 >;
249 };
250};
251
252&omap3_pmx_wkup {
253 pinctrl-names = "default";
254 pinctrl-0 = <&hsusb2_reset_pin>;
255 hsusb2_reset_pin: pinmux_hsusb1_reset_pin {
256 pinctrl-single,pins = <
257 OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
258 >;
259 };
260 wl127x_gpio: pinmux_wl127x_gpio_pin {
261 pinctrl-single,pins = <
262 OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
263 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
264 >;
265 };
266};
267
268&omap3_pmx_core2 {
269 pinctrl-names = "default";
270 pinctrl-0 = <&hsusb2_2_pins>;
271 hsusb2_2_pins: pinmux_hsusb2_2_pins {
272 pinctrl-single,pins = <
273 OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
274 OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
275 OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
276 OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
277 OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
278 OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
279 >;
280 };
281};
282
283&uart2 {
284 interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&uart2_pins>;
287};
288
289&mcspi1 {
290 pinctrl-names = "default";
291 pinctrl-0 = <&mcspi1_pins>;
292};
293
294#include "twl4030.dtsi"
295#include "twl4030_omap3.dtsi"
296
297&vaux3 {
298 regulator-min-microvolt = <2800000>;
299 regulator-max-microvolt = <2800000>;
300};
301
302&twl {
303 twl_power: power {
304 compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";
305 ti,use_poweroff;
306 };
307};
308
309&twl_gpio {
310 ti,use-leds;
311};