1// SPDX-License-Identifier: ISC
  2/*
  3 * Device Tree file for Intel XScale Network Processors
  4 * in the IXP 4xx series.
  5 */
  6#include <dt-bindings/interrupt-controller/irq.h>
  7#include <dt-bindings/gpio/gpio.h>
  8
  9/ {
 10	soc {
 11		#address-cells = <1>;
 12		#size-cells = <1>;
 13		ranges;
 14		compatible = "simple-bus";
 15		interrupt-parent = <&intcon>;
 16
 17		/*
 18		 * The IXP4xx expansion bus is a set of 16 or 32MB
 19		 * windows in the 256MB space from 0x50000000 to
 20		 * 0x5fffffff.
 21		 */
 22		bus@50000000 {
 23			compatible = "simple-bus";
 24			#address-cells = <1>;
 25			#size-cells = <1>;
 26			ranges = <0x00000000 0x50000000 0x10000000>;
 27			dma-ranges = <0x00000000 0x50000000 0x10000000>;
 28		};
 29
 30		qmgr: queue-manager@60000000 {
 31			compatible = "intel,ixp4xx-ahb-queue-manager";
 32			reg = <0x60000000 0x4000>;
 33			interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
 34		};
 35
 36		pci@c0000000 {
 37			/* compatible filled in by per-soc device tree */
 38			reg = <0xc0000000 0x1000>;
 39			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
 40				     <9 IRQ_TYPE_LEVEL_HIGH>,
 41				     <10 IRQ_TYPE_LEVEL_HIGH>;
 42			#address-cells = <3>;
 43			#size-cells = <2>;
 44			device_type = "pci";
 45			bus-range = <0x00 0xff>;
 46			status = "disabled";
 47
 48			ranges =
 49			/*
 50			 * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
 51			 * done in 4 chunks of 16MB each.
 52			 */
 53			<0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
 54			/* 64KB I/O space at 0x4c000000 */
 55			<0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
 56
 57			/*
 58			 * This needs to map to the start of physical memory so
 59			 * PCI devices can see all (hopefully) memory. This is done
 60			 * using 4 1:1 16MB windows, so the RAM should not be more than
 61			 * 64 MB for this to work. If your memory is anywhere else
 62			 * than at 0x0 you need to alter this.
 63			 */
 64			dma-ranges =
 65			<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
 66
 67			#interrupt-cells = <1>;
 68			interrupt-map-mask = <0xf800 0 0 7>;
 69			/* Each unique DTS using PCI must specify the swizzling */
 70		};
 71
 72		uart0: serial@c8000000 {
 73			compatible = "intel,xscale-uart";
 74			reg = <0xc8000000 0x1000>;
 75			/*
 76			 * The reg-offset and reg-shift is a side effect
 77			 * of running the platform in big endian mode.
 78			 */
 79			reg-offset = <3>;
 80			reg-shift = <2>;
 81			interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
 82			clock-frequency = <14745600>;
 83			no-loopback-test;
 84		};
 85
 86		gpio0: gpio@c8004000 {
 87			compatible = "intel,ixp4xx-gpio";
 88			reg = <0xc8004000 0x1000>;
 89			gpio-controller;
 90			#gpio-cells = <2>;
 91			interrupt-controller;
 92			#interrupt-cells = <2>;
 93		};
 94
 95		intcon: interrupt-controller@c8003000 {
 96			/*
 97			 * Note: no compatible string. The subvariant of the
 98			 * chip needs to define what version it is. The
 99			 * location of the interrupt controller is fixed in
100			 * memory across all variants.
101			 */
102			reg = <0xc8003000 0x100>;
103			interrupt-controller;
104			#interrupt-cells = <2>;
105		};
106
107		timer@c8005000 {
108			compatible = "intel,ixp4xx-timer";
109			reg = <0xc8005000 0x100>;
110			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
111		};
112
113		npe: npe@c8006000 {
114			compatible = "intel,ixp4xx-network-processing-engine";
115			reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
116
117			/* NPE-C contains a crypto accelerator */
118			crypto {
119				compatible = "intel,ixp4xx-crypto";
120				intel,npe-handle = <&npe 2>;
121				queue-rx = <&qmgr 30>;
122				queue-txready = <&qmgr 29>;
123			};
124		};
125
126		/* This is known as EthB */
127		ethernet@c8009000 {
128			compatible = "intel,ixp4xx-ethernet";
129			reg = <0xc8009000 0x1000>;
130			status = "disabled";
131			/* Dummy values that depend on firmware */
132			queue-rx = <&qmgr 3>;
133			queue-txready = <&qmgr 20>;
134			intel,npe-handle = <&npe 1>;
135		};
136
137		/* This is known as EthC */
138		ethernet@c800a000 {
139			compatible = "intel,ixp4xx-ethernet";
140			reg = <0xc800a000 0x1000>;
141			status = "disabled";
142			/* Dummy values that depend on firmware */
143			queue-rx = <&qmgr 0>;
144			queue-txready = <&qmgr 0>;
145			intel,npe-handle = <&npe 2>;
146		};
147
148		/* This is known as EthA */
149		ethernet@c800c000 {
150			compatible = "intel,ixp4xx-ethernet";
151			reg = <0xc800c000 0x1000>;
152			status = "disabled";
153			intel,npe = <0>;
154			/* Dummy values that depend on firmware */
155			queue-rx = <&qmgr 0>;
156			queue-txready = <&qmgr 0>;
157		};
158	};
159};