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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 PHYTEC Messtechnik GmbH
4 * Author: Christian Hemp <c.hemp@phytec.de>
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8
9/ {
10 aliases {
11 rtc1 = &da9062_rtc;
12 rtc2 = &snvs_rtc;
13 };
14
15 /*
16 * Set the minimum memory size here and
17 * let the bootloader set the real size.
18 */
19 memory@10000000 {
20 device_type = "memory";
21 reg = <0x10000000 0x8000000>;
22 };
23
24 gpio_leds_som: somleds {
25 compatible = "gpio-leds";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpioleds_som>;
28
29 som-led-green {
30 label = "phycore:green";
31 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
32 linux,default-trigger = "heartbeat";
33 };
34 };
35};
36
37&ecspi1 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_ecspi1>;
40 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
41 status = "okay";
42
43 m25p80: flash@0 {
44 compatible = "jedec,spi-nor";
45 spi-max-frequency = <20000000>;
46 reg = <0>;
47 status = "disabled";
48 };
49};
50
51&fec {
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_enet>;
54 phy-handle = <ðphy>;
55 phy-mode = "rgmii";
56 phy-supply = <&vdd_eth_io>;
57 phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
58 status = "disabled";
59
60 mdio {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 ethphy: ethernet-phy@3 {
65 reg = <3>;
66 txc-skew-ps = <1680>;
67 rxc-skew-ps = <1860>;
68 };
69 };
70};
71
72&gpmi {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_gpmi_nand>;
75 nand-on-flash-bbt;
76 status = "disabled";
77};
78
79&i2c3 {
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_i2c3>;
82 clock-frequency = <400000>;
83 status = "okay";
84
85 eeprom@50 {
86 compatible = "atmel,24c32";
87 reg = <0x50>;
88 };
89
90 pmic@58 {
91 compatible = "dlg,da9062";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_pmic>;
94 reg = <0x58>;
95 interrupt-parent = <&gpio1>;
96 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
97 interrupt-controller;
98
99 da9062_rtc: rtc {
100 compatible = "dlg,da9062-rtc";
101 };
102
103 watchdog {
104 compatible = "dlg,da9062-watchdog";
105 };
106
107 regulators {
108 vdd_arm: buck1 {
109 regulator-name = "vdd_arm";
110 regulator-min-microvolt = <730000>;
111 regulator-max-microvolt = <1380000>;
112 regulator-always-on;
113 };
114
115 vdd_soc: buck2 {
116 regulator-name = "vdd_soc";
117 regulator-min-microvolt = <730000>;
118 regulator-max-microvolt = <1380000>;
119 regulator-always-on;
120 };
121
122 vdd_ddr3_1p5: buck3 {
123 regulator-name = "vdd_ddr3";
124 regulator-min-microvolt = <1500000>;
125 regulator-max-microvolt = <1500000>;
126 regulator-always-on;
127 };
128
129 vdd_eth_1p2: buck4 {
130 regulator-name = "vdd_eth";
131 regulator-min-microvolt = <1200000>;
132 regulator-max-microvolt = <1200000>;
133 regulator-always-on;
134 };
135
136 vdd_snvs: ldo1 {
137 regulator-name = "vdd_snvs";
138 regulator-min-microvolt = <3000000>;
139 regulator-max-microvolt = <3000000>;
140 regulator-always-on;
141 };
142
143 vdd_high: ldo2 {
144 regulator-name = "vdd_high";
145 regulator-min-microvolt = <3000000>;
146 regulator-max-microvolt = <3000000>;
147 regulator-always-on;
148 };
149
150 vdd_eth_io: ldo3 {
151 regulator-name = "vdd_eth_io";
152 regulator-min-microvolt = <2500000>;
153 regulator-max-microvolt = <2500000>;
154 };
155
156 vdd_emmc_1p8: ldo4 {
157 regulator-name = "vdd_emmc";
158 regulator-min-microvolt = <1800000>;
159 regulator-max-microvolt = <1800000>;
160 };
161 };
162 };
163};
164
165®_arm {
166 vin-supply = <&vdd_arm>;
167};
168
169®_pu {
170 vin-supply = <&vdd_soc>;
171};
172
173®_soc {
174 vin-supply = <&vdd_soc>;
175};
176
177&snvs_poweroff {
178 status = "okay";
179};
180
181&usdhc4 {
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_usdhc4>;
184 bus-width = <8>;
185 non-removable;
186 vmmc-supply = <&vdd_emmc_1p8>;
187 status = "disabled";
188};
189
190&iomuxc {
191 pinctrl_enet: enetgrp {
192 fsl,pins = <
193 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
194 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
195 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
196 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
197 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
198 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
199 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
200 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
201 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
202 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
203 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
204 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
205 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
206 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
207 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
208 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
209 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
210 >;
211 };
212
213 pinctrl_gpioleds_som: gpioledssomgrp {
214 fsl,pins = <
215 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
216 >;
217 };
218
219 pinctrl_gpmi_nand: gpminandgrp {
220 fsl,pins = <
221 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
222 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
223 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
224 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
225 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
226 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
227 MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
228 MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
229 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
230 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
231 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
232 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
233 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
234 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
235 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
236 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
237 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
238 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
239 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
240 >;
241 };
242
243 pinctrl_i2c3: i2c3grp {
244 fsl,pins = <
245 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
246 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
247 >;
248 };
249
250 pinctrl_ecspi1: ecspi1grp {
251 fsl,pins = <
252 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
253 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
254 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
255 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
256 >;
257 };
258
259 pinctrl_pmic: pmicgrp {
260 fsl,pins = <
261 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
262 >;
263 };
264
265 pinctrl_usdhc4: usdhc4grp {
266 fsl,pins = <
267 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
268 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
269 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
270 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
271 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
272 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
273 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
274 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
275 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
276 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
277 >;
278 };
279};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 PHYTEC Messtechnik GmbH
4 * Author: Christian Hemp <c.hemp@phytec.de>
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/regulator/dlg,da9063-regulator.h>
9
10/ {
11 aliases {
12 rtc1 = &da9062_rtc;
13 rtc2 = &snvs_rtc;
14 };
15
16 /*
17 * Set the minimum memory size here and
18 * let the bootloader set the real size.
19 */
20 memory@10000000 {
21 device_type = "memory";
22 reg = <0x10000000 0x8000000>;
23 };
24
25 gpio_leds_som: somleds {
26 compatible = "gpio-leds";
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_gpioleds_som>;
29
30 som-led-green {
31 label = "phycore:green";
32 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
33 linux,default-trigger = "heartbeat";
34 };
35 };
36};
37
38&ecspi1 {
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_ecspi1>;
41 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
42 status = "okay";
43
44 m25p80: flash@0 {
45 compatible = "jedec,spi-nor";
46 spi-max-frequency = <20000000>;
47 reg = <0>;
48 status = "disabled";
49 };
50};
51
52&fec {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_enet>;
55 phy-handle = <ðphy>;
56 phy-mode = "rgmii";
57 phy-supply = <&vdd_eth_io>;
58 phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
59 status = "disabled";
60
61 mdio {
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 ethphy: ethernet-phy@3 {
66 reg = <3>;
67 txc-skew-ps = <1680>;
68 rxc-skew-ps = <1860>;
69 };
70 };
71};
72
73&gpmi {
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_gpmi_nand>;
76 nand-on-flash-bbt;
77 status = "disabled";
78};
79
80&i2c3 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_i2c3>;
83 clock-frequency = <400000>;
84 status = "okay";
85
86 eeprom@50 {
87 compatible = "st,24c32", "atmel,24c32";
88 pagesize = <32>;
89 reg = <0x50>;
90 };
91
92 pmic: pmic@58 {
93 compatible = "dlg,da9062";
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_pmic>;
96 reg = <0x58>;
97 interrupt-parent = <&gpio1>;
98 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
99 interrupt-controller;
100 gpio-controller;
101 #gpio-cells = <2>;
102
103 da9062_rtc: rtc {
104 compatible = "dlg,da9062-rtc";
105 };
106
107 da9062_onkey: onkey {
108 compatible = "dlg,da9062-onkey";
109 };
110
111 watchdog {
112 compatible = "dlg,da9062-watchdog";
113 dlg,use-sw-pm;
114 };
115
116 regulators {
117 vdd_arm: buck1 {
118 regulator-name = "vdd_arm";
119 regulator-min-microvolt = <925000>;
120 regulator-max-microvolt = <1380000>;
121 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
122 regulator-always-on;
123 };
124
125 vdd_soc: buck2 {
126 regulator-name = "vdd_soc";
127 regulator-min-microvolt = <1150000>;
128 regulator-max-microvolt = <1380000>;
129 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
130 regulator-always-on;
131 };
132
133 vdd_ddr3_1p5: buck3 {
134 regulator-name = "vdd_ddr3";
135 regulator-min-microvolt = <1500000>;
136 regulator-max-microvolt = <1500000>;
137 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
138 regulator-always-on;
139 };
140
141 vdd_eth_1p2: buck4 {
142 regulator-name = "vdd_eth";
143 regulator-min-microvolt = <1200000>;
144 regulator-max-microvolt = <1200000>;
145 regulator-initial-mode = <DA9063_BUCK_MODE_SYNC>;
146 regulator-always-on;
147 };
148
149 vdd_snvs: ldo1 {
150 regulator-name = "vdd_snvs";
151 regulator-min-microvolt = <3000000>;
152 regulator-max-microvolt = <3000000>;
153 regulator-always-on;
154 };
155
156 vdd_high: ldo2 {
157 regulator-name = "vdd_high";
158 regulator-min-microvolt = <3000000>;
159 regulator-max-microvolt = <3000000>;
160 regulator-always-on;
161 };
162
163 vdd_eth_io: ldo3 {
164 regulator-name = "vdd_eth_io";
165 regulator-min-microvolt = <2500000>;
166 regulator-max-microvolt = <2500000>;
167 };
168
169 vdd_emmc_1p8: ldo4 {
170 regulator-name = "vdd_emmc";
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <1800000>;
173 };
174 };
175 };
176};
177
178®_arm {
179 vin-supply = <&vdd_arm>;
180};
181
182®_pu {
183 vin-supply = <&vdd_soc>;
184};
185
186®_soc {
187 vin-supply = <&vdd_soc>;
188};
189
190&snvs_poweroff {
191 status = "okay";
192};
193
194&usdhc4 {
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_usdhc4>;
197 bus-width = <8>;
198 non-removable;
199 status = "disabled";
200};
201
202&iomuxc {
203 pinctrl_enet: enetgrp {
204 fsl,pins = <
205 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
206 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
207 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
208 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
209 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
210 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
211 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
212 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
213 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
214 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
215 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
216 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
217 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
218 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
219 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
220 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
221 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
222 >;
223 };
224
225 pinctrl_gpioleds_som: gpioledssomgrp {
226 fsl,pins = <
227 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
228 >;
229 };
230
231 pinctrl_gpmi_nand: gpminandgrp {
232 fsl,pins = <
233 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
234 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
235 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
236 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
237 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
238 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
239 MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
240 MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
241 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
242 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
243 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
244 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
245 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
246 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
247 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
248 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
249 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
250 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
251 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
252 >;
253 };
254
255 pinctrl_i2c3: i2c3grp {
256 fsl,pins = <
257 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
258 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
259 >;
260 };
261
262 pinctrl_ecspi1: ecspi1grp {
263 fsl,pins = <
264 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
265 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
266 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
267 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
268 >;
269 };
270
271 pinctrl_pmic: pmicgrp {
272 fsl,pins = <
273 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
274 >;
275 };
276
277 pinctrl_usdhc4: usdhc4grp {
278 fsl,pins = <
279 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
280 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
281 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
282 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
283 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
284 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
285 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
286 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
287 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
288 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
289 >;
290 };
291};