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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree file for Cortina systems Gemini SoC
4 */
5
6/include/ "skeleton.dtsi"
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/clock/cortina,gemini-clock.h>
10#include <dt-bindings/reset/cortina,gemini-reset.h>
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14 soc {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges;
18 compatible = "simple-bus";
19 interrupt-parent = <&intcon>;
20
21 flash@30000000 {
22 compatible = "cortina,gemini-flash", "cfi-flash";
23 syscon = <&syscon>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&pflash_default_pins>;
26 bank-width = <2>;
27 #address-cells = <1>;
28 #size-cells = <1>;
29 status = "disabled";
30 };
31
32 syscon: syscon@40000000 {
33 compatible = "cortina,gemini-syscon",
34 "syscon", "simple-mfd";
35 reg = <0x40000000 0x1000>;
36 #clock-cells = <1>;
37 #reset-cells = <1>;
38
39 syscon-reboot {
40 compatible = "syscon-reboot";
41 regmap = <&syscon>;
42 /* GLOBAL_RESET register */
43 offset = <0x0c>;
44 /* RESET_GLOBAL | RESET_CPU1 */
45 mask = <0xC0000000>;
46 };
47
48 pinctrl {
49 compatible = "cortina,gemini-pinctrl";
50 regmap = <&syscon>;
51 /* Hog the DRAM pins */
52 pinctrl-names = "default";
53 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
54 <&vcontrol_default_pins>;
55
56 dram_default_pins: pinctrl-dram {
57 mux {
58 function = "dram";
59 groups = "dramgrp";
60 };
61 };
62 rtc_default_pins: pinctrl-rtc {
63 mux {
64 function = "rtc";
65 groups = "rtcgrp";
66 };
67 };
68 power_default_pins: pinctrl-power {
69 mux {
70 function = "power";
71 groups = "powergrp";
72 };
73 };
74 cir_default_pins: pinctrl-cir {
75 mux {
76 function = "cir";
77 groups = "cirgrp";
78 };
79 };
80 system_default_pins: pinctrl-system {
81 mux {
82 function = "system";
83 groups = "systemgrp";
84 };
85 };
86 vcontrol_default_pins: pinctrl-vcontrol {
87 mux {
88 function = "vcontrol";
89 groups = "vcontrolgrp";
90 };
91 };
92 ice_default_pins: pinctrl-ice {
93 mux {
94 function = "ice";
95 groups = "icegrp";
96 };
97 };
98 uart_default_pins: pinctrl-uart {
99 mux {
100 function = "uart";
101 groups = "uartrxtxgrp";
102 };
103 };
104 pflash_default_pins: pinctrl-pflash {
105 mux {
106 function = "pflash";
107 groups = "pflashgrp";
108 };
109 };
110 usb_default_pins: pinctrl-usb {
111 mux {
112 function = "usb";
113 groups = "usbgrp";
114 };
115 };
116 gmii_default_pins: pinctrl-gmii {
117 /*
118 * Only activate GMAC0 by default since
119 * GMAC1 will overlap with 8 GPIO lines
120 * gpio2a, gpio2b. Overlay groups with
121 * "gmii_gmac0_grp", "gmii_gmac1_grp" for
122 * both ethernet interfaces.
123 */
124 mux {
125 function = "gmii";
126 groups = "gmii_gmac0_grp";
127 };
128 };
129 pci_default_pins: pinctrl-pci {
130 mux {
131 function = "pci";
132 groups = "pcigrp";
133 };
134 };
135 sata_default_pins: pinctrl-sata {
136 mux {
137 function = "sata";
138 groups = "satagrp";
139 };
140 };
141 /* Activate both groups of pins for this state */
142 sata_and_ide_pins: pinctrl-sata-ide {
143 mux0 {
144 function = "sata";
145 groups = "satagrp";
146 };
147 mux1 {
148 function = "ide";
149 groups = "idegrp";
150 };
151 };
152 tvc_default_pins: pinctrl-tvc {
153 mux {
154 function = "tvc";
155 groups = "tvcgrp";
156 };
157 };
158 };
159 };
160
161 watchdog@41000000 {
162 compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
163 reg = <0x41000000 0x1000>;
164 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
165 resets = <&syscon GEMINI_RESET_WDOG>;
166 clocks = <&syscon GEMINI_CLK_APB>;
167 clock-names = "PCLK";
168 };
169
170 uart0: serial@42000000 {
171 compatible = "ns16550a";
172 reg = <0x42000000 0x100>;
173 resets = <&syscon GEMINI_RESET_UART>;
174 clocks = <&syscon GEMINI_CLK_UART>;
175 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&uart_default_pins>;
178 reg-shift = <2>;
179 };
180
181 timer@43000000 {
182 compatible = "faraday,fttmr010";
183 reg = <0x43000000 0x1000>;
184 interrupt-parent = <&intcon>;
185 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
186 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
187 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
188 resets = <&syscon GEMINI_RESET_TIMER>;
189 /* APB clock or RTC clock */
190 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
191 clock-names = "PCLK", "EXTCLK";
192 syscon = <&syscon>;
193 };
194
195 rtc@45000000 {
196 compatible = "cortina,gemini-rtc";
197 reg = <0x45000000 0x100>;
198 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
199 resets = <&syscon GEMINI_RESET_RTC>;
200 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
201 clock-names = "PCLK", "EXTCLK";
202 pinctrl-names = "default";
203 pinctrl-0 = <&rtc_default_pins>;
204 };
205
206 sata: sata@46000000 {
207 compatible = "cortina,gemini-sata-bridge";
208 reg = <0x46000000 0x100>;
209 resets = <&syscon GEMINI_RESET_SATA0>,
210 <&syscon GEMINI_RESET_SATA1>;
211 reset-names = "sata0", "sata1";
212 clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
213 <&syscon GEMINI_CLK_GATE_SATA1>;
214 clock-names = "SATA0_PCLK", "SATA1_PCLK";
215 /*
216 * This defines the special "ide" state that needs
217 * to be explicitly enabled to enable the IDE pins,
218 * as these pins are normally used for other things.
219 */
220 pinctrl-names = "default", "ide";
221 pinctrl-0 = <&sata_default_pins>;
222 pinctrl-1 = <&sata_and_ide_pins>;
223 syscon = <&syscon>;
224 status = "disabled";
225 };
226
227 intcon: interrupt-controller@48000000 {
228 compatible = "faraday,ftintc010";
229 reg = <0x48000000 0x1000>;
230 resets = <&syscon GEMINI_RESET_INTCON0>;
231 interrupt-controller;
232 #interrupt-cells = <2>;
233 };
234
235 power-controller@4b000000 {
236 compatible = "cortina,gemini-power-controller";
237 reg = <0x4b000000 0x100>;
238 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&power_default_pins>;
241 };
242
243 gpio0: gpio@4d000000 {
244 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
245 reg = <0x4d000000 0x100>;
246 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
247 resets = <&syscon GEMINI_RESET_GPIO0>;
248 clocks = <&syscon GEMINI_CLK_APB>;
249 gpio-controller;
250 #gpio-cells = <2>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 };
254
255 gpio1: gpio@4e000000 {
256 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
257 reg = <0x4e000000 0x100>;
258 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
259 resets = <&syscon GEMINI_RESET_GPIO1>;
260 clocks = <&syscon GEMINI_CLK_APB>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 };
266
267 gpio2: gpio@4f000000 {
268 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
269 reg = <0x4f000000 0x100>;
270 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
271 resets = <&syscon GEMINI_RESET_GPIO2>;
272 clocks = <&syscon GEMINI_CLK_APB>;
273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 };
278
279 pci@50000000 {
280 compatible = "cortina,gemini-pci", "faraday,ftpci100";
281 /*
282 * The first 256 bytes in the IO range is actually used
283 * to configure the host bridge.
284 */
285 reg = <0x50000000 0x100>;
286 resets = <&syscon GEMINI_RESET_PCI>;
287 clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
288 clock-names = "PCLK", "PCICLK";
289 pinctrl-names = "default";
290 pinctrl-0 = <&pci_default_pins>;
291 #address-cells = <3>;
292 #size-cells = <2>;
293 #interrupt-cells = <1>;
294 status = "disabled";
295
296 bus-range = <0x00 0xff>;
297 /* PCI ranges mappings */
298 ranges =
299 /* 1MiB I/O space 0x50000000-0x500fffff */
300 <0x01000000 0 0 0x50000000 0 0x00100000>,
301 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
302 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
303
304 /* DMA ranges */
305 dma-ranges =
306 /* 128MiB at 0x00000000-0x07ffffff */
307 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
308 /* 64MiB at 0x00000000-0x03ffffff */
309 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
310 /* 64MiB at 0x00000000-0x03ffffff */
311 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
312
313 /*
314 * This PCI host bridge variant has a cascaded interrupt
315 * controller embedded in the host bridge.
316 */
317 pci_intc: interrupt-controller {
318 interrupt-parent = <&intcon>;
319 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
320 interrupt-controller;
321 #address-cells = <0>;
322 #interrupt-cells = <1>;
323 };
324 };
325
326 ethernet@60000000 {
327 compatible = "cortina,gemini-ethernet";
328 reg = <0x60000000 0x4000>, /* Global registers, queue */
329 <0x60004000 0x2000>, /* V-bit */
330 <0x60006000 0x2000>; /* A-bit */
331 pinctrl-names = "default";
332 pinctrl-0 = <&gmii_default_pins>;
333 status = "disabled";
334 #address-cells = <1>;
335 #size-cells = <1>;
336 ranges;
337
338 gmac0: ethernet-port@0 {
339 compatible = "cortina,gemini-ethernet-port";
340 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
341 <0x6000a000 0x2000>; /* Port 0 GMAC */
342 interrupt-parent = <&intcon>;
343 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
344 resets = <&syscon GEMINI_RESET_GMAC0>;
345 clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
346 clock-names = "PCLK";
347 };
348
349 gmac1: ethernet-port@1 {
350 compatible = "cortina,gemini-ethernet-port";
351 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
352 <0x6000e000 0x2000>; /* Port 1 GMAC */
353 interrupt-parent = <&intcon>;
354 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
355 resets = <&syscon GEMINI_RESET_GMAC1>;
356 clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
357 clock-names = "PCLK";
358 };
359 };
360
361 ata@63000000 {
362 compatible = "cortina,gemini-pata", "faraday,ftide010";
363 reg = <0x63000000 0x1000>;
364 interrupts = <4 IRQ_TYPE_EDGE_RISING>;
365 resets = <&syscon GEMINI_RESET_IDE>;
366 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
367 clock-names = "PCLK";
368 sata = <&sata>;
369 status = "disabled";
370 };
371
372 ata@63400000 {
373 compatible = "cortina,gemini-pata", "faraday,ftide010";
374 reg = <0x63400000 0x1000>;
375 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
376 resets = <&syscon GEMINI_RESET_IDE>;
377 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
378 clock-names = "PCLK";
379 sata = <&sata>;
380 status = "disabled";
381 };
382
383 dma-controller@67000000 {
384 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
385 /* Faraday Technology FTDMAC020 variant */
386 arm,primecell-periphid = <0x0003b080>;
387 reg = <0x67000000 0x1000>;
388 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
389 resets = <&syscon GEMINI_RESET_DMAC>;
390 clocks = <&syscon GEMINI_CLK_AHB>;
391 clock-names = "apb_pclk";
392 /* Bus interface AHB1 (AHB0) is totally tilted */
393 lli-bus-interface-ahb2;
394 mem-bus-interface-ahb2;
395 memcpy-burst-size = <256>;
396 memcpy-bus-width = <32>;
397 #dma-cells = <2>;
398 };
399
400 display-controller@6a000000 {
401 compatible = "cortina,gemini-tvc", "faraday,tve200";
402 reg = <0x6a000000 0x1000>;
403 interrupts = <13 IRQ_TYPE_EDGE_RISING>;
404 resets = <&syscon GEMINI_RESET_TVC>;
405 clocks = <&syscon GEMINI_CLK_GATE_TVC>,
406 <&syscon GEMINI_CLK_TVC>;
407 clock-names = "PCLK", "TVE";
408 pinctrl-names = "default";
409 pinctrl-0 = <&tvc_default_pins>;
410 #address-cells = <1>;
411 #size-cells = <0>;
412 status = "disabled";
413 };
414 };
415};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree file for Cortina systems Gemini SoC
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/clock/cortina,gemini-clock.h>
8#include <dt-bindings/reset/cortina,gemini-reset.h>
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 soc {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 ranges;
16 compatible = "simple-bus";
17 interrupt-parent = <&intcon>;
18
19 flash@30000000 {
20 compatible = "cortina,gemini-flash", "cfi-flash";
21 syscon = <&syscon>;
22 pinctrl-names = "default";
23 pinctrl-0 = <&pflash_default_pins>;
24 bank-width = <2>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 status = "disabled";
28 };
29
30 syscon: syscon@40000000 {
31 compatible = "cortina,gemini-syscon",
32 "syscon", "simple-mfd";
33 reg = <0x40000000 0x1000>;
34 #clock-cells = <1>;
35 #reset-cells = <1>;
36
37 syscon-reboot {
38 compatible = "syscon-reboot";
39 regmap = <&syscon>;
40 /* GLOBAL_RESET register */
41 offset = <0x0c>;
42 /* RESET_GLOBAL | RESET_CPU1 */
43 mask = <0xC0000000>;
44 };
45
46 pinctrl {
47 compatible = "cortina,gemini-pinctrl";
48 regmap = <&syscon>;
49 /* Hog the DRAM pins */
50 pinctrl-names = "default";
51 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
52 <&vcontrol_default_pins>;
53
54 dram_default_pins: pinctrl-dram {
55 mux {
56 function = "dram";
57 groups = "dramgrp";
58 };
59 };
60 rtc_default_pins: pinctrl-rtc {
61 mux {
62 function = "rtc";
63 groups = "rtcgrp";
64 };
65 };
66 power_default_pins: pinctrl-power {
67 mux {
68 function = "power";
69 groups = "powergrp";
70 };
71 };
72 cir_default_pins: pinctrl-cir {
73 mux {
74 function = "cir";
75 groups = "cirgrp";
76 };
77 };
78 system_default_pins: pinctrl-system {
79 mux {
80 function = "system";
81 groups = "systemgrp";
82 };
83 };
84 vcontrol_default_pins: pinctrl-vcontrol {
85 mux {
86 function = "vcontrol";
87 groups = "vcontrolgrp";
88 };
89 };
90 ice_default_pins: pinctrl-ice {
91 mux {
92 function = "ice";
93 groups = "icegrp";
94 };
95 };
96 uart_default_pins: pinctrl-uart {
97 mux {
98 function = "uart";
99 groups = "uartrxtxgrp";
100 };
101 };
102 pflash_default_pins: pinctrl-pflash {
103 mux {
104 function = "pflash";
105 groups = "pflashgrp";
106 };
107 };
108 usb_default_pins: pinctrl-usb {
109 mux {
110 function = "usb";
111 groups = "usbgrp";
112 };
113 };
114 gmii_default_pins: pinctrl-gmii {
115 /*
116 * Only activate GMAC0 by default since
117 * GMAC1 will overlap with 8 GPIO lines
118 * gpio2a, gpio2b. Overlay groups with
119 * "gmii_gmac0_grp", "gmii_gmac1_grp" for
120 * both ethernet interfaces.
121 */
122 mux {
123 function = "gmii";
124 groups = "gmii_gmac0_grp";
125 };
126 };
127 pci_default_pins: pinctrl-pci {
128 mux {
129 function = "pci";
130 groups = "pcigrp";
131 };
132 };
133 sata_default_pins: pinctrl-sata {
134 mux {
135 function = "sata";
136 groups = "satagrp";
137 };
138 };
139 /* Activate both groups of pins for this state */
140 sata_and_ide_pins: pinctrl-sata-ide {
141 mux0 {
142 function = "sata";
143 groups = "satagrp";
144 };
145 mux1 {
146 function = "ide";
147 groups = "idegrp";
148 };
149 };
150 tvc_default_pins: pinctrl-tvc {
151 mux {
152 function = "tvc";
153 groups = "tvcgrp";
154 };
155 };
156 };
157 };
158
159 watchdog@41000000 {
160 compatible = "cortina,gemini-watchdog", "faraday,ftwdt010";
161 reg = <0x41000000 0x1000>;
162 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
163 resets = <&syscon GEMINI_RESET_WDOG>;
164 clocks = <&syscon GEMINI_CLK_APB>;
165 clock-names = "PCLK";
166 };
167
168 uart0: serial@42000000 {
169 compatible = "ns16550a";
170 reg = <0x42000000 0x100>;
171 resets = <&syscon GEMINI_RESET_UART>;
172 clocks = <&syscon GEMINI_CLK_UART>;
173 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&uart_default_pins>;
176 reg-shift = <2>;
177 };
178
179 timer@43000000 {
180 compatible = "faraday,fttmr010";
181 reg = <0x43000000 0x1000>;
182 interrupt-parent = <&intcon>;
183 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */
184 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */
185 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */
186 resets = <&syscon GEMINI_RESET_TIMER>;
187 /* APB clock or RTC clock */
188 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
189 clock-names = "PCLK", "EXTCLK";
190 syscon = <&syscon>;
191 };
192
193 rtc@45000000 {
194 compatible = "cortina,gemini-rtc", "faraday,ftrtc010";
195 reg = <0x45000000 0x100>;
196 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
197 resets = <&syscon GEMINI_RESET_RTC>;
198 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>;
199 clock-names = "PCLK", "EXTCLK";
200 pinctrl-names = "default";
201 pinctrl-0 = <&rtc_default_pins>;
202 };
203
204 sata: sata@46000000 {
205 compatible = "cortina,gemini-sata-bridge";
206 reg = <0x46000000 0x100>;
207 resets = <&syscon GEMINI_RESET_SATA0>,
208 <&syscon GEMINI_RESET_SATA1>;
209 reset-names = "sata0", "sata1";
210 clocks = <&syscon GEMINI_CLK_GATE_SATA0>,
211 <&syscon GEMINI_CLK_GATE_SATA1>;
212 clock-names = "SATA0_PCLK", "SATA1_PCLK";
213 /*
214 * This defines the special "ide" state that needs
215 * to be explicitly enabled to enable the IDE pins,
216 * as these pins are normally used for other things.
217 */
218 pinctrl-names = "default", "ide";
219 pinctrl-0 = <&sata_default_pins>;
220 pinctrl-1 = <&sata_and_ide_pins>;
221 syscon = <&syscon>;
222 status = "disabled";
223 };
224
225 intcon: interrupt-controller@48000000 {
226 compatible = "faraday,ftintc010";
227 reg = <0x48000000 0x1000>;
228 resets = <&syscon GEMINI_RESET_INTCON0>;
229 interrupt-controller;
230 #interrupt-cells = <2>;
231 };
232
233 power-controller@4b000000 {
234 compatible = "cortina,gemini-power-controller";
235 reg = <0x4b000000 0x100>;
236 interrupts = <26 IRQ_TYPE_EDGE_RISING>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&power_default_pins>;
239 };
240
241 gpio0: gpio@4d000000 {
242 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
243 reg = <0x4d000000 0x100>;
244 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
245 resets = <&syscon GEMINI_RESET_GPIO0>;
246 clocks = <&syscon GEMINI_CLK_APB>;
247 gpio-controller;
248 #gpio-cells = <2>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
252
253 gpio1: gpio@4e000000 {
254 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
255 reg = <0x4e000000 0x100>;
256 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
257 resets = <&syscon GEMINI_RESET_GPIO1>;
258 clocks = <&syscon GEMINI_CLK_APB>;
259 gpio-controller;
260 #gpio-cells = <2>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 };
264
265 gpio2: gpio@4f000000 {
266 compatible = "cortina,gemini-gpio", "faraday,ftgpio010";
267 reg = <0x4f000000 0x100>;
268 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
269 resets = <&syscon GEMINI_RESET_GPIO2>;
270 clocks = <&syscon GEMINI_CLK_APB>;
271 gpio-controller;
272 #gpio-cells = <2>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 };
276
277 pci@50000000 {
278 compatible = "cortina,gemini-pci", "faraday,ftpci100";
279 /*
280 * The first 256 bytes in the IO range is actually used
281 * to configure the host bridge.
282 */
283 reg = <0x50000000 0x100>;
284 resets = <&syscon GEMINI_RESET_PCI>;
285 clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>;
286 clock-names = "PCLK", "PCICLK";
287 pinctrl-names = "default";
288 pinctrl-0 = <&pci_default_pins>;
289 device_type = "pci";
290 #address-cells = <3>;
291 #size-cells = <2>;
292 #interrupt-cells = <1>;
293 status = "disabled";
294
295 bus-range = <0x00 0xff>;
296 /* PCI ranges mappings */
297 ranges =
298 /* 1MiB I/O space 0x50000000-0x500fffff */
299 <0x01000000 0 0 0x50000000 0 0x00100000>,
300 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
301 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
302
303 /* DMA ranges */
304 dma-ranges =
305 /* 128MiB at 0x00000000-0x07ffffff */
306 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
307 /* 64MiB at 0x00000000-0x03ffffff */
308 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
309 /* 64MiB at 0x00000000-0x03ffffff */
310 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
311
312 /*
313 * This PCI host bridge variant has a cascaded interrupt
314 * controller embedded in the host bridge.
315 */
316 pci_intc: interrupt-controller {
317 interrupt-parent = <&intcon>;
318 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
319 interrupt-controller;
320 #address-cells = <0>;
321 #interrupt-cells = <1>;
322 };
323 };
324
325 ethernet@60000000 {
326 compatible = "cortina,gemini-ethernet";
327 reg = <0x60000000 0x4000>, /* Global registers, queue */
328 <0x60004000 0x2000>, /* V-bit */
329 <0x60006000 0x2000>; /* A-bit */
330 pinctrl-names = "default";
331 pinctrl-0 = <&gmii_default_pins>;
332 status = "disabled";
333 #address-cells = <1>;
334 #size-cells = <1>;
335 ranges;
336
337 gmac0: ethernet-port@0 {
338 compatible = "cortina,gemini-ethernet-port";
339 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
340 <0x6000a000 0x2000>; /* Port 0 GMAC */
341 interrupt-parent = <&intcon>;
342 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
343 resets = <&syscon GEMINI_RESET_GMAC0>;
344 clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
345 clock-names = "PCLK";
346 };
347
348 gmac1: ethernet-port@1 {
349 compatible = "cortina,gemini-ethernet-port";
350 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
351 <0x6000e000 0x2000>; /* Port 1 GMAC */
352 interrupt-parent = <&intcon>;
353 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
354 resets = <&syscon GEMINI_RESET_GMAC1>;
355 clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
356 clock-names = "PCLK";
357 };
358 };
359
360 crypto: crypto@62000000 {
361 compatible = "cortina,sl3516-crypto";
362 reg = <0x62000000 0x10000>;
363 interrupts = <7 IRQ_TYPE_EDGE_RISING>;
364 resets = <&syscon GEMINI_RESET_SECURITY>;
365 clocks = <&syscon GEMINI_CLK_GATE_SECURITY>;
366 };
367
368 ide@63000000 {
369 compatible = "cortina,gemini-pata", "faraday,ftide010";
370 reg = <0x63000000 0x1000>;
371 interrupts = <4 IRQ_TYPE_EDGE_RISING>;
372 resets = <&syscon GEMINI_RESET_IDE>;
373 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
374 clock-names = "PCLK";
375 sata = <&sata>;
376 status = "disabled";
377 #address-cells = <1>;
378 #size-cells = <0>;
379 };
380
381 ide@63400000 {
382 compatible = "cortina,gemini-pata", "faraday,ftide010";
383 reg = <0x63400000 0x1000>;
384 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
385 resets = <&syscon GEMINI_RESET_IDE>;
386 clocks = <&syscon GEMINI_CLK_GATE_IDE>;
387 clock-names = "PCLK";
388 sata = <&sata>;
389 status = "disabled";
390 #address-cells = <1>;
391 #size-cells = <0>;
392 };
393
394 dma-controller@67000000 {
395 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
396 /* Faraday Technology FTDMAC020 variant */
397 arm,primecell-periphid = <0x0003b080>;
398 reg = <0x67000000 0x1000>;
399 interrupts = <9 IRQ_TYPE_EDGE_RISING>;
400 resets = <&syscon GEMINI_RESET_DMAC>;
401 clocks = <&syscon GEMINI_CLK_AHB>;
402 clock-names = "apb_pclk";
403 /* Bus interface AHB1 (AHB0) is totally tilted */
404 lli-bus-interface-ahb2;
405 mem-bus-interface-ahb2;
406 memcpy-burst-size = <256>;
407 memcpy-bus-width = <32>;
408 #dma-cells = <2>;
409 };
410
411 display-controller@6a000000 {
412 compatible = "cortina,gemini-tvc", "faraday,tve200";
413 reg = <0x6a000000 0x1000>;
414 interrupts = <13 IRQ_TYPE_EDGE_RISING>;
415 resets = <&syscon GEMINI_RESET_TVC>;
416 clocks = <&syscon GEMINI_CLK_GATE_TVC>,
417 <&syscon GEMINI_CLK_TVC>;
418 clock-names = "PCLK", "TVE";
419 pinctrl-names = "default";
420 pinctrl-0 = <&tvc_default_pins>;
421 status = "disabled";
422 };
423
424 usb@68000000 {
425 compatible = "cortina,gemini-usb", "faraday,fotg210";
426 reg = <0x68000000 0x1000>;
427 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
428 resets = <&syscon GEMINI_RESET_USB0>;
429 clocks = <&syscon GEMINI_CLK_GATE_USB0>;
430 clock-names = "PCLK";
431 /*
432 * This will claim pins for USB0 and USB1 at the same
433 * time as they are using some common pins. If you for
434 * some reason have a system using USB1 at 96000000 but
435 * NOT using USB0 at 68000000 you wll have to add the
436 * usb_default_pins to the USB controller at 96000000
437 * in your .dts for the board.
438 */
439 pinctrl-names = "default";
440 pinctrl-0 = <&usb_default_pins>;
441 syscon = <&syscon>;
442 status = "disabled";
443 };
444
445 usb@69000000 {
446 compatible = "cortina,gemini-usb", "faraday,fotg210";
447 reg = <0x69000000 0x1000>;
448 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
449 resets = <&syscon GEMINI_RESET_USB1>;
450 clocks = <&syscon GEMINI_CLK_GATE_USB1>;
451 clock-names = "PCLK";
452 syscon = <&syscon>;
453 status = "disabled";
454 };
455 };
456};