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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4412 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
14 * nodes can be added to this file.
15 */
16
17#include "exynos4.dtsi"
18
19#include "exynos4-cpu-thermal.dtsi"
20
21/ {
22 compatible = "samsung,exynos4412", "samsung,exynos4";
23
24 aliases {
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
31 mshc0 = &mshc_0;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu0: cpu@a00 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a9";
41 reg = <0xA00>;
42 clocks = <&clock CLK_ARM_CLK>;
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
46 };
47
48 cpu@a01 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a9";
51 reg = <0xA01>;
52 operating-points-v2 = <&cpu0_opp_table>;
53 };
54
55 cpu@a02 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a9";
58 reg = <0xA02>;
59 operating-points-v2 = <&cpu0_opp_table>;
60 };
61
62 cpu@a03 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a9";
65 reg = <0xA03>;
66 operating-points-v2 = <&cpu0_opp_table>;
67 };
68 };
69
70 cpu0_opp_table: opp_table0 {
71 compatible = "operating-points-v2";
72 opp-shared;
73
74 opp-200000000 {
75 opp-hz = /bits/ 64 <200000000>;
76 opp-microvolt = <900000>;
77 clock-latency-ns = <200000>;
78 };
79 opp-300000000 {
80 opp-hz = /bits/ 64 <300000000>;
81 opp-microvolt = <900000>;
82 clock-latency-ns = <200000>;
83 };
84 opp-400000000 {
85 opp-hz = /bits/ 64 <400000000>;
86 opp-microvolt = <925000>;
87 clock-latency-ns = <200000>;
88 };
89 opp-500000000 {
90 opp-hz = /bits/ 64 <500000000>;
91 opp-microvolt = <950000>;
92 clock-latency-ns = <200000>;
93 };
94 opp-600000000 {
95 opp-hz = /bits/ 64 <600000000>;
96 opp-microvolt = <975000>;
97 clock-latency-ns = <200000>;
98 };
99 opp-700000000 {
100 opp-hz = /bits/ 64 <700000000>;
101 opp-microvolt = <987500>;
102 clock-latency-ns = <200000>;
103 };
104 opp-800000000 {
105 opp-hz = /bits/ 64 <800000000>;
106 opp-microvolt = <1000000>;
107 clock-latency-ns = <200000>;
108 opp-suspend;
109 };
110 opp-900000000 {
111 opp-hz = /bits/ 64 <900000000>;
112 opp-microvolt = <1037500>;
113 clock-latency-ns = <200000>;
114 };
115 opp-1000000000 {
116 opp-hz = /bits/ 64 <1000000000>;
117 opp-microvolt = <1087500>;
118 clock-latency-ns = <200000>;
119 };
120 opp-1100000000 {
121 opp-hz = /bits/ 64 <1100000000>;
122 opp-microvolt = <1137500>;
123 clock-latency-ns = <200000>;
124 };
125 opp-1200000000 {
126 opp-hz = /bits/ 64 <1200000000>;
127 opp-microvolt = <1187500>;
128 clock-latency-ns = <200000>;
129 };
130 opp-1300000000 {
131 opp-hz = /bits/ 64 <1300000000>;
132 opp-microvolt = <1250000>;
133 clock-latency-ns = <200000>;
134 };
135 opp-1400000000 {
136 opp-hz = /bits/ 64 <1400000000>;
137 opp-microvolt = <1287500>;
138 clock-latency-ns = <200000>;
139 };
140 cpu0_opp_1500: opp-1500000000 {
141 opp-hz = /bits/ 64 <1500000000>;
142 opp-microvolt = <1350000>;
143 clock-latency-ns = <200000>;
144 turbo-mode;
145 };
146 };
147
148
149 soc: soc {
150
151 pinctrl_0: pinctrl@11400000 {
152 compatible = "samsung,exynos4x12-pinctrl";
153 reg = <0x11400000 0x1000>;
154 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
155 };
156
157 pinctrl_1: pinctrl@11000000 {
158 compatible = "samsung,exynos4x12-pinctrl";
159 reg = <0x11000000 0x1000>;
160 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
161
162 wakup_eint: wakeup-interrupt-controller {
163 compatible = "samsung,exynos4210-wakeup-eint";
164 interrupt-parent = <&gic>;
165 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
166 };
167 };
168
169 pinctrl_2: pinctrl@3860000 {
170 compatible = "samsung,exynos4x12-pinctrl";
171 reg = <0x03860000 0x1000>;
172 interrupt-parent = <&combiner>;
173 interrupts = <10 0>;
174 };
175
176 pinctrl_3: pinctrl@106e0000 {
177 compatible = "samsung,exynos4x12-pinctrl";
178 reg = <0x106E0000 0x1000>;
179 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
180 };
181
182 sysram@2020000 {
183 compatible = "mmio-sram";
184 reg = <0x02020000 0x40000>;
185 #address-cells = <1>;
186 #size-cells = <1>;
187 ranges = <0 0x02020000 0x40000>;
188
189 smp-sysram@0 {
190 compatible = "samsung,exynos4210-sysram";
191 reg = <0x0 0x1000>;
192 };
193
194 smp-sysram@2f000 {
195 compatible = "samsung,exynos4210-sysram-ns";
196 reg = <0x2f000 0x1000>;
197 };
198 };
199
200 pd_isp: isp-power-domain@10023ca0 {
201 compatible = "samsung,exynos4210-pd";
202 reg = <0x10023CA0 0x20>;
203 #power-domain-cells = <0>;
204 label = "ISP";
205 };
206
207 l2c: l2-cache-controller@10502000 {
208 compatible = "arm,pl310-cache";
209 reg = <0x10502000 0x1000>;
210 cache-unified;
211 cache-level = <2>;
212 arm,tag-latency = <2 2 1>;
213 arm,data-latency = <3 2 1>;
214 arm,double-linefill = <1>;
215 arm,double-linefill-incr = <0>;
216 arm,double-linefill-wrap = <1>;
217 arm,prefetch-drop = <1>;
218 arm,prefetch-offset = <7>;
219 };
220
221 clock: clock-controller@10030000 {
222 compatible = "samsung,exynos4412-clock";
223 reg = <0x10030000 0x18000>;
224 #clock-cells = <1>;
225 };
226
227 isp_clock: clock-controller@10048000 {
228 compatible = "samsung,exynos4412-isp-clock";
229 reg = <0x10048000 0x1000>;
230 #clock-cells = <1>;
231 power-domains = <&pd_isp>;
232 clocks = <&clock CLK_ACLK200>,
233 <&clock CLK_ACLK400_MCUISP>;
234 clock-names = "aclk200", "aclk400_mcuisp";
235 };
236
237 mct@10050000 {
238 compatible = "samsung,exynos4412-mct";
239 reg = <0x10050000 0x800>;
240 interrupt-parent = <&mct_map>;
241 interrupts = <0>, <1>, <2>, <3>, <4>;
242 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
243 clock-names = "fin_pll", "mct";
244
245 mct_map: mct-map {
246 #interrupt-cells = <1>;
247 #address-cells = <0>;
248 #size-cells = <0>;
249 interrupt-map =
250 <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
251 <1 &combiner 12 5>,
252 <2 &combiner 12 6>,
253 <3 &combiner 12 7>,
254 <4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
255 };
256 };
257
258 watchdog: watchdog@10060000 {
259 compatible = "samsung,exynos5250-wdt";
260 reg = <0x10060000 0x100>;
261 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&clock CLK_WDT>;
263 clock-names = "watchdog";
264 samsung,syscon-phandle = <&pmu_system_controller>;
265 };
266
267 adc: adc@126c0000 {
268 compatible = "samsung,exynos-adc-v1";
269 reg = <0x126C0000 0x100>;
270 interrupt-parent = <&combiner>;
271 interrupts = <10 3>;
272 clocks = <&clock CLK_TSADC>;
273 clock-names = "adc";
274 #io-channel-cells = <1>;
275 io-channel-ranges;
276 samsung,syscon-phandle = <&pmu_system_controller>;
277 status = "disabled";
278 };
279
280 g2d: g2d@10800000 {
281 compatible = "samsung,exynos4212-g2d";
282 reg = <0x10800000 0x1000>;
283 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
285 clock-names = "sclk_fimg2d", "fimg2d";
286 iommus = <&sysmmu_g2d>;
287 };
288
289 mshc_0: mmc@12550000 {
290 compatible = "samsung,exynos4412-dw-mshc";
291 reg = <0x12550000 0x1000>;
292 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 fifo-depth = <0x80>;
296 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
297 clock-names = "biu", "ciu";
298 status = "disabled";
299 };
300
301 sysmmu_g2d: sysmmu@10A40000{
302 compatible = "samsung,exynos-sysmmu";
303 reg = <0x10A40000 0x1000>;
304 interrupt-parent = <&combiner>;
305 interrupts = <4 7>;
306 clock-names = "sysmmu", "master";
307 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
308 #iommu-cells = <0>;
309 };
310
311 sysmmu_fimc_isp: sysmmu@12260000 {
312 compatible = "samsung,exynos-sysmmu";
313 reg = <0x12260000 0x1000>;
314 interrupt-parent = <&combiner>;
315 interrupts = <16 2>;
316 power-domains = <&pd_isp>;
317 clock-names = "sysmmu";
318 clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
319 #iommu-cells = <0>;
320 };
321
322 sysmmu_fimc_drc: sysmmu@12270000 {
323 compatible = "samsung,exynos-sysmmu";
324 reg = <0x12270000 0x1000>;
325 interrupt-parent = <&combiner>;
326 interrupts = <16 3>;
327 power-domains = <&pd_isp>;
328 clock-names = "sysmmu";
329 clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
330 #iommu-cells = <0>;
331 };
332
333 sysmmu_fimc_fd: sysmmu@122a0000 {
334 compatible = "samsung,exynos-sysmmu";
335 reg = <0x122A0000 0x1000>;
336 interrupt-parent = <&combiner>;
337 interrupts = <16 4>;
338 power-domains = <&pd_isp>;
339 clock-names = "sysmmu";
340 clocks = <&isp_clock CLK_ISP_SMMU_FD>;
341 #iommu-cells = <0>;
342 };
343
344 sysmmu_fimc_mcuctl: sysmmu@122b0000 {
345 compatible = "samsung,exynos-sysmmu";
346 reg = <0x122B0000 0x1000>;
347 interrupt-parent = <&combiner>;
348 interrupts = <16 5>;
349 power-domains = <&pd_isp>;
350 clock-names = "sysmmu";
351 clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
352 #iommu-cells = <0>;
353 };
354
355 sysmmu_fimc_lite0: sysmmu@123b0000 {
356 compatible = "samsung,exynos-sysmmu";
357 reg = <0x123B0000 0x1000>;
358 interrupt-parent = <&combiner>;
359 interrupts = <16 0>;
360 power-domains = <&pd_isp>;
361 clock-names = "sysmmu", "master";
362 clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
363 <&isp_clock CLK_ISP_FIMC_LITE0>;
364 #iommu-cells = <0>;
365 };
366
367 sysmmu_fimc_lite1: sysmmu@123c0000 {
368 compatible = "samsung,exynos-sysmmu";
369 reg = <0x123C0000 0x1000>;
370 interrupt-parent = <&combiner>;
371 interrupts = <16 1>;
372 power-domains = <&pd_isp>;
373 clock-names = "sysmmu", "master";
374 clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
375 <&isp_clock CLK_ISP_FIMC_LITE1>;
376 #iommu-cells = <0>;
377 };
378
379 bus_dmc: bus_dmc {
380 compatible = "samsung,exynos-bus";
381 clocks = <&clock CLK_DIV_DMC>;
382 clock-names = "bus";
383 operating-points-v2 = <&bus_dmc_opp_table>;
384 status = "disabled";
385 };
386
387 bus_acp: bus_acp {
388 compatible = "samsung,exynos-bus";
389 clocks = <&clock CLK_DIV_ACP>;
390 clock-names = "bus";
391 operating-points-v2 = <&bus_acp_opp_table>;
392 status = "disabled";
393 };
394
395 bus_c2c: bus_c2c {
396 compatible = "samsung,exynos-bus";
397 clocks = <&clock CLK_DIV_C2C>;
398 clock-names = "bus";
399 operating-points-v2 = <&bus_dmc_opp_table>;
400 status = "disabled";
401 };
402
403 bus_dmc_opp_table: opp_table1 {
404 compatible = "operating-points-v2";
405 opp-shared;
406
407 opp-100000000 {
408 opp-hz = /bits/ 64 <100000000>;
409 opp-microvolt = <900000>;
410 };
411 opp-134000000 {
412 opp-hz = /bits/ 64 <134000000>;
413 opp-microvolt = <900000>;
414 };
415 opp-160000000 {
416 opp-hz = /bits/ 64 <160000000>;
417 opp-microvolt = <900000>;
418 };
419 opp-267000000 {
420 opp-hz = /bits/ 64 <267000000>;
421 opp-microvolt = <950000>;
422 };
423 opp-400000000 {
424 opp-hz = /bits/ 64 <400000000>;
425 opp-microvolt = <1050000>;
426 };
427 };
428
429 bus_acp_opp_table: opp_table2 {
430 compatible = "operating-points-v2";
431 opp-shared;
432
433 opp-100000000 {
434 opp-hz = /bits/ 64 <100000000>;
435 };
436 opp-134000000 {
437 opp-hz = /bits/ 64 <134000000>;
438 };
439 opp-160000000 {
440 opp-hz = /bits/ 64 <160000000>;
441 };
442 opp-267000000 {
443 opp-hz = /bits/ 64 <267000000>;
444 };
445 };
446
447 bus_leftbus: bus_leftbus {
448 compatible = "samsung,exynos-bus";
449 clocks = <&clock CLK_DIV_GDL>;
450 clock-names = "bus";
451 operating-points-v2 = <&bus_leftbus_opp_table>;
452 status = "disabled";
453 };
454
455 bus_rightbus: bus_rightbus {
456 compatible = "samsung,exynos-bus";
457 clocks = <&clock CLK_DIV_GDR>;
458 clock-names = "bus";
459 operating-points-v2 = <&bus_leftbus_opp_table>;
460 status = "disabled";
461 };
462
463 bus_display: bus_display {
464 compatible = "samsung,exynos-bus";
465 clocks = <&clock CLK_ACLK160>;
466 clock-names = "bus";
467 operating-points-v2 = <&bus_display_opp_table>;
468 status = "disabled";
469 };
470
471 bus_fsys: bus_fsys {
472 compatible = "samsung,exynos-bus";
473 clocks = <&clock CLK_ACLK133>;
474 clock-names = "bus";
475 operating-points-v2 = <&bus_fsys_opp_table>;
476 status = "disabled";
477 };
478
479 bus_peri: bus_peri {
480 compatible = "samsung,exynos-bus";
481 clocks = <&clock CLK_ACLK100>;
482 clock-names = "bus";
483 operating-points-v2 = <&bus_peri_opp_table>;
484 status = "disabled";
485 };
486
487 bus_mfc: bus_mfc {
488 compatible = "samsung,exynos-bus";
489 clocks = <&clock CLK_SCLK_MFC>;
490 clock-names = "bus";
491 operating-points-v2 = <&bus_leftbus_opp_table>;
492 status = "disabled";
493 };
494
495 bus_leftbus_opp_table: opp_table3 {
496 compatible = "operating-points-v2";
497 opp-shared;
498
499 opp-100000000 {
500 opp-hz = /bits/ 64 <100000000>;
501 opp-microvolt = <900000>;
502 };
503 opp-134000000 {
504 opp-hz = /bits/ 64 <134000000>;
505 opp-microvolt = <925000>;
506 };
507 opp-160000000 {
508 opp-hz = /bits/ 64 <160000000>;
509 opp-microvolt = <950000>;
510 };
511 opp-200000000 {
512 opp-hz = /bits/ 64 <200000000>;
513 opp-microvolt = <1000000>;
514 };
515 };
516
517 bus_display_opp_table: opp_table4 {
518 compatible = "operating-points-v2";
519 opp-shared;
520
521 opp-160000000 {
522 opp-hz = /bits/ 64 <160000000>;
523 };
524 opp-200000000 {
525 opp-hz = /bits/ 64 <200000000>;
526 };
527 };
528
529 bus_fsys_opp_table: opp_table5 {
530 compatible = "operating-points-v2";
531 opp-shared;
532
533 opp-100000000 {
534 opp-hz = /bits/ 64 <100000000>;
535 };
536 opp-134000000 {
537 opp-hz = /bits/ 64 <134000000>;
538 };
539 };
540
541 bus_peri_opp_table: opp_table6 {
542 compatible = "operating-points-v2";
543 opp-shared;
544
545 opp-50000000 {
546 opp-hz = /bits/ 64 <50000000>;
547 };
548 opp-100000000 {
549 opp-hz = /bits/ 64 <100000000>;
550 };
551 };
552 };
553};
554
555&combiner {
556 samsung,combiner-nr = <20>;
557 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
577};
578
579&camera {
580 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
581 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
582 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
583
584 /* fimc_[0-3] are configured outside, under phandles */
585 fimc_lite_0: fimc-lite@12390000 {
586 compatible = "samsung,exynos4212-fimc-lite";
587 reg = <0x12390000 0x1000>;
588 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
589 power-domains = <&pd_isp>;
590 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
591 clock-names = "flite";
592 iommus = <&sysmmu_fimc_lite0>;
593 status = "disabled";
594 };
595
596 fimc_lite_1: fimc-lite@123a0000 {
597 compatible = "samsung,exynos4212-fimc-lite";
598 reg = <0x123A0000 0x1000>;
599 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
600 power-domains = <&pd_isp>;
601 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
602 clock-names = "flite";
603 iommus = <&sysmmu_fimc_lite1>;
604 status = "disabled";
605 };
606
607 fimc_is: fimc-is@12000000 {
608 compatible = "samsung,exynos4212-fimc-is";
609 reg = <0x12000000 0x260000>;
610 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
612 power-domains = <&pd_isp>;
613 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
614 <&isp_clock CLK_ISP_FIMC_LITE1>,
615 <&isp_clock CLK_ISP_PPMUISPX>,
616 <&isp_clock CLK_ISP_PPMUISPMX>,
617 <&isp_clock CLK_ISP_FIMC_ISP>,
618 <&isp_clock CLK_ISP_FIMC_DRC>,
619 <&isp_clock CLK_ISP_FIMC_FD>,
620 <&isp_clock CLK_ISP_MCUISP>,
621 <&isp_clock CLK_ISP_GICISP>,
622 <&isp_clock CLK_ISP_MCUCTL_ISP>,
623 <&isp_clock CLK_ISP_PWM_ISP>,
624 <&isp_clock CLK_ISP_DIV_ISP0>,
625 <&isp_clock CLK_ISP_DIV_ISP1>,
626 <&isp_clock CLK_ISP_DIV_MCUISP0>,
627 <&isp_clock CLK_ISP_DIV_MCUISP1>,
628 <&clock CLK_MOUT_MPLL_USER_T>,
629 <&clock CLK_ACLK200>,
630 <&clock CLK_ACLK400_MCUISP>,
631 <&clock CLK_DIV_ACLK200>,
632 <&clock CLK_DIV_ACLK400_MCUISP>,
633 <&clock CLK_UART_ISP_SCLK>;
634 clock-names = "lite0", "lite1", "ppmuispx",
635 "ppmuispmx", "isp",
636 "drc", "fd", "mcuisp",
637 "gicisp", "mcuctl_isp", "pwm_isp",
638 "ispdiv0", "ispdiv1", "mcuispdiv0",
639 "mcuispdiv1", "mpll", "aclk200",
640 "aclk400mcuisp", "div_aclk200",
641 "div_aclk400mcuisp", "uart";
642 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
643 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
644 iommu-names = "isp", "drc", "fd", "mcuctl";
645 #address-cells = <1>;
646 #size-cells = <1>;
647 ranges;
648 status = "disabled";
649
650 pmu@10020000 {
651 reg = <0x10020000 0x3000>;
652 };
653
654 i2c1_isp: i2c-isp@12140000 {
655 compatible = "samsung,exynos4212-i2c-isp";
656 reg = <0x12140000 0x100>;
657 clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
658 clock-names = "i2c_isp";
659 #address-cells = <1>;
660 #size-cells = <0>;
661 };
662 };
663};
664
665&exynos_usbphy {
666 compatible = "samsung,exynos4x12-usb2-phy";
667 samsung,sysreg-phandle = <&sys_reg>;
668};
669
670&fimc_0 {
671 compatible = "samsung,exynos4212-fimc";
672 samsung,pix-limits = <4224 8192 1920 4224>;
673 samsung,mainscaler-ext;
674 samsung,isp-wb;
675 samsung,cam-if;
676};
677
678&fimc_1 {
679 compatible = "samsung,exynos4212-fimc";
680 samsung,pix-limits = <4224 8192 1920 4224>;
681 samsung,mainscaler-ext;
682 samsung,isp-wb;
683 samsung,cam-if;
684};
685
686&fimc_2 {
687 compatible = "samsung,exynos4212-fimc";
688 samsung,pix-limits = <4224 8192 1920 4224>;
689 samsung,mainscaler-ext;
690 samsung,isp-wb;
691 samsung,lcd-wb;
692 samsung,cam-if;
693};
694
695&fimc_3 {
696 compatible = "samsung,exynos4212-fimc";
697 samsung,pix-limits = <1920 8192 1366 1920>;
698 samsung,rotators = <0>;
699 samsung,mainscaler-ext;
700 samsung,isp-wb;
701 samsung,lcd-wb;
702};
703
704&gic {
705 cpu-offset = <0x4000>;
706};
707
708&hdmi {
709 compatible = "samsung,exynos4212-hdmi";
710};
711
712&jpeg_codec {
713 compatible = "samsung,exynos4212-jpeg";
714};
715
716&rotator {
717 compatible = "samsung,exynos4212-rotator";
718};
719
720&mixer {
721 compatible = "samsung,exynos4212-mixer";
722 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
723 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
724 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
725};
726
727&pmu {
728 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
729};
730
731&pmu_system_controller {
732 compatible = "samsung,exynos4412-pmu", "syscon";
733 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
734 "clkout4", "clkout8", "clkout9";
735 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
736 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
737 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
738 #clock-cells = <1>;
739};
740
741&tmu {
742 compatible = "samsung,exynos4412-tmu";
743 interrupt-parent = <&combiner>;
744 interrupts = <2 4>;
745 reg = <0x100C0000 0x100>;
746 clocks = <&clock 383>;
747 clock-names = "tmu_apbif";
748 status = "disabled";
749};
750
751#include "exynos4412-pinctrl.dtsi"
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4412 SoC device tree source
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 *
8 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
9 * based board files can include this file and provide values for board specfic
10 * bindings.
11 *
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
14 * nodes can be added to this file.
15 */
16
17#include "exynos4.dtsi"
18
19#include "exynos4-cpu-thermal.dtsi"
20
21/ {
22 compatible = "samsung,exynos4412", "samsung,exynos4";
23
24 aliases {
25 pinctrl0 = &pinctrl_0;
26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3;
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
31 mshc0 = &mshc_0;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu0: cpu@a00 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a9";
41 reg = <0xA00>;
42 clocks = <&clock CLK_ARM_CLK>;
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
46 };
47
48 cpu1: cpu@a01 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a9";
51 reg = <0xA01>;
52 clocks = <&clock CLK_ARM_CLK>;
53 clock-names = "cpu";
54 operating-points-v2 = <&cpu0_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
56 };
57
58 cpu2: cpu@a02 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a9";
61 reg = <0xA02>;
62 clocks = <&clock CLK_ARM_CLK>;
63 clock-names = "cpu";
64 operating-points-v2 = <&cpu0_opp_table>;
65 #cooling-cells = <2>; /* min followed by max */
66 };
67
68 cpu3: cpu@a03 {
69 device_type = "cpu";
70 compatible = "arm,cortex-a9";
71 reg = <0xA03>;
72 clocks = <&clock CLK_ARM_CLK>;
73 clock-names = "cpu";
74 operating-points-v2 = <&cpu0_opp_table>;
75 #cooling-cells = <2>; /* min followed by max */
76 };
77 };
78
79 cpu0_opp_table: opp-table0 {
80 compatible = "operating-points-v2";
81 opp-shared;
82
83 opp-200000000 {
84 opp-hz = /bits/ 64 <200000000>;
85 opp-microvolt = <900000>;
86 clock-latency-ns = <200000>;
87 };
88 opp-300000000 {
89 opp-hz = /bits/ 64 <300000000>;
90 opp-microvolt = <900000>;
91 clock-latency-ns = <200000>;
92 };
93 opp-400000000 {
94 opp-hz = /bits/ 64 <400000000>;
95 opp-microvolt = <925000>;
96 clock-latency-ns = <200000>;
97 };
98 opp-500000000 {
99 opp-hz = /bits/ 64 <500000000>;
100 opp-microvolt = <950000>;
101 clock-latency-ns = <200000>;
102 };
103 opp-600000000 {
104 opp-hz = /bits/ 64 <600000000>;
105 opp-microvolt = <975000>;
106 clock-latency-ns = <200000>;
107 };
108 opp-700000000 {
109 opp-hz = /bits/ 64 <700000000>;
110 opp-microvolt = <987500>;
111 clock-latency-ns = <200000>;
112 };
113 opp-800000000 {
114 opp-hz = /bits/ 64 <800000000>;
115 opp-microvolt = <1000000>;
116 clock-latency-ns = <200000>;
117 opp-suspend;
118 };
119 opp-900000000 {
120 opp-hz = /bits/ 64 <900000000>;
121 opp-microvolt = <1037500>;
122 clock-latency-ns = <200000>;
123 };
124 opp-1000000000 {
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt = <1087500>;
127 clock-latency-ns = <200000>;
128 };
129 opp-1100000000 {
130 opp-hz = /bits/ 64 <1100000000>;
131 opp-microvolt = <1137500>;
132 clock-latency-ns = <200000>;
133 };
134 opp-1200000000 {
135 opp-hz = /bits/ 64 <1200000000>;
136 opp-microvolt = <1187500>;
137 clock-latency-ns = <200000>;
138 };
139 opp-1300000000 {
140 opp-hz = /bits/ 64 <1300000000>;
141 opp-microvolt = <1250000>;
142 clock-latency-ns = <200000>;
143 };
144 opp-1400000000 {
145 opp-hz = /bits/ 64 <1400000000>;
146 opp-microvolt = <1287500>;
147 clock-latency-ns = <200000>;
148 };
149 cpu0_opp_1500: opp-1500000000 {
150 opp-hz = /bits/ 64 <1500000000>;
151 opp-microvolt = <1350000>;
152 clock-latency-ns = <200000>;
153 turbo-mode;
154 };
155 };
156
157
158 soc: soc {
159
160 pinctrl_0: pinctrl@11400000 {
161 compatible = "samsung,exynos4x12-pinctrl";
162 reg = <0x11400000 0x1000>;
163 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
164 };
165
166 pinctrl_1: pinctrl@11000000 {
167 compatible = "samsung,exynos4x12-pinctrl";
168 reg = <0x11000000 0x1000>;
169 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
170
171 wakup_eint: wakeup-interrupt-controller {
172 compatible = "samsung,exynos4210-wakeup-eint";
173 interrupt-parent = <&gic>;
174 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
175 };
176 };
177
178 pinctrl_2: pinctrl@3860000 {
179 compatible = "samsung,exynos4x12-pinctrl";
180 reg = <0x03860000 0x1000>;
181 interrupt-parent = <&combiner>;
182 interrupts = <10 0>;
183 };
184
185 pinctrl_3: pinctrl@106e0000 {
186 compatible = "samsung,exynos4x12-pinctrl";
187 reg = <0x106E0000 0x1000>;
188 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
189 };
190
191 sram@2020000 {
192 compatible = "mmio-sram";
193 reg = <0x02020000 0x40000>;
194 #address-cells = <1>;
195 #size-cells = <1>;
196 ranges = <0 0x02020000 0x40000>;
197
198 smp-sram@0 {
199 compatible = "samsung,exynos4210-sysram";
200 reg = <0x0 0x1000>;
201 };
202
203 smp-sram@2f000 {
204 compatible = "samsung,exynos4210-sysram-ns";
205 reg = <0x2f000 0x1000>;
206 };
207 };
208
209 pd_isp: power-domain@10023ca0 {
210 compatible = "samsung,exynos4210-pd";
211 reg = <0x10023CA0 0x20>;
212 #power-domain-cells = <0>;
213 label = "ISP";
214 };
215
216 l2c: cache-controller@10502000 {
217 compatible = "arm,pl310-cache";
218 reg = <0x10502000 0x1000>;
219 cache-unified;
220 cache-level = <2>;
221 prefetch-data = <1>;
222 prefetch-instr = <1>;
223 arm,tag-latency = <2 2 1>;
224 arm,data-latency = <3 2 1>;
225 arm,double-linefill = <1>;
226 arm,double-linefill-incr = <0>;
227 arm,double-linefill-wrap = <1>;
228 arm,prefetch-drop = <1>;
229 arm,prefetch-offset = <7>;
230 };
231
232 clock: clock-controller@10030000 {
233 compatible = "samsung,exynos4412-clock";
234 reg = <0x10030000 0x18000>;
235 #clock-cells = <1>;
236 };
237
238 isp_clock: clock-controller@10048000 {
239 compatible = "samsung,exynos4412-isp-clock";
240 reg = <0x10048000 0x1000>;
241 #clock-cells = <1>;
242 power-domains = <&pd_isp>;
243 clocks = <&clock CLK_ACLK200>,
244 <&clock CLK_ACLK400_MCUISP>;
245 clock-names = "aclk200", "aclk400_mcuisp";
246 };
247
248 timer@10050000 {
249 compatible = "samsung,exynos4412-mct";
250 reg = <0x10050000 0x800>;
251 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
252 clock-names = "fin_pll", "mct";
253 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
254 <&combiner 12 5>,
255 <&combiner 12 6>,
256 <&combiner 12 7>,
257 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
258 };
259
260 watchdog: watchdog@10060000 {
261 compatible = "samsung,exynos5250-wdt";
262 reg = <0x10060000 0x100>;
263 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clock CLK_WDT>;
265 clock-names = "watchdog";
266 samsung,syscon-phandle = <&pmu_system_controller>;
267 };
268
269 adc: adc@126c0000 {
270 compatible = "samsung,exynos4212-adc";
271 reg = <0x126C0000 0x100>;
272 interrupt-parent = <&combiner>;
273 interrupts = <10 3>;
274 clocks = <&clock CLK_TSADC>;
275 clock-names = "adc";
276 #io-channel-cells = <1>;
277 samsung,syscon-phandle = <&pmu_system_controller>;
278 status = "disabled";
279 };
280
281 g2d: g2d@10800000 {
282 compatible = "samsung,exynos4212-g2d";
283 reg = <0x10800000 0x1000>;
284 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
286 clock-names = "sclk_fimg2d", "fimg2d";
287 iommus = <&sysmmu_g2d>;
288 };
289
290 mshc_0: mmc@12550000 {
291 compatible = "samsung,exynos4412-dw-mshc";
292 reg = <0x12550000 0x1000>;
293 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296 fifo-depth = <0x80>;
297 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
298 clock-names = "biu", "ciu";
299 status = "disabled";
300 };
301
302 sysmmu_g2d: sysmmu@10a40000 {
303 compatible = "samsung,exynos-sysmmu";
304 reg = <0x10A40000 0x1000>;
305 interrupt-parent = <&combiner>;
306 interrupts = <4 7>;
307 clock-names = "sysmmu", "master";
308 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
309 #iommu-cells = <0>;
310 };
311
312 sysmmu_fimc_isp: sysmmu@12260000 {
313 compatible = "samsung,exynos-sysmmu";
314 reg = <0x12260000 0x1000>;
315 interrupt-parent = <&combiner>;
316 interrupts = <16 2>;
317 power-domains = <&pd_isp>;
318 clock-names = "sysmmu";
319 clocks = <&isp_clock CLK_ISP_SMMU_ISP>;
320 #iommu-cells = <0>;
321 };
322
323 sysmmu_fimc_drc: sysmmu@12270000 {
324 compatible = "samsung,exynos-sysmmu";
325 reg = <0x12270000 0x1000>;
326 interrupt-parent = <&combiner>;
327 interrupts = <16 3>;
328 power-domains = <&pd_isp>;
329 clock-names = "sysmmu";
330 clocks = <&isp_clock CLK_ISP_SMMU_DRC>;
331 #iommu-cells = <0>;
332 };
333
334 sysmmu_fimc_fd: sysmmu@122a0000 {
335 compatible = "samsung,exynos-sysmmu";
336 reg = <0x122A0000 0x1000>;
337 interrupt-parent = <&combiner>;
338 interrupts = <16 4>;
339 power-domains = <&pd_isp>;
340 clock-names = "sysmmu";
341 clocks = <&isp_clock CLK_ISP_SMMU_FD>;
342 #iommu-cells = <0>;
343 };
344
345 sysmmu_fimc_mcuctl: sysmmu@122b0000 {
346 compatible = "samsung,exynos-sysmmu";
347 reg = <0x122B0000 0x1000>;
348 interrupt-parent = <&combiner>;
349 interrupts = <16 5>;
350 power-domains = <&pd_isp>;
351 clock-names = "sysmmu";
352 clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>;
353 #iommu-cells = <0>;
354 };
355
356 sysmmu_fimc_lite0: sysmmu@123b0000 {
357 compatible = "samsung,exynos-sysmmu";
358 reg = <0x123B0000 0x1000>;
359 interrupt-parent = <&combiner>;
360 interrupts = <16 0>;
361 power-domains = <&pd_isp>;
362 clock-names = "sysmmu", "master";
363 clocks = <&isp_clock CLK_ISP_SMMU_LITE0>,
364 <&isp_clock CLK_ISP_FIMC_LITE0>;
365 #iommu-cells = <0>;
366 };
367
368 sysmmu_fimc_lite1: sysmmu@123c0000 {
369 compatible = "samsung,exynos-sysmmu";
370 reg = <0x123C0000 0x1000>;
371 interrupt-parent = <&combiner>;
372 interrupts = <16 1>;
373 power-domains = <&pd_isp>;
374 clock-names = "sysmmu", "master";
375 clocks = <&isp_clock CLK_ISP_SMMU_LITE1>,
376 <&isp_clock CLK_ISP_FIMC_LITE1>;
377 #iommu-cells = <0>;
378 };
379
380 bus_dmc: bus-dmc {
381 compatible = "samsung,exynos-bus";
382 clocks = <&clock CLK_DIV_DMC>;
383 clock-names = "bus";
384 operating-points-v2 = <&bus_dmc_opp_table>;
385 samsung,data-clock-ratio = <4>;
386 #interconnect-cells = <0>;
387 status = "disabled";
388 };
389
390 bus_acp: bus-acp {
391 compatible = "samsung,exynos-bus";
392 clocks = <&clock CLK_DIV_ACP>;
393 clock-names = "bus";
394 operating-points-v2 = <&bus_acp_opp_table>;
395 status = "disabled";
396 };
397
398 bus_c2c: bus-c2c {
399 compatible = "samsung,exynos-bus";
400 clocks = <&clock CLK_DIV_C2C>;
401 clock-names = "bus";
402 operating-points-v2 = <&bus_dmc_opp_table>;
403 status = "disabled";
404 };
405
406 bus_dmc_opp_table: opp-table1 {
407 compatible = "operating-points-v2";
408
409 opp-100000000 {
410 opp-hz = /bits/ 64 <100000000>;
411 opp-microvolt = <900000>;
412 };
413 opp-134000000 {
414 opp-hz = /bits/ 64 <134000000>;
415 opp-microvolt = <900000>;
416 };
417 opp-160000000 {
418 opp-hz = /bits/ 64 <160000000>;
419 opp-microvolt = <900000>;
420 };
421 opp-267000000 {
422 opp-hz = /bits/ 64 <267000000>;
423 opp-microvolt = <950000>;
424 };
425 opp-400000000 {
426 opp-hz = /bits/ 64 <400000000>;
427 opp-microvolt = <1050000>;
428 opp-suspend;
429 };
430 };
431
432 bus_acp_opp_table: opp-table2 {
433 compatible = "operating-points-v2";
434
435 opp-100000000 {
436 opp-hz = /bits/ 64 <100000000>;
437 };
438 opp-134000000 {
439 opp-hz = /bits/ 64 <134000000>;
440 };
441 opp-160000000 {
442 opp-hz = /bits/ 64 <160000000>;
443 };
444 opp-267000000 {
445 opp-hz = /bits/ 64 <267000000>;
446 };
447 };
448
449 bus_leftbus: bus-leftbus {
450 compatible = "samsung,exynos-bus";
451 clocks = <&clock CLK_DIV_GDL>;
452 clock-names = "bus";
453 operating-points-v2 = <&bus_leftbus_opp_table>;
454 interconnects = <&bus_dmc>;
455 #interconnect-cells = <0>;
456 status = "disabled";
457 };
458
459 bus_rightbus: bus-rightbus {
460 compatible = "samsung,exynos-bus";
461 clocks = <&clock CLK_DIV_GDR>;
462 clock-names = "bus";
463 operating-points-v2 = <&bus_leftbus_opp_table>;
464 status = "disabled";
465 };
466
467 bus_display: bus-display {
468 compatible = "samsung,exynos-bus";
469 clocks = <&clock CLK_ACLK160>;
470 clock-names = "bus";
471 operating-points-v2 = <&bus_display_opp_table>;
472 interconnects = <&bus_leftbus &bus_dmc>;
473 #interconnect-cells = <0>;
474 status = "disabled";
475 };
476
477 bus_fsys: bus-fsys {
478 compatible = "samsung,exynos-bus";
479 clocks = <&clock CLK_ACLK133>;
480 clock-names = "bus";
481 operating-points-v2 = <&bus_fsys_opp_table>;
482 status = "disabled";
483 };
484
485 bus_peri: bus-peri {
486 compatible = "samsung,exynos-bus";
487 clocks = <&clock CLK_ACLK100>;
488 clock-names = "bus";
489 operating-points-v2 = <&bus_peri_opp_table>;
490 status = "disabled";
491 };
492
493 bus_mfc: bus-mfc {
494 compatible = "samsung,exynos-bus";
495 clocks = <&clock CLK_SCLK_MFC>;
496 clock-names = "bus";
497 operating-points-v2 = <&bus_leftbus_opp_table>;
498 status = "disabled";
499 };
500
501 bus_leftbus_opp_table: opp-table3 {
502 compatible = "operating-points-v2";
503
504 opp-100000000 {
505 opp-hz = /bits/ 64 <100000000>;
506 opp-microvolt = <900000>;
507 };
508 opp-134000000 {
509 opp-hz = /bits/ 64 <134000000>;
510 opp-microvolt = <925000>;
511 };
512 opp-160000000 {
513 opp-hz = /bits/ 64 <160000000>;
514 opp-microvolt = <950000>;
515 };
516 opp-200000000 {
517 opp-hz = /bits/ 64 <200000000>;
518 opp-microvolt = <1000000>;
519 opp-suspend;
520 };
521 };
522
523 bus_display_opp_table: opp-table4 {
524 compatible = "operating-points-v2";
525
526 opp-160000000 {
527 opp-hz = /bits/ 64 <160000000>;
528 };
529 opp-200000000 {
530 opp-hz = /bits/ 64 <200000000>;
531 };
532 };
533
534 bus_fsys_opp_table: opp-table5 {
535 compatible = "operating-points-v2";
536
537 opp-100000000 {
538 opp-hz = /bits/ 64 <100000000>;
539 };
540 opp-134000000 {
541 opp-hz = /bits/ 64 <134000000>;
542 };
543 };
544
545 bus_peri_opp_table: opp-table6 {
546 compatible = "operating-points-v2";
547
548 opp-50000000 {
549 opp-hz = /bits/ 64 <50000000>;
550 };
551 opp-100000000 {
552 opp-hz = /bits/ 64 <100000000>;
553 };
554 };
555 };
556};
557
558&combiner {
559 samsung,combiner-nr = <20>;
560 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
580};
581
582&camera {
583 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
584 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
585 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
586
587 /* fimc_[0-3] are configured outside, under phandles */
588 fimc_lite_0: fimc-lite@12390000 {
589 compatible = "samsung,exynos4212-fimc-lite";
590 reg = <0x12390000 0x1000>;
591 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
592 power-domains = <&pd_isp>;
593 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
594 clock-names = "flite";
595 iommus = <&sysmmu_fimc_lite0>;
596 status = "disabled";
597 };
598
599 fimc_lite_1: fimc-lite@123a0000 {
600 compatible = "samsung,exynos4212-fimc-lite";
601 reg = <0x123A0000 0x1000>;
602 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
603 power-domains = <&pd_isp>;
604 clocks = <&isp_clock CLK_ISP_FIMC_LITE1>;
605 clock-names = "flite";
606 iommus = <&sysmmu_fimc_lite1>;
607 status = "disabled";
608 };
609
610 fimc_is: fimc-is@12000000 {
611 compatible = "samsung,exynos4212-fimc-is";
612 reg = <0x12000000 0x260000>;
613 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
615 power-domains = <&pd_isp>;
616 clocks = <&isp_clock CLK_ISP_FIMC_LITE0>,
617 <&isp_clock CLK_ISP_FIMC_LITE1>,
618 <&isp_clock CLK_ISP_PPMUISPX>,
619 <&isp_clock CLK_ISP_PPMUISPMX>,
620 <&isp_clock CLK_ISP_FIMC_ISP>,
621 <&isp_clock CLK_ISP_FIMC_DRC>,
622 <&isp_clock CLK_ISP_FIMC_FD>,
623 <&isp_clock CLK_ISP_MCUISP>,
624 <&isp_clock CLK_ISP_GICISP>,
625 <&isp_clock CLK_ISP_MCUCTL_ISP>,
626 <&isp_clock CLK_ISP_PWM_ISP>,
627 <&isp_clock CLK_ISP_DIV_ISP0>,
628 <&isp_clock CLK_ISP_DIV_ISP1>,
629 <&isp_clock CLK_ISP_DIV_MCUISP0>,
630 <&isp_clock CLK_ISP_DIV_MCUISP1>,
631 <&clock CLK_MOUT_MPLL_USER_T>,
632 <&clock CLK_ACLK200>,
633 <&clock CLK_ACLK400_MCUISP>,
634 <&clock CLK_DIV_ACLK200>,
635 <&clock CLK_DIV_ACLK400_MCUISP>,
636 <&clock CLK_UART_ISP_SCLK>;
637 clock-names = "lite0", "lite1", "ppmuispx",
638 "ppmuispmx", "isp",
639 "drc", "fd", "mcuisp",
640 "gicisp", "mcuctl_isp", "pwm_isp",
641 "ispdiv0", "ispdiv1", "mcuispdiv0",
642 "mcuispdiv1", "mpll", "aclk200",
643 "aclk400mcuisp", "div_aclk200",
644 "div_aclk400mcuisp", "uart";
645 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>,
646 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>;
647 iommu-names = "isp", "drc", "fd", "mcuctl";
648 #address-cells = <1>;
649 #size-cells = <1>;
650 ranges;
651 status = "disabled";
652
653 pmu@10020000 {
654 reg = <0x10020000 0x3000>;
655 };
656
657 i2c1_isp: i2c-isp@12140000 {
658 compatible = "samsung,exynos4212-i2c-isp";
659 reg = <0x12140000 0x100>;
660 clocks = <&isp_clock CLK_ISP_I2C1_ISP>;
661 clock-names = "i2c_isp";
662 #address-cells = <1>;
663 #size-cells = <0>;
664 };
665 };
666};
667
668&exynos_usbphy {
669 compatible = "samsung,exynos4x12-usb2-phy";
670 samsung,sysreg-phandle = <&sys_reg>;
671};
672
673&fimc_0 {
674 compatible = "samsung,exynos4212-fimc";
675 samsung,pix-limits = <4224 8192 1920 4224>;
676 samsung,mainscaler-ext;
677 samsung,isp-wb;
678 samsung,cam-if;
679};
680
681&fimc_1 {
682 compatible = "samsung,exynos4212-fimc";
683 samsung,pix-limits = <4224 8192 1920 4224>;
684 samsung,mainscaler-ext;
685 samsung,isp-wb;
686 samsung,cam-if;
687};
688
689&fimc_2 {
690 compatible = "samsung,exynos4212-fimc";
691 samsung,pix-limits = <4224 8192 1920 4224>;
692 samsung,mainscaler-ext;
693 samsung,isp-wb;
694 samsung,lcd-wb;
695 samsung,cam-if;
696};
697
698&fimc_3 {
699 compatible = "samsung,exynos4212-fimc";
700 samsung,pix-limits = <1920 8192 1366 1920>;
701 samsung,rotators = <0>;
702 samsung,mainscaler-ext;
703 samsung,isp-wb;
704 samsung,lcd-wb;
705};
706
707&gic {
708 cpu-offset = <0x4000>;
709};
710
711&gpu {
712 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
723 interrupt-names = "gp",
724 "gpmmu",
725 "pp0",
726 "ppmmu0",
727 "pp1",
728 "ppmmu1",
729 "pp2",
730 "ppmmu2",
731 "pp3",
732 "ppmmu3",
733 "pmu";
734 operating-points-v2 = <&gpu_opp_table>;
735
736 gpu_opp_table: opp-table {
737 compatible = "operating-points-v2";
738
739 opp-160000000 {
740 opp-hz = /bits/ 64 <160000000>;
741 opp-microvolt = <875000>;
742 };
743 opp-267000000 {
744 opp-hz = /bits/ 64 <267000000>;
745 opp-microvolt = <900000>;
746 };
747 opp-350000000 {
748 opp-hz = /bits/ 64 <350000000>;
749 opp-microvolt = <950000>;
750 };
751 opp-440000000 {
752 opp-hz = /bits/ 64 <440000000>;
753 opp-microvolt = <1025000>;
754 };
755 };
756};
757
758&hdmi {
759 compatible = "samsung,exynos4212-hdmi";
760};
761
762&jpeg_codec {
763 compatible = "samsung,exynos4212-jpeg";
764};
765
766&rotator {
767 compatible = "samsung,exynos4212-rotator";
768};
769
770&mixer {
771 compatible = "samsung,exynos4212-mixer";
772 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
773 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
774 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
775 interconnects = <&bus_display &bus_dmc>;
776};
777
778&pmu {
779 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
780 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
781 status = "okay";
782};
783
784&pmu_system_controller {
785 compatible = "samsung,exynos4412-pmu", "syscon";
786 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
787 "clkout4", "clkout8", "clkout9";
788 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
789 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
790 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
791 #clock-cells = <1>;
792};
793
794&tmu {
795 compatible = "samsung,exynos4412-tmu";
796 interrupt-parent = <&combiner>;
797 interrupts = <2 4>;
798 reg = <0x100C0000 0x100>;
799 clocks = <&clock 383>;
800 clock-names = "tmu_apbif";
801 status = "disabled";
802};
803
804#include "exynos4412-pinctrl.dtsi"