1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 * FriendlyARM's Exynos4412 based TINY4412 board device tree source
 4 *
 5 * Copyright (c) 2013 Alex Ling <kasimling@gmail.com>
 6 *
 7 * Device tree source file for FriendlyARM's TINY4412 board which is based on
 8 * Samsung's Exynos4412 SoC.
 9 */
10
11/dts-v1/;
12#include "exynos4412.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16	model = "FriendlyARM TINY4412 board based on Exynos4412";
17	compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4";
18
19	chosen {
20		stdout-path = &serial_0;
21	};
22
23	memory@40000000 {
24		device_type = "memory";
25		reg = <0x40000000 0x40000000>;
26	};
27
28	leds {
29		compatible = "gpio-leds";
30
31		led1 {
32			label = "led1";
33			gpios = <&gpm4 0 GPIO_ACTIVE_LOW>;
34			default-state = "off";
35			linux,default-trigger = "heartbeat";
36		};
37
38		led2 {
39			label = "led2";
40			gpios = <&gpm4 1 GPIO_ACTIVE_LOW>;
41			default-state = "off";
42		};
43
44		led3 {
45			label = "led3";
46			gpios = <&gpm4 2 GPIO_ACTIVE_LOW>;
47			default-state = "off";
48		};
49
50		led4 {
51			label = "led4";
52			gpios = <&gpm4 3 GPIO_ACTIVE_LOW>;
53			default-state = "off";
54			linux,default-trigger = "mmc0";
55		};
56	};
57
58	fixed-rate-clocks {
59		xxti {
60			compatible = "samsung,clock-xxti";
61			clock-frequency = <0>;
62		};
63
64		xusbxti {
65			compatible = "samsung,clock-xusbxti";
66			clock-frequency = <24000000>;
67		};
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
68	};
69};
70
71&rtc {
72	status = "okay";
 
 
73};
74
75&sdhci_2 {
76	bus-width = <4>;
77	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
78	pinctrl-names = "default";
79	status = "okay";
80};
81
82&serial_0 {
83	status = "okay";
84};
85
86&serial_1 {
87	status = "okay";
88};
89
90&serial_2 {
91	status = "okay";
92};
93
94&serial_3 {
95	status = "okay";
96};

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * FriendlyARM's Exynos4412 based TINY4412 board device tree source
  4 *
  5 * Copyright (c) 2013 Alex Ling <kasimling@gmail.com>
  6 *
  7 * Device tree source file for FriendlyARM's TINY4412 board which is based on
  8 * Samsung's Exynos4412 SoC.
  9 */
 10
 11/dts-v1/;
 12#include "exynos4412.dtsi"
 13#include <dt-bindings/gpio/gpio.h>
 14
 15/ {
 16	model = "FriendlyARM TINY4412 board based on Exynos4412";
 17	compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4";
 18
 19	chosen {
 20		stdout-path = &serial_0;
 21	};
 22
 23	memory@40000000 {
 24		device_type = "memory";
 25		reg = <0x40000000 0x40000000>;
 26	};
 27
 28	leds {
 29		compatible = "gpio-leds";
 30
 31		led1 {
 32			label = "led1";
 33			gpios = <&gpm4 0 GPIO_ACTIVE_LOW>;
 34			default-state = "off";
 35			linux,default-trigger = "heartbeat";
 36		};
 37
 38		led2 {
 39			label = "led2";
 40			gpios = <&gpm4 1 GPIO_ACTIVE_LOW>;
 41			default-state = "off";
 42		};
 43
 44		led3 {
 45			label = "led3";
 46			gpios = <&gpm4 2 GPIO_ACTIVE_LOW>;
 47			default-state = "off";
 48		};
 49
 50		led4 {
 51			label = "led4";
 52			gpios = <&gpm4 3 GPIO_ACTIVE_LOW>;
 53			default-state = "off";
 54			linux,default-trigger = "mmc0";
 55		};
 56	};
 57
 58	fixed-rate-clocks {
 59		xxti {
 60			compatible = "samsung,clock-xxti";
 61			clock-frequency = <0>;
 62		};
 63
 64		xusbxti {
 65			compatible = "samsung,clock-xusbxti";
 66			clock-frequency = <24000000>;
 67		};
 68
 69		pmic_ap_clk: pmic-ap-clk {
 70			/* Workaround for missing clock on PMIC */
 71			compatible = "fixed-clock";
 72			#clock-cells = <0>;
 73			clock-frequency = <32768>;
 74		};
 75	};
 76
 77	panel {
 78		compatible = "innolux,at070tn92";
 79
 80		port {
 81			panel_input: endpoint {
 82				remote-endpoint = <&lcdc_output>;
 83			};
 84		};
 85	};
 86};
 87
 88&cpu_thermal {
 89	cooling-maps {
 90		cooling_map0: map0 {
 91			/* Corresponds to 800MHz at freq_table */
 92			cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
 93					 <&cpu2 7 7>, <&cpu3 7 7>;
 94		};
 95		cooling_map1: map1 {
 96			/* Corresponds to 200MHz at freq_table */
 97			cooling-device = <&cpu0 13 13>, <&cpu1 13 13>,
 98					 <&cpu2 13 13>, <&cpu3 13 13>;
 99		};
100	};
101};
102
103&fimd {
104	pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
105	pinctrl-names = "default";
106	#address-cells = <1>;
107	#size-cells = <0>;
108	status = "okay";
109
110	port@3 {
111		reg = <3>;
112		lcdc_output: endpoint {
113			remote-endpoint = <&panel_input>;
114		};
115	};
116};
117
118&rtc {
119	status = "okay";
120	clocks = <&clock CLK_RTC>, <&pmic_ap_clk>;
121	clock-names = "rtc", "rtc_src";
122};
123
124&sdhci_2 {
125	bus-width = <4>;
126	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
127	pinctrl-names = "default";
128	status = "okay";
129};
130
131&serial_0 {
132	status = "okay";
133};
134
135&serial_1 {
136	status = "okay";
137};
138
139&serial_2 {
140	status = "okay";
141};
142
143&serial_3 {
144	status = "okay";
145};