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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
4 *
5 * Copyright (C) 2015 Russell King
6 *
7 * This board is in development; the contents of this file work with
8 * the A1 rev 2.0 of the board, which does not represent final
9 * production board. Things will change, don't expect this file to
10 * remain compatible info the future.
11 */
12
13/dts-v1/;
14#include "armada-388-clearfog.dtsi"
15
16/ {
17 model = "SolidRun Clearfog A1";
18 compatible = "solidrun,clearfog-a1", "marvell,armada388",
19 "marvell,armada385", "marvell,armada380";
20
21 soc {
22 internal-regs {
23 usb3@f0000 {
24 /* CON2, nearest CPU, USB2 only. */
25 status = "okay";
26 };
27 };
28
29 pcie {
30 pcie@3,0 {
31 /* Port 2, Lane 0. CON2, nearest CPU. */
32 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
33 status = "okay";
34 };
35 };
36 };
37
38 dsa@0 {
39 status = "disabled";
40
41 compatible = "marvell,dsa";
42 dsa,ethernet = <ð1>;
43 dsa,mii-bus = <&mdio>;
44 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
45 pinctrl-names = "default";
46 #address-cells = <2>;
47 #size-cells = <0>;
48
49 switch@0 {
50 #address-cells = <1>;
51 #size-cells = <0>;
52 reg = <4 0>;
53
54 port@0 {
55 reg = <0>;
56 label = "lan5";
57 };
58
59 port@1 {
60 reg = <1>;
61 label = "lan4";
62 };
63
64 port@2 {
65 reg = <2>;
66 label = "lan3";
67 };
68
69 port@3 {
70 reg = <3>;
71 label = "lan2";
72 };
73
74 port@4 {
75 reg = <4>;
76 label = "lan1";
77 };
78
79 port@5 {
80 reg = <5>;
81 label = "cpu";
82 };
83
84 port@6 {
85 /* 88E1512 external phy */
86 reg = <6>;
87 label = "lan6";
88 fixed-link {
89 speed = <1000>;
90 full-duplex;
91 };
92 };
93 };
94 };
95
96 gpio-keys {
97 compatible = "gpio-keys";
98 pinctrl-0 = <&rear_button_pins>;
99 pinctrl-names = "default";
100
101 button_0 {
102 /* The rear SW3 button */
103 label = "Rear Button";
104 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
105 linux,can-disable;
106 linux,code = <BTN_0>;
107 };
108 };
109};
110
111ð1 {
112 /* ethernet@30000 */
113 fixed-link {
114 speed = <1000>;
115 full-duplex;
116 };
117};
118
119&expander0 {
120 /*
121 * PCA9655 GPIO expander:
122 * 0-CON3 CLKREQ#
123 * 1-CON3 PERST#
124 * 2-CON2 PERST#
125 * 3-CON3 W_DISABLE
126 * 4-CON2 CLKREQ#
127 * 5-USB3 overcurrent
128 * 6-USB3 power
129 * 7-CON2 W_DISABLE
130 * 8-JP4 P1
131 * 9-JP4 P4
132 * 10-JP4 P5
133 * 11-m.2 DEVSLP
134 * 12-SFP_LOS
135 * 13-SFP_TX_FAULT
136 * 14-SFP_TX_DISABLE
137 * 15-SFP_MOD_DEF0
138 */
139 pcie2_0_clkreq {
140 gpio-hog;
141 gpios = <4 GPIO_ACTIVE_LOW>;
142 input;
143 line-name = "pcie2.0-clkreq";
144 };
145 pcie2_0_w_disable {
146 gpio-hog;
147 gpios = <7 GPIO_ACTIVE_LOW>;
148 output-low;
149 line-name = "pcie2.0-w-disable";
150 };
151};
152
153&mdio {
154 status = "okay";
155
156 switch@4 {
157 compatible = "marvell,mv88e6085";
158 #address-cells = <1>;
159 #size-cells = <0>;
160 reg = <4>;
161 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
162 pinctrl-names = "default";
163
164 ports {
165 #address-cells = <1>;
166 #size-cells = <0>;
167
168 port@0 {
169 reg = <0>;
170 label = "lan5";
171 };
172
173 port@1 {
174 reg = <1>;
175 label = "lan4";
176 };
177
178 port@2 {
179 reg = <2>;
180 label = "lan3";
181 };
182
183 port@3 {
184 reg = <3>;
185 label = "lan2";
186 };
187
188 port@4 {
189 reg = <4>;
190 label = "lan1";
191 };
192
193 port@5 {
194 reg = <5>;
195 label = "cpu";
196 ethernet = <ð1>;
197 fixed-link {
198 speed = <1000>;
199 full-duplex;
200 };
201 };
202
203 port@6 {
204 /* 88E1512 external phy */
205 reg = <6>;
206 label = "lan6";
207 fixed-link {
208 speed = <1000>;
209 full-duplex;
210 };
211 };
212 };
213 };
214};
215
216&pinctrl {
217 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
218 marvell,pins = "mpp46";
219 marvell,function = "ref";
220 };
221 clearfog_dsa0_pins: clearfog-dsa0-pins {
222 marvell,pins = "mpp23", "mpp41";
223 marvell,function = "gpio";
224 };
225 clearfog_spi1_cs_pins: spi1-cs-pins {
226 marvell,pins = "mpp55";
227 marvell,function = "spi1";
228 };
229 rear_button_pins: rear-button-pins {
230 marvell,pins = "mpp34";
231 marvell,function = "gpio";
232 };
233};
234
235&spi1 {
236 /*
237 * Add SPI CS pins for clearfog:
238 * CS0: W25Q32 (not populated on uSOM)
239 * CS1:
240 * CS2: mikrobus
241 */
242 pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
243};
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
4 *
5 * Copyright (C) 2015 Russell King
6 */
7
8/dts-v1/;
9#include "armada-388-clearfog.dtsi"
10
11/ {
12 model = "SolidRun Clearfog A1";
13 compatible = "solidrun,clearfog-a1", "marvell,armada388",
14 "marvell,armada385", "marvell,armada380";
15
16 soc {
17 internal-regs {
18 usb3@f0000 {
19 /* CON2, nearest CPU, USB2 only. */
20 status = "okay";
21 };
22 };
23
24 pcie {
25 pcie@3,0 {
26 /* Port 2, Lane 0. CON2, nearest CPU. */
27 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
28 status = "okay";
29 };
30 };
31 };
32
33 gpio-keys {
34 compatible = "gpio-keys";
35 pinctrl-0 = <&rear_button_pins>;
36 pinctrl-names = "default";
37
38 button_0 {
39 /* The rear SW3 button */
40 label = "Rear Button";
41 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
42 linux,can-disable;
43 linux,code = <BTN_0>;
44 };
45 };
46};
47
48ð1 {
49 /* ethernet@30000 */
50 fixed-link {
51 speed = <1000>;
52 full-duplex;
53 };
54};
55
56&expander0 {
57 /*
58 * PCA9655 GPIO expander:
59 * 0-CON3 CLKREQ#
60 * 1-CON3 PERST#
61 * 2-CON2 PERST#
62 * 3-CON3 W_DISABLE
63 * 4-CON2 CLKREQ#
64 * 5-USB3 overcurrent
65 * 6-USB3 power
66 * 7-CON2 W_DISABLE
67 * 8-JP4 P1
68 * 9-JP4 P4
69 * 10-JP4 P5
70 * 11-m.2 DEVSLP
71 * 12-SFP_LOS
72 * 13-SFP_TX_FAULT
73 * 14-SFP_TX_DISABLE
74 * 15-SFP_MOD_DEF0
75 */
76 pcie2-0-clkreq-hog {
77 gpio-hog;
78 gpios = <4 GPIO_ACTIVE_LOW>;
79 input;
80 line-name = "pcie2.0-clkreq";
81 };
82 pcie2-0-w-disable-hog {
83 gpio-hog;
84 gpios = <7 GPIO_ACTIVE_LOW>;
85 output-low;
86 line-name = "pcie2.0-w-disable";
87 };
88};
89
90&mdio {
91 status = "okay";
92
93 switch@4 {
94 compatible = "marvell,mv88e6085";
95 #address-cells = <1>;
96 #size-cells = <0>;
97 reg = <4>;
98 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
99 pinctrl-names = "default";
100
101 ports {
102 #address-cells = <1>;
103 #size-cells = <0>;
104
105 port@0 {
106 reg = <0>;
107 label = "lan5";
108 };
109
110 port@1 {
111 reg = <1>;
112 label = "lan4";
113 };
114
115 port@2 {
116 reg = <2>;
117 label = "lan3";
118 };
119
120 port@3 {
121 reg = <3>;
122 label = "lan2";
123 };
124
125 port@4 {
126 reg = <4>;
127 label = "lan1";
128 };
129
130 port@5 {
131 reg = <5>;
132 label = "cpu";
133 ethernet = <ð1>;
134 fixed-link {
135 speed = <1000>;
136 full-duplex;
137 };
138 };
139
140 port@6 {
141 /* 88E1512 external phy */
142 reg = <6>;
143 label = "lan6";
144 fixed-link {
145 speed = <1000>;
146 full-duplex;
147 };
148 };
149 };
150 };
151};
152
153&pinctrl {
154 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
155 marvell,pins = "mpp46";
156 marvell,function = "ref";
157 };
158 clearfog_dsa0_pins: clearfog-dsa0-pins {
159 marvell,pins = "mpp23", "mpp41";
160 marvell,function = "gpio";
161 };
162 clearfog_spi1_cs_pins: spi1-cs-pins {
163 marvell,pins = "mpp55";
164 marvell,function = "spi1";
165 };
166 rear_button_pins: rear-button-pins {
167 marvell,pins = "mpp34";
168 marvell,function = "gpio";
169 };
170};
171
172&spi1 {
173 /*
174 * Add SPI CS pins for clearfog:
175 * CS0: W25Q32
176 * CS1:
177 * CS2: mikrobus
178 */
179 pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
180};