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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Marvell Armada 370 Reference Design board
4 * (RD-88F6710-A1)
5 *
6 * Copied from arch/arm/boot/dts/armada-370-db.dts
7 *
8 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
9 *
10 * Note: this Device Tree assumes that the bootloader has remapped the
11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
14 * boards were delivered with an older version of the bootloader that
15 * left internal registers mapped at 0xd0000000. If you are in this
16 * situation, you should either update your bootloader (preferred
17 * solution) or the below Device Tree should be adjusted.
18 */
19
20/dts-v1/;
21#include <dt-bindings/input/input.h>
22#include <dt-bindings/interrupt-controller/irq.h>
23#include <dt-bindings/gpio/gpio.h>
24#include "armada-370.dtsi"
25
26/ {
27 model = "Marvell Armada 370 Reference Design";
28 compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
29
30 chosen {
31 stdout-path = "serial0:115200n8";
32 };
33
34 memory@0 {
35 device_type = "memory";
36 reg = <0x00000000 0x20000000>; /* 512 MB */
37 };
38
39 soc {
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
43
44 internal-regs {
45 serial@12000 {
46 status = "okay";
47 };
48 sata@a0000 {
49 nr-ports = <2>;
50 status = "okay";
51 };
52
53 ethernet@70000 {
54 status = "okay";
55 phy = <&phy0>;
56 phy-mode = "sgmii";
57 };
58 ethernet@74000 {
59 pinctrl-0 = <&ge1_rgmii_pins>;
60 pinctrl-names = "default";
61 status = "okay";
62 phy-mode = "rgmii-id";
63 fixed-link {
64 speed = <1000>;
65 full-duplex;
66 };
67 };
68
69 mvsdio@d4000 {
70 pinctrl-0 = <&sdio_pins1>;
71 pinctrl-names = "default";
72 status = "okay";
73 /* No CD or WP GPIOs */
74 broken-cd;
75 };
76
77 usb@50000 {
78 status = "okay";
79 };
80
81 usb@51000 {
82 status = "okay";
83 };
84
85 gpio-keys {
86 compatible = "gpio-keys";
87 #address-cells = <1>;
88 #size-cells = <0>;
89 button {
90 label = "Software Button";
91 linux,code = <KEY_POWER>;
92 gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
93 };
94 };
95
96 gpio-fan {
97 compatible = "gpio-fan";
98 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
99 gpio-fan,speed-map = <0 0 3000 1>;
100 pinctrl-0 = <&fan_pins>;
101 pinctrl-names = "default";
102 };
103
104 gpio_leds {
105 compatible = "gpio-leds";
106 pinctrl-names = "default";
107 pinctrl-0 = <&led_pins>;
108
109 sw_led {
110 label = "370rd:green:sw";
111 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
112 default-state = "keep";
113 };
114 };
115
116 nand@d0000 {
117 status = "okay";
118 num-cs = <1>;
119 marvell,nand-keep-config;
120 marvell,nand-enable-arbiter;
121 nand-on-flash-bbt;
122
123 partition@0 {
124 label = "U-Boot";
125 reg = <0 0x800000>;
126 };
127 partition@800000 {
128 label = "Linux";
129 reg = <0x800000 0x800000>;
130 };
131 partition@1000000 {
132 label = "Filesystem";
133 reg = <0x1000000 0x3f000000>;
134 };
135 };
136 };
137 };
138
139 dsa {
140 status = "disabled";
141
142 compatible = "marvell,dsa";
143 #address-cells = <2>;
144 #size-cells = <0>;
145
146 dsa,ethernet = <ð1>;
147 dsa,mii-bus = <&mdio>;
148
149 switch@0 {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */
153
154 port@0 {
155 reg = <0>;
156 label = "lan0";
157 };
158
159 port@1 {
160 reg = <1>;
161 label = "lan1";
162 };
163
164 port@2 {
165 reg = <2>;
166 label = "lan2";
167 };
168
169 port@3 {
170 reg = <3>;
171 label = "lan3";
172 };
173
174 port@5 {
175 reg = <5>;
176 label = "cpu";
177 };
178 };
179 };
180};
181
182&pciec {
183 status = "okay";
184
185 /* Internal mini-PCIe connector */
186 pcie@1,0 {
187 /* Port 0, Lane 0 */
188 status = "okay";
189 };
190
191 /* Internal mini-PCIe connector */
192 pcie@2,0 {
193 /* Port 1, Lane 0 */
194 status = "okay";
195 };
196};
197
198&mdio {
199 pinctrl-0 = <&mdio_pins>;
200 pinctrl-names = "default";
201 phy0: ethernet-phy@0 {
202 reg = <0>;
203 };
204
205 switch: switch@10 {
206 compatible = "marvell,mv88e6085";
207 #address-cells = <1>;
208 #size-cells = <0>;
209 reg = <0x10>;
210 interrupt-controller;
211 #interrupt-cells = <2>;
212
213 ports {
214 #address-cells = <1>;
215 #size-cells = <0>;
216
217 port@0 {
218 reg = <0>;
219 label = "lan0";
220 };
221
222 port@1 {
223 reg = <1>;
224 label = "lan1";
225 };
226
227 port@2 {
228 reg = <2>;
229 label = "lan2";
230 };
231
232 port@3 {
233 reg = <3>;
234 label = "lan3";
235 };
236
237 port@5 {
238 reg = <5>;
239 label = "cpu";
240 ethernet = <ð1>;
241 fixed-link {
242 speed = <1000>;
243 full-duplex;
244 };
245 };
246 };
247
248 mdio {
249 #address-cells = <1>;
250 #size-cells = <0>;
251
252 switchphy0: switchphy@0 {
253 reg = <0>;
254 interrupt-parent = <&switch>;
255 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
256 };
257
258 switchphy1: switchphy@1 {
259 reg = <1>;
260 interrupt-parent = <&switch>;
261 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
262 };
263
264 switchphy2: switchphy@2 {
265 reg = <2>;
266 interrupt-parent = <&switch>;
267 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
268 };
269
270 switchphy3: switchphy@3 {
271 reg = <3>;
272 interrupt-parent = <&switch>;
273 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
274 };
275 };
276 };
277};
278
279
280&pinctrl {
281 fan_pins: fan-pins {
282 marvell,pins = "mpp8";
283 marvell,function = "gpio";
284 };
285
286 led_pins: led-pins {
287 marvell,pins = "mpp32";
288 marvell,function = "gpio";
289 };
290};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Marvell Armada 370 Reference Design board
4 * (RD-88F6710-A1)
5 *
6 * Copied from arch/arm/boot/dts/armada-370-db.dts
7 *
8 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
9 *
10 * Note: this Device Tree assumes that the bootloader has remapped the
11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
14 * boards were delivered with an older version of the bootloader that
15 * left internal registers mapped at 0xd0000000. If you are in this
16 * situation, you should either update your bootloader (preferred
17 * solution) or the below Device Tree should be adjusted.
18 */
19
20/dts-v1/;
21#include <dt-bindings/input/input.h>
22#include <dt-bindings/interrupt-controller/irq.h>
23#include <dt-bindings/gpio/gpio.h>
24#include "armada-370.dtsi"
25
26/ {
27 model = "Marvell Armada 370 Reference Design";
28 compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
29
30 chosen {
31 stdout-path = "serial0:115200n8";
32 };
33
34 memory@0 {
35 device_type = "memory";
36 reg = <0x00000000 0x20000000>; /* 512 MB */
37 };
38
39 soc {
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
43
44 internal-regs {
45 serial@12000 {
46 status = "okay";
47 };
48 sata@a0000 {
49 nr-ports = <2>;
50 status = "okay";
51 };
52
53 ethernet@70000 {
54 status = "okay";
55 phy = <&phy0>;
56 phy-mode = "sgmii";
57 };
58 ethernet@74000 {
59 pinctrl-0 = <&ge1_rgmii_pins>;
60 pinctrl-names = "default";
61 status = "okay";
62 phy-mode = "rgmii-id";
63 fixed-link {
64 speed = <1000>;
65 full-duplex;
66 };
67 };
68
69 mvsdio@d4000 {
70 pinctrl-0 = <&sdio_pins1>;
71 pinctrl-names = "default";
72 status = "okay";
73 /* No CD or WP GPIOs */
74 broken-cd;
75 };
76
77 usb@50000 {
78 status = "okay";
79 };
80
81 usb@51000 {
82 status = "okay";
83 };
84
85 gpio-keys {
86 compatible = "gpio-keys";
87 #address-cells = <1>;
88 #size-cells = <0>;
89 button {
90 label = "Software Button";
91 linux,code = <KEY_POWER>;
92 gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
93 };
94 };
95
96 gpio-fan {
97 compatible = "gpio-fan";
98 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
99 gpio-fan,speed-map = <0 0 3000 1>;
100 pinctrl-0 = <&fan_pins>;
101 pinctrl-names = "default";
102 };
103
104 gpio_leds {
105 compatible = "gpio-leds";
106 pinctrl-names = "default";
107 pinctrl-0 = <&led_pins>;
108
109 sw_led {
110 label = "370rd:green:sw";
111 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
112 default-state = "keep";
113 };
114 };
115 };
116 };
117};
118
119&pciec {
120 status = "okay";
121
122 /* Internal mini-PCIe connector */
123 pcie@1,0 {
124 /* Port 0, Lane 0 */
125 status = "okay";
126 };
127
128 /* Internal mini-PCIe connector */
129 pcie@2,0 {
130 /* Port 1, Lane 0 */
131 status = "okay";
132 };
133};
134
135&mdio {
136 pinctrl-0 = <&mdio_pins>;
137 pinctrl-names = "default";
138 phy0: ethernet-phy@0 {
139 reg = <0>;
140 };
141
142 switch: switch@10 {
143 compatible = "marvell,mv88e6085";
144 #address-cells = <1>;
145 #size-cells = <0>;
146 reg = <0x10>;
147 interrupt-controller;
148 #interrupt-cells = <2>;
149
150 ports {
151 #address-cells = <1>;
152 #size-cells = <0>;
153
154 port@0 {
155 reg = <0>;
156 label = "lan0";
157 };
158
159 port@1 {
160 reg = <1>;
161 label = "lan1";
162 };
163
164 port@2 {
165 reg = <2>;
166 label = "lan2";
167 };
168
169 port@3 {
170 reg = <3>;
171 label = "lan3";
172 };
173
174 port@5 {
175 reg = <5>;
176 label = "cpu";
177 ethernet = <ð1>;
178 fixed-link {
179 speed = <1000>;
180 full-duplex;
181 };
182 };
183 };
184
185 mdio {
186 #address-cells = <1>;
187 #size-cells = <0>;
188
189 switchphy0: switchphy@0 {
190 reg = <0>;
191 interrupt-parent = <&switch>;
192 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
193 };
194
195 switchphy1: switchphy@1 {
196 reg = <1>;
197 interrupt-parent = <&switch>;
198 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
199 };
200
201 switchphy2: switchphy@2 {
202 reg = <2>;
203 interrupt-parent = <&switch>;
204 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
205 };
206
207 switchphy3: switchphy@3 {
208 reg = <3>;
209 interrupt-parent = <&switch>;
210 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
211 };
212 };
213 };
214};
215
216
217&pinctrl {
218 fan_pins: fan-pins {
219 marvell,pins = "mpp8";
220 marvell,function = "gpio";
221 };
222
223 led_pins: led-pins {
224 marvell,pins = "mpp32";
225 marvell,function = "gpio";
226 };
227};
228
229&nand_controller {
230 status = "okay";
231
232 nand@0 {
233 reg = <0>;
234 label = "pxa3xx_nand-0";
235 nand-rb = <0>;
236 marvell,nand-keep-config;
237 nand-on-flash-bbt;
238
239 partitions {
240 compatible = "fixed-partitions";
241 #address-cells = <1>;
242 #size-cells = <1>;
243
244 partition@0 {
245 label = "U-Boot";
246 reg = <0 0x800000>;
247 };
248 partition@800000 {
249 label = "Linux";
250 reg = <0x800000 0x800000>;
251 };
252 partition@1000000 {
253 label = "Filesystem";
254 reg = <0x1000000 0x3f000000>;
255 };
256 };
257 };
258};