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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2016 Derald D. Woods <woods.technical@gmail.com>
4 *
5 * Based on am3517-evm.dts
6 */
7
8/ {
9 cpus {
10 cpu@0 {
11 cpu0-supply = <&vdd_core_reg>;
12 };
13 };
14
15 wl12xx_buffer: wl12xx_buf {
16 compatible = "regulator-fixed";
17 regulator-name = "wl1271_buf";
18 regulator-min-microvolt = <1800000>;
19 regulator-max-microvolt = <1800000>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&wl12xx_buffer_pins>;
22 gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */
23 regulator-always-on;
24 vin-supply = <&vdd_1v8_reg>;
25 };
26
27 wl12xx_vmmc2: wl12xx_vmmc2 {
28 compatible = "regulator-fixed";
29 regulator-name = "vwl1271";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
32 pinctrl-names = "default";
33 pinctrl-0 = <&wl12xx_wkup_pins>;
34 gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */
35 startup-delay-us = <70000>;
36 enable-active-high;
37 regulator-always-on;
38 vin-supply = <&wl12xx_buffer>;
39 };
40};
41
42&gpmc {
43 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
44
45 nand@0,0 {
46 compatible = "ti,omap2-nand";
47 linux,mtd-name = "micron,mt29f4g16abchch";
48 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
49 nand-bus-width = <16>;
50 ti,nand-ecc-opt = "bch8";
51 gpmc,sync-clk-ps = <0>;
52 gpmc,cs-on-ns = <0>;
53 gpmc,cs-rd-off-ns = <44>;
54 gpmc,cs-wr-off-ns = <44>;
55 gpmc,adv-on-ns = <6>;
56 gpmc,adv-rd-off-ns = <34>;
57 gpmc,adv-wr-off-ns = <44>;
58 gpmc,we-off-ns = <40>;
59 gpmc,oe-off-ns = <54>;
60 gpmc,access-ns = <64>;
61 gpmc,rd-cycle-ns = <82>;
62 gpmc,wr-cycle-ns = <82>;
63 gpmc,wr-access-ns = <40>;
64 gpmc,wr-data-mux-bus-ns = <0>;
65 gpmc,device-width = <2>;
66 #address-cells = <1>;
67 #size-cells = <1>;
68 };
69};
70
71&i2c1 {
72 clock-frequency = <400000>;
73
74 s35390a: s35390a@30 {
75 compatible = "sii,s35390a";
76 reg = <0x30>;
77
78 pinctrl-names = "default";
79 pinctrl-0 = <&rtc_pins>;
80 interrupts-extended = <&gpio2 23 IRQ_TYPE_EDGE_FALLING>; /* gpio_55 */
81 };
82
83 tps: tps65023@48 {
84 compatible = "ti,tps65023";
85 reg = <0x48>;
86
87 regulators {
88 vdd_core_reg: VDCDC1 {
89 regulator-name = "vdd_core";
90 regulator-always-on;
91 regulator-min-microvolt = <1200000>;
92 regulator-max-microvolt = <1200000>;
93 };
94
95 vdd_io_reg: VDCDC2 {
96 regulator-name = "vdd_io";
97 regulator-always-on;
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 };
101
102 vdd_1v8_reg: VDCDC3 {
103 regulator-name = "vdd_1v8";
104 regulator-always-on;
105 regulator-min-microvolt = <1800000>;
106 regulator-max-microvolt = <1800000>;
107 };
108
109 vdd_usb18_reg: LDO1 {
110 regulator-name = "vdd_usb18";
111 regulator-always-on;
112 regulator-min-microvolt = <1800000>;
113 regulator-max-microvolt = <1800000>;
114 };
115
116 vdd_usb33_reg: LDO2 {
117 regulator-name = "vdd_usb33";
118 regulator-always-on;
119 regulator-min-microvolt = <3300000>;
120 regulator-max-microvolt = <3300000>;
121 };
122 };
123 };
124
125 touchscreen: tsc2004@4b {
126 compatible = "ti,tsc2004";
127 reg = <0x4b>;
128
129 vio-supply = <&vdd_io_reg>;
130
131 pinctrl-names = "default";
132 pinctrl-0 = <&tsc2004_pins>;
133 interrupts-extended = <&gpio3 1 IRQ_TYPE_EDGE_RISING>; /* gpio_65 */
134
135 touchscreen-fuzz-x = <4>;
136 touchscreen-fuzz-y = <7>;
137 touchscreen-fuzz-pressure = <2>;
138 touchscreen-size-x = <480>;
139 touchscreen-size-y = <272>;
140 touchscreen-max-pressure = <2048>;
141
142 ti,x-plate-ohms = <280>;
143 ti,esd-recovery-timeout-ms = <8000>;
144 };
145};
146
147&mmc2 {
148 interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>;
149
150 status = "okay";
151 pinctrl-names = "default";
152 pinctrl-0 = <&mmc2_pins>;
153 vmmc-supply = <&wl12xx_vmmc2>;
154 non-removable;
155 bus-width = <4>;
156 cap-power-off-card;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 wlcore: wlcore@2 {
160 compatible = "ti,wl1271";
161 reg = <2>;
162 interrupt-parent = <&gpio6>;
163 interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */
164 ref-clock-frequency = <26000000>;
165 tcxo-clock-frequency = <26000000>;
166 };
167};
168
169&uart2 {
170 pinctrl-names = "default";
171 pinctrl-0 = <&uart2_pins>;
172
173 bluetooth {
174 compatible = "ti,wl1271-st";
175 enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */
176 max-speed = <3000000>;
177 };
178};
179
180&omap3_pmx_core {
181
182 wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
183 pinctrl-single,pins = <
184 OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4) /* mmc1_dat7.gpio_129 */
185 >;
186 };
187
188 mmc2_pins: pinmux_mmc2_pins {
189 pinctrl-single,pins = <
190 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_clk.mmc2_clk */
191 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_cmd.mmc2_cmd */
192 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat0.mmc2_dat0 */
193 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat1.mmc2_dat1 */
194 OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat2.mmc2_dat2 */
195 OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc2_dat3.mmc2_dat3 */
196 OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */
197 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */
198 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */
199 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */
200 OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4) /* hdq_sio.gpio_170 */
201 >;
202 };
203
204 rtc_pins: pinmux_rtc_pins {
205 pinctrl-single,pins = <
206 OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */
207 >;
208 };
209
210 tsc2004_pins: pinmux_tsc2004_pins {
211 pinctrl-single,pins = <
212 OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */
213 >;
214 };
215
216 uart2_pins: pinmux_uart2_pins {
217 pinctrl-single,pins = <
218 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts */
219 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0) /* uart2_rts */
220 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx */
221 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx */
222 OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0) /* gpio_56 */
223 >;
224 };
225};
226
227&omap3_pmx_wkup {
228
229 wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins {
230 pinctrl-single,pins = <
231 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
232 >;
233 };
234};