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1// SPDX-License-Identifier: GPL-2.0-or-later
2/* SPDX-FileCopyrightText: Alexander Shiyan, <shc_work@mail.ru> */
3/* Based on code by myd_c335x.dts, MYiRtech.com */
4/* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ */
5
6/dts-v1/;
7
8#include "am335x-myirtech-myc.dtsi"
9
10#include <dt-bindings/display/tda998x.h>
11#include <dt-bindings/input/input.h>
12
13/ {
14 model = "MYIR MYD-AM335X";
15 compatible = "myir,myd-am335x", "myir,myc-am335x", "ti,am33xx";
16
17 chosen {
18 stdout-path = &uart0;
19 };
20
21 clk12m: clk12m {
22 compatible = "fixed-clock";
23 clock-frequency = <12000000>;
24
25 #clock-cells = <0>;
26 };
27
28 gpio_buttons: gpio_buttons {
29 compatible = "gpio-keys";
30 pinctrl-names = "default";
31 pinctrl-0 = <&gpio_buttons_pins>;
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 button1: button@0 {
36 reg = <0>;
37 label = "button1";
38 linux,code = <BTN_1>;
39 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
40 };
41
42 button2: button@1 {
43 reg = <1>;
44 label = "button2";
45 linux,code = <BTN_2>;
46 gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
47 };
48 };
49
50 sound: sound {
51 compatible = "simple-audio-card";
52 simple-audio-card,format = "i2s";
53 simple-audio-card,bitclock-master = <&master_codec>;
54 simple-audio-card,frame-master = <&master_codec>;
55
56 simple-audio-card,cpu {
57 sound-dai = <&mcasp0>;
58 };
59
60 master_codec: simple-audio-card,codec@1 {
61 sound-dai = <&sgtl5000>;
62 };
63
64 simple-audio-card,codec@2 {
65 sound-dai = <&tda9988>;
66 };
67 };
68
69 vdd_5v0: vdd_5v0_reg {
70 compatible = "regulator-fixed";
71 regulator-name = "vdd_5v0";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
74 regulator-always-on;
75 regulator-boot-on;
76 };
77
78 vdd_3v3: vdd_3v3_reg {
79 compatible = "regulator-fixed";
80 regulator-name = "vdd-3v3";
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 regulator-always-on;
84 regulator-boot-on;
85 vin-supply = <&vdd_5v0>;
86 };
87};
88
89&cpsw_emac1 {
90 phy-handle = <&phy1>;
91 phy-mode = "rgmii-id";
92};
93
94&davinci_mdio {
95 phy1: ethernet-phy@6 {
96 reg = <6>;
97 eee-broken-1000t;
98 };
99};
100
101&dcan0 {
102 pinctrl-names = "default", "sleep";
103 pinctrl-0 = <&dcan0_pins_default>;
104 pinctrl-1 = <&dcan0_pins_sleep>;
105 status = "okay";
106};
107
108&dcan1 {
109 pinctrl-names = "default", "sleep";
110 pinctrl-0 = <&dcan1_pins_default>;
111 pinctrl-1 = <&dcan1_pins_sleep>;
112 status = "okay";
113};
114
115&ehrpwm0 {
116 pinctrl-names = "default", "sleep";
117 pinctrl-0 = <&ehrpwm0_pins_default>;
118 pinctrl-1 = <&ehrpwm0_pins_sleep>;
119 status = "okay";
120};
121
122&epwmss0 {
123 status = "okay";
124};
125
126&i2c1 {
127 pinctrl-names = "default", "gpio", "sleep";
128 pinctrl-0 = <&i2c1_pins_default>;
129 pinctrl-1 = <&i2c1_pins_gpio>;
130 pinctrl-2 = <&i2c1_pins_sleep>;
131 clock-frequency = <400000>;
132 scl-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
133 sda-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
134 status = "okay";
135
136 sgtl5000: sgtl5000@a {
137 compatible = "fsl,sgtl5000";
138 reg =<0xa>;
139 clocks = <&clk12m>;
140 micbias-resistor-k-ohms = <4>;
141 micbias-voltage-m-volts = <2250>;
142 VDDA-supply = <&vdd_3v3>;
143 VDDIO-supply = <&vdd_3v3>;
144
145 #sound-dai-cells = <0>;
146 };
147
148 tda9988: tda9988@70 {
149 compatible = "nxp,tda998x";
150 reg =<0x70>;
151 audio-ports = <TDA998x_I2S 1>;
152
153 #sound-dai-cells = <0>;
154
155 ports {
156 port@0 {
157 hdmi_0: endpoint@0 {
158 remote-endpoint = <&lcdc_0>;
159 };
160 };
161 };
162 };
163};
164
165&lcdc {
166 pinctrl-names = "default", "sleep";
167 pinctrl-0 = <&lcdc_pins_default>;
168 pinctrl-1 = <&lcdc_pins_sleep>;
169 blue-and-red-wiring = "straight";
170 status = "okay";
171
172 port {
173 lcdc_0: endpoint@0 {
174 remote-endpoint = <&hdmi_0>;
175 };
176 };
177};
178
179&leds {
180 pinctrl-0 = <&led_mod_pins &leds_pins>;
181
182 led1: led1 {
183 label = "base:user1";
184 gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
185 color = <LED_COLOR_ID_GREEN>;
186 default-state = "off";
187 };
188
189 led2: led2 {
190 label = "base:user2";
191 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
192 color = <LED_COLOR_ID_GREEN>;
193 default-state = "off";
194 };
195};
196
197&mac {
198 pinctrl-0 = <ð_slave1_pins_default>, <ð_slave2_pins_default>;
199 pinctrl-1 = <ð_slave1_pins_sleep>, <ð_slave2_pins_sleep>;
200 slaves = <2>;
201};
202
203&mcasp0 {
204 pinctrl-names = "default", "sleep";
205 pinctrl-0 = <&mcasp0_pins_default>;
206 pinctrl-1 = <&mcasp0_pins_sleep>;
207 op-mode = <0>;
208 tdm-slots = <2>;
209 serial-dir = <0 1 2 0>;
210 tx-num-evt = <32>;
211 rx-num-evt = <32>;
212 status = "okay";
213
214 #sound-dai-cells = <0>;
215};
216
217&mmc1 {
218 pinctrl-names = "default", "sleep";
219 pinctrl-0 = <&mmc1_pins_default>;
220 pinctrl-1 = <&mmc1_pins_sleep>;
221 cd-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
222 bus-width = <4>;
223 vmmc-supply = <&vdd_3v3>;
224 status = "okay";
225};
226
227&nand0 {
228 partition@0 {
229 label = "MLO";
230 reg = <0x00000 0x20000>;
231 };
232
233 partition@20000 {
234 label = "boot";
235 reg = <0x20000 0x80000>;
236 };
237};
238
239&tscadc {
240 status = "okay";
241
242 adc: adc {
243 ti,adc-channels = <0 1 2 3 4 5 6>;
244 };
245};
246
247&uart0 {
248 pinctrl-names = "default";
249 pinctrl-0 = <&uart0_pins>;
250 status = "okay";
251};
252
253&uart1 {
254 pinctrl-names = "default", "sleep";
255 pinctrl-0 = <&uart1_pins_default>;
256 pinctrl-1 = <&uart1_pins_sleep>;
257 linux,rs485-enabled-at-boot-time;
258 status = "okay";
259};
260
261&uart2 {
262 pinctrl-names = "default", "sleep";
263 pinctrl-0 = <&uart2_pins_default>;
264 pinctrl-1 = <&uart2_pins_sleep>;
265 status = "okay";
266};
267
268&usb {
269 pinctrl-names = "default";
270 pinctrl-0 = <&usb_pins>;
271};
272
273&usb0 {
274 dr_mode = "otg";
275};
276
277&usb0_phy {
278 vcc-supply = <&vdd_5v0>;
279};
280
281&usb1 {
282 dr_mode = "host";
283};
284
285&usb1_phy {
286 vcc-supply = <&vdd_5v0>;
287};
288
289&vdd_mod {
290 vin-supply = <&vdd_3v3>;
291};
292
293&am33xx_pinmux {
294 dcan0_pins_default: pinmux_dcan0_pins_default {
295 pinctrl-single,pins = <
296 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan0_tx_mux2 */
297 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT, MUX_MODE2) /* dcan0_rx_mux2 */
298 >;
299 };
300
301 dcan0_pins_sleep: pinmux_dcan0_pins_sleep {
302 pinctrl-single,pins = <
303 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
304 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
305 >;
306 };
307
308 dcan1_pins_default: pinmux_dcan1_pins_default {
309 pinctrl-single,pins = <
310 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* dcan1_tx_mux0 */
311 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* dcan1_rx_mux0 */
312 >;
313 };
314
315 dcan1_pins_sleep: pinmux_dcan1_pins_sleep {
316 pinctrl-single,pins = <
317 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
318 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
319 >;
320 };
321
322 ehrpwm0_pins_default: pinmux_ehrpwm0_pins_default {
323 pinctrl-single,pins = <
324 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT, MUX_MODE3) /* ehrpwm0A_mux1 */
325 >;
326 };
327
328 ehrpwm0_pins_sleep: pinmux_ehrpwm0_pins_sleep {
329 pinctrl-single,pins = <
330 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
331 >;
332 };
333
334 eth_slave2_pins_default: pinmux_eth_slave2_pins_default {
335 pinctrl-single,pins = <
336 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tctl */
337 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rctl */
338 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td3 */
339 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td2 */
340 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td1 */
341 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_td0 */
342 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* rgmii2_tclk */
343 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rclk */
344 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd3 */
345 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2) /* rgmii2_rd2 */
346 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd1 */)
347 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2 /* rgmii2_rd0 */)
348 >;
349 };
350
351 eth_slave2_pins_sleep: pinmux_eth_slave2_pins_sleep {
352 pinctrl-single,pins = <
353 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
354 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
355 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
356 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
357 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
358 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
359 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
360 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
361 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
362 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
363 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
364 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
365 >;
366 };
367
368 gpio_buttons_pins: pinmux_gpio_buttons_pins {
369 pinctrl-single,pins = <
370 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpio3[0] */
371 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT, MUX_MODE7) /* gpio0[29] */
372 >;
373 };
374
375 i2c1_pins_default: pinmux_i2c1_pins_default {
376 pinctrl-single,pins = <
377 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SDA_mux3 */
378 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT | SLEWCTRL_FAST, MUX_MODE2) /* I2C1_SCL_mux3 */
379 >;
380 };
381
382 i2c1_pins_gpio: pinmux_i2c1_pins_gpio {
383 pinctrl-single,pins = <
384 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE7) /* gpio0[4] */
385 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE7) /* gpio0[5] */
386 >;
387 };
388
389 i2c1_pins_sleep: pinmux_i2c1_pins_sleep {
390 pinctrl-single,pins = <
391 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLDOWN, MUX_MODE7)
392 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLDOWN, MUX_MODE7)
393 >;
394 };
395
396 lcdc_pins_default: pinmux_lcdc_pins_default {
397 pinctrl-single,pins = <
398 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) /* lcd_data0 */
399 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) /* lcd_data1 */
400 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) /* lcd_data2 */
401 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) /* lcd_data3 */
402 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) /* lcd_data4 */
403 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) /* lcd_data5 */
404 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) /* lcd_data6 */
405 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) /* lcd_data7 */
406 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) /* lcd_data8 */
407 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) /* lcd_data9 */
408 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) /* lcd_data10 */
409 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) /* lcd_data11 */
410 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) /* lcd_data12 */
411 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) /* lcd_data13 */
412 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) /* lcd_data14 */
413 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) /* lcd_data15 */
414 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_vsync */
415 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) /* lcd_hsync */
416 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) /* lcd_pclk */
417 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) /* lcd_ac_bias_en */
418 >;
419 };
420
421 lcdc_pins_sleep: pinmux_lcdc_pins_sleep {
422 pinctrl-single,pins = <
423 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
424 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
425 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
426 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
427 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
428 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
429 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
430 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
431 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
432 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
433 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
434 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
435 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
436 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
437 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
438 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
439 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
440 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
441 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
442 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
443 >;
444 };
445
446 leds_pins: pinmux_leds_pins {
447 pinctrl-single,pins = <
448 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7) /* gpio0[27] */
449 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE7) /* gpio0[3] */
450 >;
451 };
452
453 mcasp0_pins_default: pinmux_mcasp0_pins_default {
454 pinctrl-single,pins = <
455 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_aclkx_mux0 */
456 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_fsx_mux0 */
457 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mcasp0_axr2_mux0 */
458 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE0) /* mcasp0_axr1_mux0 */
459 >;
460 };
461
462 mcasp0_pins_sleep: pinmux_mcasp0_pins_sleep {
463 pinctrl-single,pins = <
464 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE7)
465 AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE7)
466 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT_PULLDOWN, MUX_MODE7)
467 AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7)
468 >;
469 };
470
471 mmc1_pins_default: pinmux_mmc1_pins_default {
472 pinctrl-single,pins = <
473 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat3 */
474 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat2 */
475 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat1 */
476 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_dat0 */
477 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk */
478 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd */
479 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* gpio3[21] */
480 >;
481 };
482
483 mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
484 pinctrl-single,pins = <
485 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLDOWN, MUX_MODE0)
486 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLDOWN, MUX_MODE0)
487 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLDOWN, MUX_MODE0)
488 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLDOWN, MUX_MODE0)
489 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
490 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLDOWN, MUX_MODE0)
491 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7)
492 >;
493 };
494
495 uart0_pins: pinmux_uart0_pins {
496 pinctrl-single,pins = <
497 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart0_rxd */
498 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart0_txd */
499 >;
500 };
501
502 uart1_pins_default: pinmux_uart1_pins_default {
503 pinctrl-single,pins = <
504 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) /* uart1_rxd */
505 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* uart1_txd */
506 >;
507 };
508
509 uart1_pins_sleep: pinmux_uart1_pins_sleep {
510 pinctrl-single,pins = <
511 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLDOWN, MUX_MODE7)
512 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLDOWN, MUX_MODE7)
513 >;
514 };
515
516 uart2_pins_default: pinmux_uart2_pins_default {
517 pinctrl-single,pins = <
518 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE6) /* uart2_rxd_mux1 */
519 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_OUTPUT, MUX_MODE6) /* uart2_txd_mux1 */
520 >;
521 };
522
523 uart2_pins_sleep: pinmux_uart2_pins_sleep {
524 pinctrl-single,pins = <
525 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
526 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
527 >;
528 };
529
530 usb_pins: pinmux_usb_pins {
531 pinctrl-single,pins = <
532 AM33XX_PADCONF(AM335X_PIN_USB0_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB0_DRVVBUS */
533 AM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* USB1_DRVVBUS */
534 >;
535 };
536};