1/*
 2 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 */
 8
 9/ {
10	compatible = "snps,arc";
11	#address-cells = <1>;
12	#size-cells = <1>;
13	chosen { };
14	aliases { };
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu@0 {
21			device_type = "cpu";
22			compatible = "snps,archs38";
23			reg = <0>;
24			clocks = <&core_clk>;
25		};
26		cpu@1 {
27			device_type = "cpu";
28			compatible = "snps,archs38";
29			reg = <1>;
30			clocks = <&core_clk>;
31		};
32		cpu@2 {
33			device_type = "cpu";
34			compatible = "snps,archs38";
35			reg = <2>;
36			clocks = <&core_clk>;
37		};
38		cpu@3 {
39			device_type = "cpu";
40			compatible = "snps,archs38";
41			reg = <3>;
42			clocks = <&core_clk>;
43		};
44	};
45
46	/* TIMER0 with interrupt for clockevent */
47	timer0 {
48		compatible = "snps,arc-timer";
49		interrupts = <16>;
50		interrupt-parent = <&core_intc>;
51		clocks = <&core_clk>;
52	};
53
54	/* 64-bit Global Free Running Counter */
55	gfrc {
56		compatible = "snps,archs-timer-gfrc";
57		clocks = <&core_clk>;
58	};
59
60	memory {
61		device_type = "memory";
62		reg = <0x80000000 0x10000000>;	/* 256M */
63	};
64};

 1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
 
 
 
 
 4 */
 5
 6/ {
 7	compatible = "snps,arc";
 8	#address-cells = <1>;
 9	#size-cells = <1>;
10	chosen { };
11	aliases { };
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "snps,archs38";
20			reg = <0>;
21			clocks = <&core_clk>;
22		};
23		cpu@1 {
24			device_type = "cpu";
25			compatible = "snps,archs38";
26			reg = <1>;
27			clocks = <&core_clk>;
28		};
29		cpu@2 {
30			device_type = "cpu";
31			compatible = "snps,archs38";
32			reg = <2>;
33			clocks = <&core_clk>;
34		};
35		cpu@3 {
36			device_type = "cpu";
37			compatible = "snps,archs38";
38			reg = <3>;
39			clocks = <&core_clk>;
40		};
41	};
42
43	/* TIMER0 with interrupt for clockevent */
44	timer0 {
45		compatible = "snps,arc-timer";
46		interrupts = <16>;
47		interrupt-parent = <&core_intc>;
48		clocks = <&core_clk>;
49	};
50
51	/* 64-bit Global Free Running Counter */
52	gfrc {
53		compatible = "snps,archs-timer-gfrc";
54		clocks = <&core_clk>;
55	};
56
57	memory {
58		device_type = "memory";
59		reg = <0x80000000 0x10000000>;	/* 256M */
60	};
61};