1/*
 2 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 */
 8
 9/ {
10	compatible = "snps,arc";
11	#address-cells = <1>;
12	#size-cells = <1>;
13	chosen { };
14	aliases { };
15
16	cpus {
17		#address-cells = <1>;
18		#size-cells = <0>;
19
20		cpu@0 {
21			device_type = "cpu";
22			compatible = "snps,archs38";
23			reg = <0>;
24			clocks = <&core_clk>;
25		};
26	};
27
28	/* TIMER0 with interrupt for clockevent */
29	timer0 {
30		compatible = "snps,arc-timer";
31		interrupts = <16>;
32		interrupt-parent = <&core_intc>;
33		clocks = <&core_clk>;
34	};
35
36	/* 64-bit Local RTC: preferred clocksource for UP */
37	rtc {
38		compatible = "snps,archs-timer-rtc";
39		clocks = <&core_clk>;
40	};
41
42	/* TIMER1 for free running clocksource: Fallback if rtc not found */
43	timer1 {
44		compatible = "snps,arc-timer";
45		clocks = <&core_clk>;
46	};
47
48	memory {
49		device_type = "memory";
50		reg = <0x80000000 0x10000000>;	/* 256M */
51	};
52};

 1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
 
 
 
 
 4 */
 5
 6/ {
 7	compatible = "snps,arc";
 8	#address-cells = <1>;
 9	#size-cells = <1>;
10	chosen { };
11	aliases { };
12
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "snps,archs38";
20			reg = <0>;
21			clocks = <&core_clk>;
22		};
23	};
24
25	/* TIMER0 with interrupt for clockevent */
26	timer0 {
27		compatible = "snps,arc-timer";
28		interrupts = <16>;
29		interrupt-parent = <&core_intc>;
30		clocks = <&core_clk>;
31	};
32
33	/* 64-bit Local RTC: preferred clocksource for UP */
34	rtc {
35		compatible = "snps,archs-timer-rtc";
36		clocks = <&core_clk>;
37	};
38
39	/* TIMER1 for free running clocksource: Fallback if rtc not found */
40	timer1 {
41		compatible = "snps,arc-timer";
42		clocks = <&core_clk>;
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x80000000 0x10000000>;	/* 256M */
48	};
49};