1/*
  2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 as
  6 * published by the Free Software Foundation.
  7 */
  8/dts-v1/;
  9
 10/include/ "skeleton_hs_idu.dtsi"
 11
 12/ {
 13	model = "snps,nsimosci_hs-smp";
 14	compatible = "snps,nsimosci_hs";
 15	#address-cells = <1>;
 16	#size-cells = <1>;
 17	interrupt-parent = <&core_intc>;
 18
 19	chosen {
 20		/* this is for console on serial */
 21		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
 22	};
 23
 24	aliases {
 25		serial0 = &uart0;
 26	};
 27
 28	fpga {
 29		compatible = "simple-bus";
 30		#address-cells = <1>;
 31		#size-cells = <1>;
 32
 33		/* child and parent address space 1:1 mapped */
 34		ranges;
 35
 36		core_clk: core_clk {
 37			#clock-cells = <0>;
 38			compatible = "fixed-clock";
 39			clock-frequency = <5000000>;
 40		};
 41
 42		core_intc: core-interrupt-controller {
 43			compatible = "snps,archs-intc";
 44			interrupt-controller;
 45			#interrupt-cells = <1>;
 46		};
 47
 48		idu_intc: idu-interrupt-controller {
 49			compatible = "snps,archs-idu-intc";
 50			interrupt-controller;
 51			interrupt-parent = <&core_intc>;
 52			#interrupt-cells = <1>;
 53		};
 54
 55		uart0: serial@f0000000 {
 56			compatible = "ns8250";
 57			reg = <0xf0000000 0x2000>;
 58			interrupt-parent = <&idu_intc>;
 59			interrupts = <0>;
 60			clock-frequency = <3686400>;
 61			baud = <115200>;
 62			reg-shift = <2>;
 63			reg-io-width = <4>;
 64			no-loopback-test = <1>;
 65		};
 66
 67		pguclk: pguclk {
 68			#clock-cells = <0>;
 69			compatible = "fixed-clock";
 70			clock-frequency = <25175000>;
 71		};
 72
 73		pgu@f9000000 {
 74			compatible = "snps,arcpgu";
 75			reg = <0xf9000000 0x400>;
 76			clocks = <&pguclk>;
 77			clock-names = "pxlclk";
 78		};
 79
 80		ps2: ps2@f9001000 {
 81			compatible = "snps,arc_ps2";
 82			reg = <0xf9000400 0x14>;
 83			interrupts = <3>;
 84			interrupt-parent = <&idu_intc>;
 85			interrupt-names = "arc_ps2_irq";
 86		};
 87
 88		eth0: ethernet@f0003000 {
 89			compatible = "ezchip,nps-mgt-enet";
 90			reg = <0xf0003000 0x44>;
 91			interrupt-parent = <&idu_intc>;
 92			interrupts = <1>;
 93		};
 94
 95		arcpct0: pct {
 96			compatible = "snps,archs-pct";
 97			#interrupt-cells = <1>;
 98			interrupts = <20>;
 99		};
100	};
101};

 1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
 
 
 
 
 4 */
 5/dts-v1/;
 6
 7/include/ "skeleton_hs_idu.dtsi"
 8
 9/ {
10	model = "snps,nsimosci_hs-smp";
11	compatible = "snps,nsimosci_hs";
12	#address-cells = <1>;
13	#size-cells = <1>;
14	interrupt-parent = <&core_intc>;
15
16	chosen {
17		/* this is for console on serial */
18		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
19	};
20
21	aliases {
22		serial0 = &uart0;
23	};
24
25	fpga {
26		compatible = "simple-bus";
27		#address-cells = <1>;
28		#size-cells = <1>;
29
30		/* child and parent address space 1:1 mapped */
31		ranges;
32
33		core_clk: core_clk {
34			#clock-cells = <0>;
35			compatible = "fixed-clock";
36			clock-frequency = <5000000>;
37		};
38
39		core_intc: core-interrupt-controller {
40			compatible = "snps,archs-intc";
41			interrupt-controller;
42			#interrupt-cells = <1>;
43		};
44
45		idu_intc: idu-interrupt-controller {
46			compatible = "snps,archs-idu-intc";
47			interrupt-controller;
48			interrupt-parent = <&core_intc>;
49			#interrupt-cells = <1>;
50		};
51
52		uart0: serial@f0000000 {
53			compatible = "ns8250";
54			reg = <0xf0000000 0x2000>;
55			interrupt-parent = <&idu_intc>;
56			interrupts = <0>;
57			clock-frequency = <3686400>;
58			baud = <115200>;
59			reg-shift = <2>;
60			reg-io-width = <4>;
61			no-loopback-test = <1>;
62		};
63
64		pguclk: pguclk {
65			#clock-cells = <0>;
66			compatible = "fixed-clock";
67			clock-frequency = <25175000>;
68		};
69
70		pgu@f9000000 {
71			compatible = "snps,arcpgu";
72			reg = <0xf9000000 0x400>;
73			clocks = <&pguclk>;
74			clock-names = "pxlclk";
75		};
76
77		ps2: ps2@f9001000 {
78			compatible = "snps,arc_ps2";
79			reg = <0xf9000400 0x14>;
80			interrupts = <3>;
81			interrupt-parent = <&idu_intc>;
82			interrupt-names = "arc_ps2_irq";
83		};
84
85		eth0: ethernet@f0003000 {
86			compatible = "ezchip,nps-mgt-enet";
87			reg = <0xf0003000 0x44>;
88			interrupt-parent = <&idu_intc>;
89			interrupts = <1>;
90		};
91
92		arcpct0: pct {
93			compatible = "snps,archs-pct";
94			#interrupt-cells = <1>;
95			interrupts = <20>;
96		};
97	};
98};