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1/*
2 * ECAP PWM driver
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/io.h>
24#include <linux/err.h>
25#include <linux/clk.h>
26#include <linux/pm_runtime.h>
27#include <linux/pwm.h>
28#include <linux/of_device.h>
29
30/* ECAP registers and bits definitions */
31#define CAP1 0x08
32#define CAP2 0x0C
33#define CAP3 0x10
34#define CAP4 0x14
35#define ECCTL2 0x2A
36#define ECCTL2_APWM_POL_LOW BIT(10)
37#define ECCTL2_APWM_MODE BIT(9)
38#define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
39#define ECCTL2_TSCTR_FREERUN BIT(4)
40
41struct ecap_context {
42 u32 cap3;
43 u32 cap4;
44 u16 ecctl2;
45};
46
47struct ecap_pwm_chip {
48 struct pwm_chip chip;
49 unsigned int clk_rate;
50 void __iomem *mmio_base;
51 struct ecap_context ctx;
52};
53
54static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
55{
56 return container_of(chip, struct ecap_pwm_chip, chip);
57}
58
59/*
60 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
61 * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
62 */
63static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
64 int duty_ns, int period_ns)
65{
66 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
67 u32 period_cycles, duty_cycles;
68 unsigned long long c;
69 u16 value;
70
71 if (period_ns > NSEC_PER_SEC)
72 return -ERANGE;
73
74 c = pc->clk_rate;
75 c = c * period_ns;
76 do_div(c, NSEC_PER_SEC);
77 period_cycles = (u32)c;
78
79 if (period_cycles < 1) {
80 period_cycles = 1;
81 duty_cycles = 1;
82 } else {
83 c = pc->clk_rate;
84 c = c * duty_ns;
85 do_div(c, NSEC_PER_SEC);
86 duty_cycles = (u32)c;
87 }
88
89 pm_runtime_get_sync(pc->chip.dev);
90
91 value = readw(pc->mmio_base + ECCTL2);
92
93 /* Configure APWM mode & disable sync option */
94 value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
95
96 writew(value, pc->mmio_base + ECCTL2);
97
98 if (!pwm_is_enabled(pwm)) {
99 /* Update active registers if not running */
100 writel(duty_cycles, pc->mmio_base + CAP2);
101 writel(period_cycles, pc->mmio_base + CAP1);
102 } else {
103 /*
104 * Update shadow registers to configure period and
105 * compare values. This helps current PWM period to
106 * complete on reconfiguring
107 */
108 writel(duty_cycles, pc->mmio_base + CAP4);
109 writel(period_cycles, pc->mmio_base + CAP3);
110 }
111
112 if (!pwm_is_enabled(pwm)) {
113 value = readw(pc->mmio_base + ECCTL2);
114 /* Disable APWM mode to put APWM output Low */
115 value &= ~ECCTL2_APWM_MODE;
116 writew(value, pc->mmio_base + ECCTL2);
117 }
118
119 pm_runtime_put_sync(pc->chip.dev);
120
121 return 0;
122}
123
124static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
125 enum pwm_polarity polarity)
126{
127 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
128 u16 value;
129
130 pm_runtime_get_sync(pc->chip.dev);
131
132 value = readw(pc->mmio_base + ECCTL2);
133
134 if (polarity == PWM_POLARITY_INVERSED)
135 /* Duty cycle defines LOW period of PWM */
136 value |= ECCTL2_APWM_POL_LOW;
137 else
138 /* Duty cycle defines HIGH period of PWM */
139 value &= ~ECCTL2_APWM_POL_LOW;
140
141 writew(value, pc->mmio_base + ECCTL2);
142
143 pm_runtime_put_sync(pc->chip.dev);
144
145 return 0;
146}
147
148static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
149{
150 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
151 u16 value;
152
153 /* Leave clock enabled on enabling PWM */
154 pm_runtime_get_sync(pc->chip.dev);
155
156 /*
157 * Enable 'Free run Time stamp counter mode' to start counter
158 * and 'APWM mode' to enable APWM output
159 */
160 value = readw(pc->mmio_base + ECCTL2);
161 value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
162 writew(value, pc->mmio_base + ECCTL2);
163
164 return 0;
165}
166
167static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
168{
169 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
170 u16 value;
171
172 /*
173 * Disable 'Free run Time stamp counter mode' to stop counter
174 * and 'APWM mode' to put APWM output to low
175 */
176 value = readw(pc->mmio_base + ECCTL2);
177 value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
178 writew(value, pc->mmio_base + ECCTL2);
179
180 /* Disable clock on PWM disable */
181 pm_runtime_put_sync(pc->chip.dev);
182}
183
184static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
185{
186 if (pwm_is_enabled(pwm)) {
187 dev_warn(chip->dev, "Removing PWM device without disabling\n");
188 pm_runtime_put_sync(chip->dev);
189 }
190}
191
192static const struct pwm_ops ecap_pwm_ops = {
193 .free = ecap_pwm_free,
194 .config = ecap_pwm_config,
195 .set_polarity = ecap_pwm_set_polarity,
196 .enable = ecap_pwm_enable,
197 .disable = ecap_pwm_disable,
198 .owner = THIS_MODULE,
199};
200
201static const struct of_device_id ecap_of_match[] = {
202 { .compatible = "ti,am3352-ecap" },
203 { .compatible = "ti,am33xx-ecap" },
204 {},
205};
206MODULE_DEVICE_TABLE(of, ecap_of_match);
207
208static int ecap_pwm_probe(struct platform_device *pdev)
209{
210 struct device_node *np = pdev->dev.of_node;
211 struct ecap_pwm_chip *pc;
212 struct resource *r;
213 struct clk *clk;
214 int ret;
215
216 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
217 if (!pc)
218 return -ENOMEM;
219
220 clk = devm_clk_get(&pdev->dev, "fck");
221 if (IS_ERR(clk)) {
222 if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
223 dev_warn(&pdev->dev, "Binding is obsolete.\n");
224 clk = devm_clk_get(pdev->dev.parent, "fck");
225 }
226 }
227
228 if (IS_ERR(clk)) {
229 dev_err(&pdev->dev, "failed to get clock\n");
230 return PTR_ERR(clk);
231 }
232
233 pc->clk_rate = clk_get_rate(clk);
234 if (!pc->clk_rate) {
235 dev_err(&pdev->dev, "failed to get clock rate\n");
236 return -EINVAL;
237 }
238
239 pc->chip.dev = &pdev->dev;
240 pc->chip.ops = &ecap_pwm_ops;
241 pc->chip.of_xlate = of_pwm_xlate_with_flags;
242 pc->chip.of_pwm_n_cells = 3;
243 pc->chip.base = -1;
244 pc->chip.npwm = 1;
245
246 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
247 pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
248 if (IS_ERR(pc->mmio_base))
249 return PTR_ERR(pc->mmio_base);
250
251 ret = pwmchip_add(&pc->chip);
252 if (ret < 0) {
253 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
254 return ret;
255 }
256
257 platform_set_drvdata(pdev, pc);
258 pm_runtime_enable(&pdev->dev);
259
260 return 0;
261}
262
263static int ecap_pwm_remove(struct platform_device *pdev)
264{
265 struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
266
267 pm_runtime_disable(&pdev->dev);
268
269 return pwmchip_remove(&pc->chip);
270}
271
272#ifdef CONFIG_PM_SLEEP
273static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
274{
275 pm_runtime_get_sync(pc->chip.dev);
276 pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
277 pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
278 pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
279 pm_runtime_put_sync(pc->chip.dev);
280}
281
282static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
283{
284 writel(pc->ctx.cap3, pc->mmio_base + CAP3);
285 writel(pc->ctx.cap4, pc->mmio_base + CAP4);
286 writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
287}
288
289static int ecap_pwm_suspend(struct device *dev)
290{
291 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
292 struct pwm_device *pwm = pc->chip.pwms;
293
294 ecap_pwm_save_context(pc);
295
296 /* Disable explicitly if PWM is running */
297 if (pwm_is_enabled(pwm))
298 pm_runtime_put_sync(dev);
299
300 return 0;
301}
302
303static int ecap_pwm_resume(struct device *dev)
304{
305 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
306 struct pwm_device *pwm = pc->chip.pwms;
307
308 /* Enable explicitly if PWM was running */
309 if (pwm_is_enabled(pwm))
310 pm_runtime_get_sync(dev);
311
312 ecap_pwm_restore_context(pc);
313 return 0;
314}
315#endif
316
317static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
318
319static struct platform_driver ecap_pwm_driver = {
320 .driver = {
321 .name = "ecap",
322 .of_match_table = ecap_of_match,
323 .pm = &ecap_pwm_pm_ops,
324 },
325 .probe = ecap_pwm_probe,
326 .remove = ecap_pwm_remove,
327};
328module_platform_driver(ecap_pwm_driver);
329
330MODULE_DESCRIPTION("ECAP PWM driver");
331MODULE_AUTHOR("Texas Instruments");
332MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ECAP PWM driver
4 *
5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
6 */
7
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/io.h>
11#include <linux/err.h>
12#include <linux/clk.h>
13#include <linux/pm_runtime.h>
14#include <linux/pwm.h>
15#include <linux/of_device.h>
16
17/* ECAP registers and bits definitions */
18#define CAP1 0x08
19#define CAP2 0x0C
20#define CAP3 0x10
21#define CAP4 0x14
22#define ECCTL2 0x2A
23#define ECCTL2_APWM_POL_LOW BIT(10)
24#define ECCTL2_APWM_MODE BIT(9)
25#define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
26#define ECCTL2_TSCTR_FREERUN BIT(4)
27
28struct ecap_context {
29 u32 cap3;
30 u32 cap4;
31 u16 ecctl2;
32};
33
34struct ecap_pwm_chip {
35 struct pwm_chip chip;
36 unsigned int clk_rate;
37 void __iomem *mmio_base;
38 struct ecap_context ctx;
39};
40
41static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
42{
43 return container_of(chip, struct ecap_pwm_chip, chip);
44}
45
46/*
47 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
48 * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
49 */
50static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
51 int duty_ns, int period_ns, int enabled)
52{
53 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
54 u32 period_cycles, duty_cycles;
55 unsigned long long c;
56 u16 value;
57
58 c = pc->clk_rate;
59 c = c * period_ns;
60 do_div(c, NSEC_PER_SEC);
61 period_cycles = (u32)c;
62
63 if (period_cycles < 1) {
64 period_cycles = 1;
65 duty_cycles = 1;
66 } else {
67 c = pc->clk_rate;
68 c = c * duty_ns;
69 do_div(c, NSEC_PER_SEC);
70 duty_cycles = (u32)c;
71 }
72
73 pm_runtime_get_sync(pc->chip.dev);
74
75 value = readw(pc->mmio_base + ECCTL2);
76
77 /* Configure APWM mode & disable sync option */
78 value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
79
80 writew(value, pc->mmio_base + ECCTL2);
81
82 if (!enabled) {
83 /* Update active registers if not running */
84 writel(duty_cycles, pc->mmio_base + CAP2);
85 writel(period_cycles, pc->mmio_base + CAP1);
86 } else {
87 /*
88 * Update shadow registers to configure period and
89 * compare values. This helps current PWM period to
90 * complete on reconfiguring
91 */
92 writel(duty_cycles, pc->mmio_base + CAP4);
93 writel(period_cycles, pc->mmio_base + CAP3);
94 }
95
96 if (!enabled) {
97 value = readw(pc->mmio_base + ECCTL2);
98 /* Disable APWM mode to put APWM output Low */
99 value &= ~ECCTL2_APWM_MODE;
100 writew(value, pc->mmio_base + ECCTL2);
101 }
102
103 pm_runtime_put_sync(pc->chip.dev);
104
105 return 0;
106}
107
108static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
109 enum pwm_polarity polarity)
110{
111 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
112 u16 value;
113
114 pm_runtime_get_sync(pc->chip.dev);
115
116 value = readw(pc->mmio_base + ECCTL2);
117
118 if (polarity == PWM_POLARITY_INVERSED)
119 /* Duty cycle defines LOW period of PWM */
120 value |= ECCTL2_APWM_POL_LOW;
121 else
122 /* Duty cycle defines HIGH period of PWM */
123 value &= ~ECCTL2_APWM_POL_LOW;
124
125 writew(value, pc->mmio_base + ECCTL2);
126
127 pm_runtime_put_sync(pc->chip.dev);
128
129 return 0;
130}
131
132static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
133{
134 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
135 u16 value;
136
137 /* Leave clock enabled on enabling PWM */
138 pm_runtime_get_sync(pc->chip.dev);
139
140 /*
141 * Enable 'Free run Time stamp counter mode' to start counter
142 * and 'APWM mode' to enable APWM output
143 */
144 value = readw(pc->mmio_base + ECCTL2);
145 value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
146 writew(value, pc->mmio_base + ECCTL2);
147
148 return 0;
149}
150
151static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
152{
153 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
154 u16 value;
155
156 /*
157 * Disable 'Free run Time stamp counter mode' to stop counter
158 * and 'APWM mode' to put APWM output to low
159 */
160 value = readw(pc->mmio_base + ECCTL2);
161 value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
162 writew(value, pc->mmio_base + ECCTL2);
163
164 /* Disable clock on PWM disable */
165 pm_runtime_put_sync(pc->chip.dev);
166}
167
168static int ecap_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
169 const struct pwm_state *state)
170{
171 int err;
172 int enabled = pwm->state.enabled;
173
174 if (state->polarity != pwm->state.polarity) {
175
176 if (enabled) {
177 ecap_pwm_disable(chip, pwm);
178 enabled = false;
179 }
180
181 err = ecap_pwm_set_polarity(chip, pwm, state->polarity);
182 if (err)
183 return err;
184 }
185
186 if (!state->enabled) {
187 if (enabled)
188 ecap_pwm_disable(chip, pwm);
189 return 0;
190 }
191
192 if (state->period > NSEC_PER_SEC)
193 return -ERANGE;
194
195 err = ecap_pwm_config(chip, pwm, state->duty_cycle,
196 state->period, enabled);
197 if (err)
198 return err;
199
200 if (!enabled)
201 return ecap_pwm_enable(chip, pwm);
202
203 return 0;
204}
205
206static const struct pwm_ops ecap_pwm_ops = {
207 .apply = ecap_pwm_apply,
208 .owner = THIS_MODULE,
209};
210
211static const struct of_device_id ecap_of_match[] = {
212 { .compatible = "ti,am3352-ecap" },
213 { .compatible = "ti,am33xx-ecap" },
214 {},
215};
216MODULE_DEVICE_TABLE(of, ecap_of_match);
217
218static int ecap_pwm_probe(struct platform_device *pdev)
219{
220 struct device_node *np = pdev->dev.of_node;
221 struct ecap_pwm_chip *pc;
222 struct clk *clk;
223 int ret;
224
225 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
226 if (!pc)
227 return -ENOMEM;
228
229 clk = devm_clk_get(&pdev->dev, "fck");
230 if (IS_ERR(clk)) {
231 if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
232 dev_warn(&pdev->dev, "Binding is obsolete.\n");
233 clk = devm_clk_get(pdev->dev.parent, "fck");
234 }
235 }
236
237 if (IS_ERR(clk)) {
238 dev_err(&pdev->dev, "failed to get clock\n");
239 return PTR_ERR(clk);
240 }
241
242 pc->clk_rate = clk_get_rate(clk);
243 if (!pc->clk_rate) {
244 dev_err(&pdev->dev, "failed to get clock rate\n");
245 return -EINVAL;
246 }
247
248 pc->chip.dev = &pdev->dev;
249 pc->chip.ops = &ecap_pwm_ops;
250 pc->chip.npwm = 1;
251
252 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);
253 if (IS_ERR(pc->mmio_base))
254 return PTR_ERR(pc->mmio_base);
255
256 ret = pwmchip_add(&pc->chip);
257 if (ret < 0) {
258 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
259 return ret;
260 }
261
262 platform_set_drvdata(pdev, pc);
263 pm_runtime_enable(&pdev->dev);
264
265 return 0;
266}
267
268static int ecap_pwm_remove(struct platform_device *pdev)
269{
270 struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
271
272 pm_runtime_disable(&pdev->dev);
273
274 return pwmchip_remove(&pc->chip);
275}
276
277#ifdef CONFIG_PM_SLEEP
278static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
279{
280 pm_runtime_get_sync(pc->chip.dev);
281 pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
282 pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
283 pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
284 pm_runtime_put_sync(pc->chip.dev);
285}
286
287static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
288{
289 writel(pc->ctx.cap3, pc->mmio_base + CAP3);
290 writel(pc->ctx.cap4, pc->mmio_base + CAP4);
291 writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
292}
293
294static int ecap_pwm_suspend(struct device *dev)
295{
296 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
297 struct pwm_device *pwm = pc->chip.pwms;
298
299 ecap_pwm_save_context(pc);
300
301 /* Disable explicitly if PWM is running */
302 if (pwm_is_enabled(pwm))
303 pm_runtime_put_sync(dev);
304
305 return 0;
306}
307
308static int ecap_pwm_resume(struct device *dev)
309{
310 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
311 struct pwm_device *pwm = pc->chip.pwms;
312
313 /* Enable explicitly if PWM was running */
314 if (pwm_is_enabled(pwm))
315 pm_runtime_get_sync(dev);
316
317 ecap_pwm_restore_context(pc);
318 return 0;
319}
320#endif
321
322static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
323
324static struct platform_driver ecap_pwm_driver = {
325 .driver = {
326 .name = "ecap",
327 .of_match_table = ecap_of_match,
328 .pm = &ecap_pwm_pm_ops,
329 },
330 .probe = ecap_pwm_probe,
331 .remove = ecap_pwm_remove,
332};
333module_platform_driver(ecap_pwm_driver);
334
335MODULE_DESCRIPTION("ECAP PWM driver");
336MODULE_AUTHOR("Texas Instruments");
337MODULE_LICENSE("GPL");