1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (C) 2013 NVIDIA Corporation
  4 * Copyright (C) 2018 Cadence Design Systems Inc.
  5 */
  6
  7#include <linux/errno.h>
  8#include <linux/export.h>
  9#include <linux/kernel.h>
 10#include <linux/time64.h>
 11
 12#include <linux/phy/phy.h>
 13#include <linux/phy/phy-mipi-dphy.h>
 14
 15/*
 16 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
 17 * from the valid ranges specified in Section 6.9, Table 14, Page 41
 18 * of the D-PHY specification (v1.2).
 19 */
 20int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
 21				     unsigned int bpp,
 22				     unsigned int lanes,
 23				     struct phy_configure_opts_mipi_dphy *cfg)
 24{
 25	unsigned long long hs_clk_rate;
 26	unsigned long long ui;
 27
 28	if (!cfg)
 29		return -EINVAL;
 30
 31	hs_clk_rate = pixel_clock * bpp;
 32	do_div(hs_clk_rate, lanes);
 33
 34	ui = ALIGN(PSEC_PER_SEC, hs_clk_rate);
 35	do_div(ui, hs_clk_rate);
 36
 37	cfg->clk_miss = 0;
 38	cfg->clk_post = 60000 + 52 * ui;
 39	cfg->clk_pre = 8000;
 40	cfg->clk_prepare = 38000;
 41	cfg->clk_settle = 95000;
 42	cfg->clk_term_en = 0;
 43	cfg->clk_trail = 60000;
 44	cfg->clk_zero = 262000;
 45	cfg->d_term_en = 0;
 46	cfg->eot = 0;
 47	cfg->hs_exit = 100000;
 48	cfg->hs_prepare = 40000 + 4 * ui;
 49	cfg->hs_zero = 105000 + 6 * ui;
 50	cfg->hs_settle = 85000 + 6 * ui;
 51	cfg->hs_skip = 40000;
 52
 53	/*
 54	 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
 55	 * contains this formula as:
 56	 *
 57	 *     T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui)
 58	 *
 59	 * where n = 1 for forward-direction HS mode and n = 4 for reverse-
 60	 * direction HS mode. There's only one setting and this function does
 61	 * not parameterize on anything other that ui, so this code will
 62	 * assumes that reverse-direction HS mode is supported and uses n = 4.
 63	 */
 64	cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui);
 65
 66	cfg->init = 100;
 67	cfg->lpx = 60000;
 68	cfg->ta_get = 5 * cfg->lpx;
 69	cfg->ta_go = 4 * cfg->lpx;
 70	cfg->ta_sure = 2 * cfg->lpx;
 71	cfg->wakeup = 1000;
 72
 73	cfg->hs_clk_rate = hs_clk_rate;
 74	cfg->lanes = lanes;
 75
 76	return 0;
 77}
 78EXPORT_SYMBOL(phy_mipi_dphy_get_default_config);
 79
 80/*
 81 * Validate D-PHY configuration according to MIPI D-PHY specification
 82 * (v1.2, Section Section 6.9 "Global Operation Timing Parameters").
 83 */
 84int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg)
 85{
 86	unsigned long long ui;
 87
 88	if (!cfg)
 89		return -EINVAL;
 90
 91	ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate);
 92	do_div(ui, cfg->hs_clk_rate);
 93
 94	if (cfg->clk_miss > 60000)
 95		return -EINVAL;
 96
 97	if (cfg->clk_post < (60000 + 52 * ui))
 98		return -EINVAL;
 99
100	if (cfg->clk_pre < 8000)
101		return -EINVAL;
102
103	if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000)
104		return -EINVAL;
105
106	if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000)
107		return -EINVAL;
108
109	if (cfg->clk_term_en > 38000)
110		return -EINVAL;
111
112	if (cfg->clk_trail < 60000)
113		return -EINVAL;
114
115	if ((cfg->clk_prepare + cfg->clk_zero) < 300000)
116		return -EINVAL;
117
118	if (cfg->d_term_en > (35000 + 4 * ui))
119		return -EINVAL;
120
121	if (cfg->eot > (105000 + 12 * ui))
122		return -EINVAL;
123
124	if (cfg->hs_exit < 100000)
125		return -EINVAL;
126
127	if (cfg->hs_prepare < (40000 + 4 * ui) ||
128	    cfg->hs_prepare > (85000 + 6 * ui))
129		return -EINVAL;
130
131	if ((cfg->hs_prepare + cfg->hs_zero) < (145000 + 10 * ui))
132		return -EINVAL;
133
134	if ((cfg->hs_settle < (85000 + 6 * ui)) ||
135	    (cfg->hs_settle > (145000 + 10 * ui)))
136		return -EINVAL;
137
138	if (cfg->hs_skip < 40000 || cfg->hs_skip > (55000 + 4 * ui))
139		return -EINVAL;
140
141	if (cfg->hs_trail < max(8 * ui, 60000 + 4 * ui))
142		return -EINVAL;
143
144	if (cfg->init < 100)
145		return -EINVAL;
146
147	if (cfg->lpx < 50000)
148		return -EINVAL;
149
150	if (cfg->ta_get != (5 * cfg->lpx))
151		return -EINVAL;
152
153	if (cfg->ta_go != (4 * cfg->lpx))
154		return -EINVAL;
155
156	if (cfg->ta_sure < cfg->lpx || cfg->ta_sure > (2 * cfg->lpx))
157		return -EINVAL;
158
159	if (cfg->wakeup < 1000)
160		return -EINVAL;
161
162	return 0;
163}
164EXPORT_SYMBOL(phy_mipi_dphy_config_validate);