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1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/mailbox_controller.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21
22#include <dt-bindings/mailbox/tegra186-hsp.h>
23
24#define HSP_INT_DIMENSIONING 0x380
25#define HSP_nSM_SHIFT 0
26#define HSP_nSS_SHIFT 4
27#define HSP_nAS_SHIFT 8
28#define HSP_nDB_SHIFT 12
29#define HSP_nSI_SHIFT 16
30#define HSP_nINT_MASK 0xf
31
32#define HSP_DB_TRIGGER 0x0
33#define HSP_DB_ENABLE 0x4
34#define HSP_DB_RAW 0x8
35#define HSP_DB_PENDING 0xc
36
37#define HSP_DB_CCPLEX 1
38#define HSP_DB_BPMP 3
39#define HSP_DB_MAX 7
40
41struct tegra_hsp_channel;
42struct tegra_hsp;
43
44struct tegra_hsp_channel {
45 struct tegra_hsp *hsp;
46 struct mbox_chan *chan;
47 void __iomem *regs;
48};
49
50struct tegra_hsp_doorbell {
51 struct tegra_hsp_channel channel;
52 struct list_head list;
53 const char *name;
54 unsigned int master;
55 unsigned int index;
56};
57
58struct tegra_hsp_db_map {
59 const char *name;
60 unsigned int master;
61 unsigned int index;
62};
63
64struct tegra_hsp_soc {
65 const struct tegra_hsp_db_map *map;
66};
67
68struct tegra_hsp {
69 const struct tegra_hsp_soc *soc;
70 struct mbox_controller mbox;
71 void __iomem *regs;
72 unsigned int irq;
73 unsigned int num_sm;
74 unsigned int num_as;
75 unsigned int num_ss;
76 unsigned int num_db;
77 unsigned int num_si;
78 spinlock_t lock;
79
80 struct list_head doorbells;
81};
82
83static inline struct tegra_hsp *
84to_tegra_hsp(struct mbox_controller *mbox)
85{
86 return container_of(mbox, struct tegra_hsp, mbox);
87}
88
89static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
90{
91 return readl(hsp->regs + offset);
92}
93
94static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
95 unsigned int offset)
96{
97 writel(value, hsp->regs + offset);
98}
99
100static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
101 unsigned int offset)
102{
103 return readl(channel->regs + offset);
104}
105
106static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
107 u32 value, unsigned int offset)
108{
109 writel(value, channel->regs + offset);
110}
111
112static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
113{
114 u32 value;
115
116 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
117
118 return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
119}
120
121static struct tegra_hsp_doorbell *
122__tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
123{
124 struct tegra_hsp_doorbell *entry;
125
126 list_for_each_entry(entry, &hsp->doorbells, list)
127 if (entry->master == master)
128 return entry;
129
130 return NULL;
131}
132
133static struct tegra_hsp_doorbell *
134tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
135{
136 struct tegra_hsp_doorbell *db;
137 unsigned long flags;
138
139 spin_lock_irqsave(&hsp->lock, flags);
140 db = __tegra_hsp_doorbell_get(hsp, master);
141 spin_unlock_irqrestore(&hsp->lock, flags);
142
143 return db;
144}
145
146static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
147{
148 struct tegra_hsp *hsp = data;
149 struct tegra_hsp_doorbell *db;
150 unsigned long master, value;
151
152 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
153 if (!db)
154 return IRQ_NONE;
155
156 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
157 tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
158
159 spin_lock(&hsp->lock);
160
161 for_each_set_bit(master, &value, hsp->mbox.num_chans) {
162 struct tegra_hsp_doorbell *db;
163
164 db = __tegra_hsp_doorbell_get(hsp, master);
165 /*
166 * Depending on the bootloader chain, the CCPLEX doorbell will
167 * have some doorbells enabled, which means that requesting an
168 * interrupt will immediately fire.
169 *
170 * In that case, db->channel.chan will still be NULL here and
171 * cause a crash if not properly guarded.
172 *
173 * It remains to be seen if ignoring the doorbell in that case
174 * is the correct solution.
175 */
176 if (db && db->channel.chan)
177 mbox_chan_received_data(db->channel.chan, NULL);
178 }
179
180 spin_unlock(&hsp->lock);
181
182 return IRQ_HANDLED;
183}
184
185static struct tegra_hsp_channel *
186tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
187 unsigned int master, unsigned int index)
188{
189 struct tegra_hsp_doorbell *db;
190 unsigned int offset;
191 unsigned long flags;
192
193 db = kzalloc(sizeof(*db), GFP_KERNEL);
194 if (!db)
195 return ERR_PTR(-ENOMEM);
196
197 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) << 16;
198 offset += index * 0x100;
199
200 db->channel.regs = hsp->regs + offset;
201 db->channel.hsp = hsp;
202
203 db->name = kstrdup_const(name, GFP_KERNEL);
204 db->master = master;
205 db->index = index;
206
207 spin_lock_irqsave(&hsp->lock, flags);
208 list_add_tail(&db->list, &hsp->doorbells);
209 spin_unlock_irqrestore(&hsp->lock, flags);
210
211 return &db->channel;
212}
213
214static void __tegra_hsp_doorbell_destroy(struct tegra_hsp_doorbell *db)
215{
216 list_del(&db->list);
217 kfree_const(db->name);
218 kfree(db);
219}
220
221static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
222{
223 struct tegra_hsp_doorbell *db = chan->con_priv;
224
225 tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
226
227 return 0;
228}
229
230static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
231{
232 struct tegra_hsp_doorbell *db = chan->con_priv;
233 struct tegra_hsp *hsp = db->channel.hsp;
234 struct tegra_hsp_doorbell *ccplex;
235 unsigned long flags;
236 u32 value;
237
238 if (db->master >= hsp->mbox.num_chans) {
239 dev_err(hsp->mbox.dev,
240 "invalid master ID %u for HSP channel\n",
241 db->master);
242 return -EINVAL;
243 }
244
245 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
246 if (!ccplex)
247 return -ENODEV;
248
249 if (!tegra_hsp_doorbell_can_ring(db))
250 return -ENODEV;
251
252 spin_lock_irqsave(&hsp->lock, flags);
253
254 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
255 value |= BIT(db->master);
256 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
257
258 spin_unlock_irqrestore(&hsp->lock, flags);
259
260 return 0;
261}
262
263static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
264{
265 struct tegra_hsp_doorbell *db = chan->con_priv;
266 struct tegra_hsp *hsp = db->channel.hsp;
267 struct tegra_hsp_doorbell *ccplex;
268 unsigned long flags;
269 u32 value;
270
271 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
272 if (!ccplex)
273 return;
274
275 spin_lock_irqsave(&hsp->lock, flags);
276
277 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
278 value &= ~BIT(db->master);
279 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
280
281 spin_unlock_irqrestore(&hsp->lock, flags);
282}
283
284static const struct mbox_chan_ops tegra_hsp_doorbell_ops = {
285 .send_data = tegra_hsp_doorbell_send_data,
286 .startup = tegra_hsp_doorbell_startup,
287 .shutdown = tegra_hsp_doorbell_shutdown,
288};
289
290static struct mbox_chan *of_tegra_hsp_xlate(struct mbox_controller *mbox,
291 const struct of_phandle_args *args)
292{
293 struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
294 struct tegra_hsp *hsp = to_tegra_hsp(mbox);
295 unsigned int type = args->args[0];
296 unsigned int master = args->args[1];
297 struct tegra_hsp_doorbell *db;
298 struct mbox_chan *chan;
299 unsigned long flags;
300 unsigned int i;
301
302 switch (type) {
303 case TEGRA_HSP_MBOX_TYPE_DB:
304 db = tegra_hsp_doorbell_get(hsp, master);
305 if (db)
306 channel = &db->channel;
307
308 break;
309
310 default:
311 break;
312 }
313
314 if (IS_ERR(channel))
315 return ERR_CAST(channel);
316
317 spin_lock_irqsave(&hsp->lock, flags);
318
319 for (i = 0; i < hsp->mbox.num_chans; i++) {
320 chan = &hsp->mbox.chans[i];
321 if (!chan->con_priv) {
322 chan->con_priv = channel;
323 channel->chan = chan;
324 break;
325 }
326
327 chan = NULL;
328 }
329
330 spin_unlock_irqrestore(&hsp->lock, flags);
331
332 return chan ?: ERR_PTR(-EBUSY);
333}
334
335static void tegra_hsp_remove_doorbells(struct tegra_hsp *hsp)
336{
337 struct tegra_hsp_doorbell *db, *tmp;
338 unsigned long flags;
339
340 spin_lock_irqsave(&hsp->lock, flags);
341
342 list_for_each_entry_safe(db, tmp, &hsp->doorbells, list)
343 __tegra_hsp_doorbell_destroy(db);
344
345 spin_unlock_irqrestore(&hsp->lock, flags);
346}
347
348static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
349{
350 const struct tegra_hsp_db_map *map = hsp->soc->map;
351 struct tegra_hsp_channel *channel;
352
353 while (map->name) {
354 channel = tegra_hsp_doorbell_create(hsp, map->name,
355 map->master, map->index);
356 if (IS_ERR(channel)) {
357 tegra_hsp_remove_doorbells(hsp);
358 return PTR_ERR(channel);
359 }
360
361 map++;
362 }
363
364 return 0;
365}
366
367static int tegra_hsp_probe(struct platform_device *pdev)
368{
369 struct tegra_hsp *hsp;
370 struct resource *res;
371 u32 value;
372 int err;
373
374 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
375 if (!hsp)
376 return -ENOMEM;
377
378 hsp->soc = of_device_get_match_data(&pdev->dev);
379 INIT_LIST_HEAD(&hsp->doorbells);
380 spin_lock_init(&hsp->lock);
381
382 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
383 hsp->regs = devm_ioremap_resource(&pdev->dev, res);
384 if (IS_ERR(hsp->regs))
385 return PTR_ERR(hsp->regs);
386
387 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
388 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
389 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
390 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
391 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
392 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
393
394 err = platform_get_irq_byname(pdev, "doorbell");
395 if (err < 0) {
396 dev_err(&pdev->dev, "failed to get doorbell IRQ: %d\n", err);
397 return err;
398 }
399
400 hsp->irq = err;
401
402 hsp->mbox.of_xlate = of_tegra_hsp_xlate;
403 hsp->mbox.num_chans = 32;
404 hsp->mbox.dev = &pdev->dev;
405 hsp->mbox.txdone_irq = false;
406 hsp->mbox.txdone_poll = false;
407 hsp->mbox.ops = &tegra_hsp_doorbell_ops;
408
409 hsp->mbox.chans = devm_kcalloc(&pdev->dev, hsp->mbox.num_chans,
410 sizeof(*hsp->mbox.chans),
411 GFP_KERNEL);
412 if (!hsp->mbox.chans)
413 return -ENOMEM;
414
415 err = tegra_hsp_add_doorbells(hsp);
416 if (err < 0) {
417 dev_err(&pdev->dev, "failed to add doorbells: %d\n", err);
418 return err;
419 }
420
421 platform_set_drvdata(pdev, hsp);
422
423 err = mbox_controller_register(&hsp->mbox);
424 if (err) {
425 dev_err(&pdev->dev, "failed to register mailbox: %d\n", err);
426 tegra_hsp_remove_doorbells(hsp);
427 return err;
428 }
429
430 err = devm_request_irq(&pdev->dev, hsp->irq, tegra_hsp_doorbell_irq,
431 IRQF_NO_SUSPEND, dev_name(&pdev->dev), hsp);
432 if (err < 0) {
433 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
434 hsp->irq, err);
435 return err;
436 }
437
438 return 0;
439}
440
441static int tegra_hsp_remove(struct platform_device *pdev)
442{
443 struct tegra_hsp *hsp = platform_get_drvdata(pdev);
444
445 mbox_controller_unregister(&hsp->mbox);
446 tegra_hsp_remove_doorbells(hsp);
447
448 return 0;
449}
450
451static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
452 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
453 { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, },
454 { /* sentinel */ }
455};
456
457static const struct tegra_hsp_soc tegra186_hsp_soc = {
458 .map = tegra186_hsp_db_map,
459};
460
461static const struct of_device_id tegra_hsp_match[] = {
462 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
463 { }
464};
465
466static struct platform_driver tegra_hsp_driver = {
467 .driver = {
468 .name = "tegra-hsp",
469 .of_match_table = tegra_hsp_match,
470 },
471 .probe = tegra_hsp_probe,
472 .remove = tegra_hsp_remove,
473};
474
475static int __init tegra_hsp_init(void)
476{
477 return platform_driver_register(&tegra_hsp_driver);
478}
479core_initcall(tegra_hsp_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
4 */
5
6#include <linux/delay.h>
7#include <linux/interrupt.h>
8#include <linux/io.h>
9#include <linux/mailbox_controller.h>
10#include <linux/of.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13#include <linux/pm.h>
14#include <linux/slab.h>
15
16#include <soc/tegra/fuse.h>
17
18#include <dt-bindings/mailbox/tegra186-hsp.h>
19
20#include "mailbox.h"
21
22#define HSP_INT_IE(x) (0x100 + ((x) * 4))
23#define HSP_INT_IV 0x300
24#define HSP_INT_IR 0x304
25
26#define HSP_INT_EMPTY_SHIFT 0
27#define HSP_INT_EMPTY_MASK 0xff
28#define HSP_INT_FULL_SHIFT 8
29#define HSP_INT_FULL_MASK 0xff
30
31#define HSP_INT_DIMENSIONING 0x380
32#define HSP_nSM_SHIFT 0
33#define HSP_nSS_SHIFT 4
34#define HSP_nAS_SHIFT 8
35#define HSP_nDB_SHIFT 12
36#define HSP_nSI_SHIFT 16
37#define HSP_nINT_MASK 0xf
38
39#define HSP_DB_TRIGGER 0x0
40#define HSP_DB_ENABLE 0x4
41#define HSP_DB_RAW 0x8
42#define HSP_DB_PENDING 0xc
43
44#define HSP_SM_SHRD_MBOX 0x0
45#define HSP_SM_SHRD_MBOX_FULL BIT(31)
46#define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04
47#define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08
48
49#define HSP_DB_CCPLEX 1
50#define HSP_DB_BPMP 3
51#define HSP_DB_MAX 7
52
53struct tegra_hsp_channel;
54struct tegra_hsp;
55
56struct tegra_hsp_channel {
57 struct tegra_hsp *hsp;
58 struct mbox_chan *chan;
59 void __iomem *regs;
60};
61
62struct tegra_hsp_doorbell {
63 struct tegra_hsp_channel channel;
64 struct list_head list;
65 const char *name;
66 unsigned int master;
67 unsigned int index;
68};
69
70struct tegra_hsp_mailbox {
71 struct tegra_hsp_channel channel;
72 unsigned int index;
73 bool producer;
74};
75
76struct tegra_hsp_db_map {
77 const char *name;
78 unsigned int master;
79 unsigned int index;
80};
81
82struct tegra_hsp_soc {
83 const struct tegra_hsp_db_map *map;
84 bool has_per_mb_ie;
85};
86
87struct tegra_hsp {
88 struct device *dev;
89 const struct tegra_hsp_soc *soc;
90 struct mbox_controller mbox_db;
91 struct mbox_controller mbox_sm;
92 void __iomem *regs;
93 unsigned int doorbell_irq;
94 unsigned int *shared_irqs;
95 unsigned int shared_irq;
96 unsigned int num_sm;
97 unsigned int num_as;
98 unsigned int num_ss;
99 unsigned int num_db;
100 unsigned int num_si;
101
102 spinlock_t lock;
103 struct lock_class_key lock_key;
104
105 struct list_head doorbells;
106 struct tegra_hsp_mailbox *mailboxes;
107
108 unsigned long mask;
109};
110
111static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
112{
113 return readl(hsp->regs + offset);
114}
115
116static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
117 unsigned int offset)
118{
119 writel(value, hsp->regs + offset);
120}
121
122static inline u32 tegra_hsp_channel_readl(struct tegra_hsp_channel *channel,
123 unsigned int offset)
124{
125 return readl(channel->regs + offset);
126}
127
128static inline void tegra_hsp_channel_writel(struct tegra_hsp_channel *channel,
129 u32 value, unsigned int offset)
130{
131 writel(value, channel->regs + offset);
132}
133
134static bool tegra_hsp_doorbell_can_ring(struct tegra_hsp_doorbell *db)
135{
136 u32 value;
137
138 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_ENABLE);
139
140 return (value & BIT(TEGRA_HSP_DB_MASTER_CCPLEX)) != 0;
141}
142
143static struct tegra_hsp_doorbell *
144__tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
145{
146 struct tegra_hsp_doorbell *entry;
147
148 list_for_each_entry(entry, &hsp->doorbells, list)
149 if (entry->master == master)
150 return entry;
151
152 return NULL;
153}
154
155static struct tegra_hsp_doorbell *
156tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
157{
158 struct tegra_hsp_doorbell *db;
159 unsigned long flags;
160
161 spin_lock_irqsave(&hsp->lock, flags);
162 db = __tegra_hsp_doorbell_get(hsp, master);
163 spin_unlock_irqrestore(&hsp->lock, flags);
164
165 return db;
166}
167
168static irqreturn_t tegra_hsp_doorbell_irq(int irq, void *data)
169{
170 struct tegra_hsp *hsp = data;
171 struct tegra_hsp_doorbell *db;
172 unsigned long master, value;
173
174 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
175 if (!db)
176 return IRQ_NONE;
177
178 value = tegra_hsp_channel_readl(&db->channel, HSP_DB_PENDING);
179 tegra_hsp_channel_writel(&db->channel, value, HSP_DB_PENDING);
180
181 spin_lock(&hsp->lock);
182
183 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
184 struct tegra_hsp_doorbell *db;
185
186 db = __tegra_hsp_doorbell_get(hsp, master);
187 /*
188 * Depending on the bootloader chain, the CCPLEX doorbell will
189 * have some doorbells enabled, which means that requesting an
190 * interrupt will immediately fire.
191 *
192 * In that case, db->channel.chan will still be NULL here and
193 * cause a crash if not properly guarded.
194 *
195 * It remains to be seen if ignoring the doorbell in that case
196 * is the correct solution.
197 */
198 if (db && db->channel.chan)
199 mbox_chan_received_data(db->channel.chan, NULL);
200 }
201
202 spin_unlock(&hsp->lock);
203
204 return IRQ_HANDLED;
205}
206
207static irqreturn_t tegra_hsp_shared_irq(int irq, void *data)
208{
209 struct tegra_hsp *hsp = data;
210 unsigned long bit, mask;
211 u32 status, value;
212 void *msg;
213
214 status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
215
216 /* process EMPTY interrupts first */
217 mask = (status >> HSP_INT_EMPTY_SHIFT) & HSP_INT_EMPTY_MASK;
218
219 for_each_set_bit(bit, &mask, hsp->num_sm) {
220 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
221
222 if (mb->producer) {
223 /*
224 * Disable EMPTY interrupts until data is sent with
225 * the next message. These interrupts are level-
226 * triggered, so if we kept them enabled they would
227 * constantly trigger until we next write data into
228 * the message.
229 */
230 spin_lock(&hsp->lock);
231
232 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
233 tegra_hsp_writel(hsp, hsp->mask,
234 HSP_INT_IE(hsp->shared_irq));
235
236 spin_unlock(&hsp->lock);
237
238 mbox_chan_txdone(mb->channel.chan, 0);
239 }
240 }
241
242 /* process FULL interrupts */
243 mask = (status >> HSP_INT_FULL_SHIFT) & HSP_INT_FULL_MASK;
244
245 for_each_set_bit(bit, &mask, hsp->num_sm) {
246 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
247
248 if (!mb->producer) {
249 value = tegra_hsp_channel_readl(&mb->channel,
250 HSP_SM_SHRD_MBOX);
251 value &= ~HSP_SM_SHRD_MBOX_FULL;
252 msg = (void *)(unsigned long)value;
253 mbox_chan_received_data(mb->channel.chan, msg);
254
255 /*
256 * Need to clear all bits here since some producers,
257 * such as TCU, depend on fields in the register
258 * getting cleared by the consumer.
259 *
260 * The mailbox API doesn't give the consumers a way
261 * of doing that explicitly, so we have to make sure
262 * we cover all possible cases.
263 */
264 tegra_hsp_channel_writel(&mb->channel, 0x0,
265 HSP_SM_SHRD_MBOX);
266 }
267 }
268
269 return IRQ_HANDLED;
270}
271
272static struct tegra_hsp_channel *
273tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
274 unsigned int master, unsigned int index)
275{
276 struct tegra_hsp_doorbell *db;
277 unsigned int offset;
278 unsigned long flags;
279
280 db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
281 if (!db)
282 return ERR_PTR(-ENOMEM);
283
284 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
285 offset += index * 0x100;
286
287 db->channel.regs = hsp->regs + offset;
288 db->channel.hsp = hsp;
289
290 db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
291 db->master = master;
292 db->index = index;
293
294 spin_lock_irqsave(&hsp->lock, flags);
295 list_add_tail(&db->list, &hsp->doorbells);
296 spin_unlock_irqrestore(&hsp->lock, flags);
297
298 return &db->channel;
299}
300
301static int tegra_hsp_doorbell_send_data(struct mbox_chan *chan, void *data)
302{
303 struct tegra_hsp_doorbell *db = chan->con_priv;
304
305 tegra_hsp_channel_writel(&db->channel, 1, HSP_DB_TRIGGER);
306
307 return 0;
308}
309
310static int tegra_hsp_doorbell_startup(struct mbox_chan *chan)
311{
312 struct tegra_hsp_doorbell *db = chan->con_priv;
313 struct tegra_hsp *hsp = db->channel.hsp;
314 struct tegra_hsp_doorbell *ccplex;
315 unsigned long flags;
316 u32 value;
317
318 if (db->master >= chan->mbox->num_chans) {
319 dev_err(chan->mbox->dev,
320 "invalid master ID %u for HSP channel\n",
321 db->master);
322 return -EINVAL;
323 }
324
325 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
326 if (!ccplex)
327 return -ENODEV;
328
329 /*
330 * On simulation platforms the BPMP hasn't had a chance yet to mark
331 * the doorbell as ringable by the CCPLEX, so we want to skip extra
332 * checks here.
333 */
334 if (tegra_is_silicon() && !tegra_hsp_doorbell_can_ring(db))
335 return -ENODEV;
336
337 spin_lock_irqsave(&hsp->lock, flags);
338
339 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
340 value |= BIT(db->master);
341 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
342
343 spin_unlock_irqrestore(&hsp->lock, flags);
344
345 return 0;
346}
347
348static void tegra_hsp_doorbell_shutdown(struct mbox_chan *chan)
349{
350 struct tegra_hsp_doorbell *db = chan->con_priv;
351 struct tegra_hsp *hsp = db->channel.hsp;
352 struct tegra_hsp_doorbell *ccplex;
353 unsigned long flags;
354 u32 value;
355
356 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
357 if (!ccplex)
358 return;
359
360 spin_lock_irqsave(&hsp->lock, flags);
361
362 value = tegra_hsp_channel_readl(&ccplex->channel, HSP_DB_ENABLE);
363 value &= ~BIT(db->master);
364 tegra_hsp_channel_writel(&ccplex->channel, value, HSP_DB_ENABLE);
365
366 spin_unlock_irqrestore(&hsp->lock, flags);
367}
368
369static const struct mbox_chan_ops tegra_hsp_db_ops = {
370 .send_data = tegra_hsp_doorbell_send_data,
371 .startup = tegra_hsp_doorbell_startup,
372 .shutdown = tegra_hsp_doorbell_shutdown,
373};
374
375static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data)
376{
377 struct tegra_hsp_mailbox *mb = chan->con_priv;
378 struct tegra_hsp *hsp = mb->channel.hsp;
379 unsigned long flags;
380 u32 value;
381
382 if (WARN_ON(!mb->producer))
383 return -EPERM;
384
385 /* copy data and mark mailbox full */
386 value = (u32)(unsigned long)data;
387 value |= HSP_SM_SHRD_MBOX_FULL;
388
389 tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX);
390
391 /* enable EMPTY interrupt for the shared mailbox */
392 spin_lock_irqsave(&hsp->lock, flags);
393
394 hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
395 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
396
397 spin_unlock_irqrestore(&hsp->lock, flags);
398
399 return 0;
400}
401
402static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
403 unsigned long timeout)
404{
405 struct tegra_hsp_mailbox *mb = chan->con_priv;
406 struct tegra_hsp_channel *ch = &mb->channel;
407 u32 value;
408
409 timeout = jiffies + msecs_to_jiffies(timeout);
410
411 while (time_before(jiffies, timeout)) {
412 value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX);
413 if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) {
414 mbox_chan_txdone(chan, 0);
415 return 0;
416 }
417
418 udelay(1);
419 }
420
421 return -ETIME;
422}
423
424static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
425{
426 struct tegra_hsp_mailbox *mb = chan->con_priv;
427 struct tegra_hsp_channel *ch = &mb->channel;
428 struct tegra_hsp *hsp = mb->channel.hsp;
429 unsigned long flags;
430
431 chan->txdone_method = TXDONE_BY_IRQ;
432
433 /*
434 * Shared mailboxes start out as consumers by default. FULL and EMPTY
435 * interrupts are coalesced at the same shared interrupt.
436 *
437 * Keep EMPTY interrupts disabled at startup and only enable them when
438 * the mailbox is actually full. This is required because the FULL and
439 * EMPTY interrupts are level-triggered, so keeping EMPTY interrupts
440 * enabled all the time would cause an interrupt storm while mailboxes
441 * are idle.
442 */
443
444 spin_lock_irqsave(&hsp->lock, flags);
445
446 if (mb->producer)
447 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
448 else
449 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
450
451 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
452
453 spin_unlock_irqrestore(&hsp->lock, flags);
454
455 if (hsp->soc->has_per_mb_ie) {
456 if (mb->producer)
457 tegra_hsp_channel_writel(ch, 0x0,
458 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
459 else
460 tegra_hsp_channel_writel(ch, 0x1,
461 HSP_SM_SHRD_MBOX_FULL_INT_IE);
462 }
463
464 return 0;
465}
466
467static void tegra_hsp_mailbox_shutdown(struct mbox_chan *chan)
468{
469 struct tegra_hsp_mailbox *mb = chan->con_priv;
470 struct tegra_hsp_channel *ch = &mb->channel;
471 struct tegra_hsp *hsp = mb->channel.hsp;
472 unsigned long flags;
473
474 if (hsp->soc->has_per_mb_ie) {
475 if (mb->producer)
476 tegra_hsp_channel_writel(ch, 0x0,
477 HSP_SM_SHRD_MBOX_EMPTY_INT_IE);
478 else
479 tegra_hsp_channel_writel(ch, 0x0,
480 HSP_SM_SHRD_MBOX_FULL_INT_IE);
481 }
482
483 spin_lock_irqsave(&hsp->lock, flags);
484
485 if (mb->producer)
486 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
487 else
488 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
489
490 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
491
492 spin_unlock_irqrestore(&hsp->lock, flags);
493}
494
495static const struct mbox_chan_ops tegra_hsp_sm_ops = {
496 .send_data = tegra_hsp_mailbox_send_data,
497 .flush = tegra_hsp_mailbox_flush,
498 .startup = tegra_hsp_mailbox_startup,
499 .shutdown = tegra_hsp_mailbox_shutdown,
500};
501
502static struct mbox_chan *tegra_hsp_db_xlate(struct mbox_controller *mbox,
503 const struct of_phandle_args *args)
504{
505 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
506 unsigned int type = args->args[0], master = args->args[1];
507 struct tegra_hsp_channel *channel = ERR_PTR(-ENODEV);
508 struct tegra_hsp_doorbell *db;
509 struct mbox_chan *chan;
510 unsigned long flags;
511 unsigned int i;
512
513 if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
514 return ERR_PTR(-ENODEV);
515
516 db = tegra_hsp_doorbell_get(hsp, master);
517 if (db)
518 channel = &db->channel;
519
520 if (IS_ERR(channel))
521 return ERR_CAST(channel);
522
523 spin_lock_irqsave(&hsp->lock, flags);
524
525 for (i = 0; i < mbox->num_chans; i++) {
526 chan = &mbox->chans[i];
527 if (!chan->con_priv) {
528 channel->chan = chan;
529 chan->con_priv = db;
530 break;
531 }
532
533 chan = NULL;
534 }
535
536 spin_unlock_irqrestore(&hsp->lock, flags);
537
538 return chan ?: ERR_PTR(-EBUSY);
539}
540
541static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox_controller *mbox,
542 const struct of_phandle_args *args)
543{
544 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
545 unsigned int type = args->args[0], index;
546 struct tegra_hsp_mailbox *mb;
547
548 index = args->args[1] & TEGRA_HSP_SM_MASK;
549
550 if (type != TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs ||
551 index >= hsp->num_sm)
552 return ERR_PTR(-ENODEV);
553
554 mb = &hsp->mailboxes[index];
555
556 if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) == 0)
557 mb->producer = false;
558 else
559 mb->producer = true;
560
561 return mb->channel.chan;
562}
563
564static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
565{
566 const struct tegra_hsp_db_map *map = hsp->soc->map;
567 struct tegra_hsp_channel *channel;
568
569 while (map->name) {
570 channel = tegra_hsp_doorbell_create(hsp, map->name,
571 map->master, map->index);
572 if (IS_ERR(channel))
573 return PTR_ERR(channel);
574
575 map++;
576 }
577
578 return 0;
579}
580
581static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
582{
583 int i;
584
585 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
586 GFP_KERNEL);
587 if (!hsp->mailboxes)
588 return -ENOMEM;
589
590 for (i = 0; i < hsp->num_sm; i++) {
591 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
592
593 mb->index = i;
594
595 mb->channel.hsp = hsp;
596 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
597 mb->channel.chan = &hsp->mbox_sm.chans[i];
598 mb->channel.chan->con_priv = mb;
599 }
600
601 return 0;
602}
603
604static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
605{
606 unsigned int i, irq = 0;
607 int err;
608
609 for (i = 0; i < hsp->num_si; i++) {
610 irq = hsp->shared_irqs[i];
611 if (irq <= 0)
612 continue;
613
614 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
615 dev_name(hsp->dev), hsp);
616 if (err < 0) {
617 dev_err(hsp->dev, "failed to request interrupt: %d\n",
618 err);
619 continue;
620 }
621
622 hsp->shared_irq = i;
623
624 /* disable all interrupts */
625 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
626
627 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
628
629 break;
630 }
631
632 if (i == hsp->num_si) {
633 dev_err(hsp->dev, "failed to find available interrupt\n");
634 return -ENOENT;
635 }
636
637 return 0;
638}
639
640static int tegra_hsp_probe(struct platform_device *pdev)
641{
642 struct tegra_hsp *hsp;
643 struct resource *res;
644 unsigned int i;
645 u32 value;
646 int err;
647
648 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
649 if (!hsp)
650 return -ENOMEM;
651
652 hsp->dev = &pdev->dev;
653 hsp->soc = of_device_get_match_data(&pdev->dev);
654 INIT_LIST_HEAD(&hsp->doorbells);
655 spin_lock_init(&hsp->lock);
656
657 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
658 hsp->regs = devm_ioremap_resource(&pdev->dev, res);
659 if (IS_ERR(hsp->regs))
660 return PTR_ERR(hsp->regs);
661
662 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
663 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
664 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
665 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
666 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
667 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
668
669 err = platform_get_irq_byname_optional(pdev, "doorbell");
670 if (err >= 0)
671 hsp->doorbell_irq = err;
672
673 if (hsp->num_si > 0) {
674 unsigned int count = 0;
675
676 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
677 sizeof(*hsp->shared_irqs),
678 GFP_KERNEL);
679 if (!hsp->shared_irqs)
680 return -ENOMEM;
681
682 for (i = 0; i < hsp->num_si; i++) {
683 char *name;
684
685 name = kasprintf(GFP_KERNEL, "shared%u", i);
686 if (!name)
687 return -ENOMEM;
688
689 err = platform_get_irq_byname_optional(pdev, name);
690 if (err >= 0) {
691 hsp->shared_irqs[i] = err;
692 count++;
693 }
694
695 kfree(name);
696 }
697
698 if (count == 0) {
699 devm_kfree(&pdev->dev, hsp->shared_irqs);
700 hsp->shared_irqs = NULL;
701 }
702 }
703
704 /* setup the doorbell controller */
705 hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
706 hsp->mbox_db.num_chans = 32;
707 hsp->mbox_db.dev = &pdev->dev;
708 hsp->mbox_db.ops = &tegra_hsp_db_ops;
709
710 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
711 sizeof(*hsp->mbox_db.chans),
712 GFP_KERNEL);
713 if (!hsp->mbox_db.chans)
714 return -ENOMEM;
715
716 if (hsp->doorbell_irq) {
717 err = tegra_hsp_add_doorbells(hsp);
718 if (err < 0) {
719 dev_err(&pdev->dev, "failed to add doorbells: %d\n",
720 err);
721 return err;
722 }
723 }
724
725 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
726 if (err < 0) {
727 dev_err(&pdev->dev, "failed to register doorbell mailbox: %d\n",
728 err);
729 return err;
730 }
731
732 /* setup the shared mailbox controller */
733 hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
734 hsp->mbox_sm.num_chans = hsp->num_sm;
735 hsp->mbox_sm.dev = &pdev->dev;
736 hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
737
738 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
739 sizeof(*hsp->mbox_sm.chans),
740 GFP_KERNEL);
741 if (!hsp->mbox_sm.chans)
742 return -ENOMEM;
743
744 if (hsp->shared_irqs) {
745 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
746 if (err < 0) {
747 dev_err(&pdev->dev, "failed to add mailboxes: %d\n",
748 err);
749 return err;
750 }
751 }
752
753 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
754 if (err < 0) {
755 dev_err(&pdev->dev, "failed to register shared mailbox: %d\n",
756 err);
757 return err;
758 }
759
760 platform_set_drvdata(pdev, hsp);
761
762 if (hsp->doorbell_irq) {
763 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
764 tegra_hsp_doorbell_irq, IRQF_NO_SUSPEND,
765 dev_name(&pdev->dev), hsp);
766 if (err < 0) {
767 dev_err(&pdev->dev,
768 "failed to request doorbell IRQ#%u: %d\n",
769 hsp->doorbell_irq, err);
770 return err;
771 }
772 }
773
774 if (hsp->shared_irqs) {
775 err = tegra_hsp_request_shared_irq(hsp);
776 if (err < 0)
777 return err;
778 }
779
780 lockdep_register_key(&hsp->lock_key);
781 lockdep_set_class(&hsp->lock, &hsp->lock_key);
782
783 return 0;
784}
785
786static int tegra_hsp_remove(struct platform_device *pdev)
787{
788 struct tegra_hsp *hsp = platform_get_drvdata(pdev);
789
790 lockdep_unregister_key(&hsp->lock_key);
791
792 return 0;
793}
794
795static int __maybe_unused tegra_hsp_resume(struct device *dev)
796{
797 struct tegra_hsp *hsp = dev_get_drvdata(dev);
798 unsigned int i;
799 struct tegra_hsp_doorbell *db;
800
801 list_for_each_entry(db, &hsp->doorbells, list) {
802 if (db && db->channel.chan)
803 tegra_hsp_doorbell_startup(db->channel.chan);
804 }
805
806 if (hsp->mailboxes) {
807 for (i = 0; i < hsp->num_sm; i++) {
808 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
809
810 if (mb->channel.chan->cl)
811 tegra_hsp_mailbox_startup(mb->channel.chan);
812 }
813 }
814
815 return 0;
816}
817
818static const struct dev_pm_ops tegra_hsp_pm_ops = {
819 .resume_noirq = tegra_hsp_resume,
820};
821
822static const struct tegra_hsp_db_map tegra186_hsp_db_map[] = {
823 { "ccplex", TEGRA_HSP_DB_MASTER_CCPLEX, HSP_DB_CCPLEX, },
824 { "bpmp", TEGRA_HSP_DB_MASTER_BPMP, HSP_DB_BPMP, },
825 { /* sentinel */ }
826};
827
828static const struct tegra_hsp_soc tegra186_hsp_soc = {
829 .map = tegra186_hsp_db_map,
830 .has_per_mb_ie = false,
831};
832
833static const struct tegra_hsp_soc tegra194_hsp_soc = {
834 .map = tegra186_hsp_db_map,
835 .has_per_mb_ie = true,
836};
837
838static const struct of_device_id tegra_hsp_match[] = {
839 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
840 { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
841 { }
842};
843
844static struct platform_driver tegra_hsp_driver = {
845 .driver = {
846 .name = "tegra-hsp",
847 .of_match_table = tegra_hsp_match,
848 .pm = &tegra_hsp_pm_ops,
849 },
850 .probe = tegra_hsp_probe,
851 .remove = tegra_hsp_remove,
852};
853
854static int __init tegra_hsp_init(void)
855{
856 return platform_driver_register(&tegra_hsp_driver);
857}
858core_initcall(tegra_hsp_init);