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1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Authors:
6 * Dave Airlie
7 * Alon Levy
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 */
27
28#include <drm/drmP.h>
29#include <drm/virtgpu_drm.h>
30#include <drm/ttm/ttm_execbuf_util.h>
31
32#include "virtgpu_drv.h"
33
34static void convert_to_hw_box(struct virtio_gpu_box *dst,
35 const struct drm_virtgpu_3d_box *src)
36{
37 dst->x = cpu_to_le32(src->x);
38 dst->y = cpu_to_le32(src->y);
39 dst->z = cpu_to_le32(src->z);
40 dst->w = cpu_to_le32(src->w);
41 dst->h = cpu_to_le32(src->h);
42 dst->d = cpu_to_le32(src->d);
43}
44
45static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
46 struct drm_file *file_priv)
47{
48 struct virtio_gpu_device *vgdev = dev->dev_private;
49 struct drm_virtgpu_map *virtio_gpu_map = data;
50
51 return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev,
52 virtio_gpu_map->handle,
53 &virtio_gpu_map->offset);
54}
55
56static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket,
57 struct list_head *head)
58{
59 struct ttm_operation_ctx ctx = { false, false };
60 struct ttm_validate_buffer *buf;
61 struct ttm_buffer_object *bo;
62 struct virtio_gpu_object *qobj;
63 int ret;
64
65 ret = ttm_eu_reserve_buffers(ticket, head, true, NULL);
66 if (ret != 0)
67 return ret;
68
69 list_for_each_entry(buf, head, head) {
70 bo = buf->bo;
71 qobj = container_of(bo, struct virtio_gpu_object, tbo);
72 ret = ttm_bo_validate(bo, &qobj->placement, &ctx);
73 if (ret) {
74 ttm_eu_backoff_reservation(ticket, head);
75 return ret;
76 }
77 }
78 return 0;
79}
80
81static void virtio_gpu_unref_list(struct list_head *head)
82{
83 struct ttm_validate_buffer *buf;
84 struct ttm_buffer_object *bo;
85 struct virtio_gpu_object *qobj;
86
87 list_for_each_entry(buf, head, head) {
88 bo = buf->bo;
89 qobj = container_of(bo, struct virtio_gpu_object, tbo);
90
91 drm_gem_object_put_unlocked(&qobj->gem_base);
92 }
93}
94
95/*
96 * Usage of execbuffer:
97 * Relocations need to take into account the full VIRTIO_GPUDrawable size.
98 * However, the command as passed from user space must *not* contain the initial
99 * VIRTIO_GPUReleaseInfo struct (first XXX bytes)
100 */
101static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
102 struct drm_file *drm_file)
103{
104 struct drm_virtgpu_execbuffer *exbuf = data;
105 struct virtio_gpu_device *vgdev = dev->dev_private;
106 struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv;
107 struct drm_gem_object *gobj;
108 struct virtio_gpu_fence *fence;
109 struct virtio_gpu_object *qobj;
110 int ret;
111 uint32_t *bo_handles = NULL;
112 void __user *user_bo_handles = NULL;
113 struct list_head validate_list;
114 struct ttm_validate_buffer *buflist = NULL;
115 int i;
116 struct ww_acquire_ctx ticket;
117 void *buf;
118
119 if (vgdev->has_virgl_3d == false)
120 return -ENOSYS;
121
122 INIT_LIST_HEAD(&validate_list);
123 if (exbuf->num_bo_handles) {
124
125 bo_handles = kvmalloc_array(exbuf->num_bo_handles,
126 sizeof(uint32_t), GFP_KERNEL);
127 buflist = kvmalloc_array(exbuf->num_bo_handles,
128 sizeof(struct ttm_validate_buffer),
129 GFP_KERNEL | __GFP_ZERO);
130 if (!bo_handles || !buflist) {
131 kvfree(bo_handles);
132 kvfree(buflist);
133 return -ENOMEM;
134 }
135
136 user_bo_handles = (void __user *)(uintptr_t)exbuf->bo_handles;
137 if (copy_from_user(bo_handles, user_bo_handles,
138 exbuf->num_bo_handles * sizeof(uint32_t))) {
139 ret = -EFAULT;
140 kvfree(bo_handles);
141 kvfree(buflist);
142 return ret;
143 }
144
145 for (i = 0; i < exbuf->num_bo_handles; i++) {
146 gobj = drm_gem_object_lookup(drm_file, bo_handles[i]);
147 if (!gobj) {
148 kvfree(bo_handles);
149 kvfree(buflist);
150 return -ENOENT;
151 }
152
153 qobj = gem_to_virtio_gpu_obj(gobj);
154 buflist[i].bo = &qobj->tbo;
155
156 list_add(&buflist[i].head, &validate_list);
157 }
158 kvfree(bo_handles);
159 }
160
161 ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
162 if (ret)
163 goto out_free;
164
165 buf = memdup_user((void __user *)(uintptr_t)exbuf->command,
166 exbuf->size);
167 if (IS_ERR(buf)) {
168 ret = PTR_ERR(buf);
169 goto out_unresv;
170 }
171 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
172 vfpriv->ctx_id, &fence);
173
174 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f);
175
176 /* fence the command bo */
177 virtio_gpu_unref_list(&validate_list);
178 kvfree(buflist);
179 dma_fence_put(&fence->f);
180 return 0;
181
182out_unresv:
183 ttm_eu_backoff_reservation(&ticket, &validate_list);
184out_free:
185 virtio_gpu_unref_list(&validate_list);
186 kvfree(buflist);
187 return ret;
188}
189
190static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
191 struct drm_file *file_priv)
192{
193 struct virtio_gpu_device *vgdev = dev->dev_private;
194 struct drm_virtgpu_getparam *param = data;
195 int value;
196
197 switch (param->param) {
198 case VIRTGPU_PARAM_3D_FEATURES:
199 value = vgdev->has_virgl_3d == true ? 1 : 0;
200 break;
201 case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
202 value = 1;
203 break;
204 default:
205 return -EINVAL;
206 }
207 if (copy_to_user((void __user *)(unsigned long)param->value,
208 &value, sizeof(int))) {
209 return -EFAULT;
210 }
211 return 0;
212}
213
214static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
215 struct drm_file *file_priv)
216{
217 struct virtio_gpu_device *vgdev = dev->dev_private;
218 struct drm_virtgpu_resource_create *rc = data;
219 int ret;
220 uint32_t res_id;
221 struct virtio_gpu_object *qobj;
222 struct drm_gem_object *obj;
223 uint32_t handle = 0;
224 uint32_t size;
225 struct list_head validate_list;
226 struct ttm_validate_buffer mainbuf;
227 struct virtio_gpu_fence *fence = NULL;
228 struct ww_acquire_ctx ticket;
229 struct virtio_gpu_resource_create_3d rc_3d;
230
231 if (vgdev->has_virgl_3d == false) {
232 if (rc->depth > 1)
233 return -EINVAL;
234 if (rc->nr_samples > 1)
235 return -EINVAL;
236 if (rc->last_level > 1)
237 return -EINVAL;
238 if (rc->target != 2)
239 return -EINVAL;
240 if (rc->array_size > 1)
241 return -EINVAL;
242 }
243
244 INIT_LIST_HEAD(&validate_list);
245 memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer));
246
247 virtio_gpu_resource_id_get(vgdev, &res_id);
248
249 size = rc->size;
250
251 /* allocate a single page size object */
252 if (size == 0)
253 size = PAGE_SIZE;
254
255 qobj = virtio_gpu_alloc_object(dev, size, false, false);
256 if (IS_ERR(qobj)) {
257 ret = PTR_ERR(qobj);
258 goto fail_id;
259 }
260 obj = &qobj->gem_base;
261
262 if (!vgdev->has_virgl_3d) {
263 virtio_gpu_cmd_create_resource(vgdev, res_id, rc->format,
264 rc->width, rc->height);
265
266 ret = virtio_gpu_object_attach(vgdev, qobj, res_id, NULL);
267 } else {
268 /* use a gem reference since unref list undoes them */
269 drm_gem_object_get(&qobj->gem_base);
270 mainbuf.bo = &qobj->tbo;
271 list_add(&mainbuf.head, &validate_list);
272
273 ret = virtio_gpu_object_list_validate(&ticket, &validate_list);
274 if (ret) {
275 DRM_DEBUG("failed to validate\n");
276 goto fail_unref;
277 }
278
279 rc_3d.resource_id = cpu_to_le32(res_id);
280 rc_3d.target = cpu_to_le32(rc->target);
281 rc_3d.format = cpu_to_le32(rc->format);
282 rc_3d.bind = cpu_to_le32(rc->bind);
283 rc_3d.width = cpu_to_le32(rc->width);
284 rc_3d.height = cpu_to_le32(rc->height);
285 rc_3d.depth = cpu_to_le32(rc->depth);
286 rc_3d.array_size = cpu_to_le32(rc->array_size);
287 rc_3d.last_level = cpu_to_le32(rc->last_level);
288 rc_3d.nr_samples = cpu_to_le32(rc->nr_samples);
289 rc_3d.flags = cpu_to_le32(rc->flags);
290
291 virtio_gpu_cmd_resource_create_3d(vgdev, &rc_3d, NULL);
292 ret = virtio_gpu_object_attach(vgdev, qobj, res_id, &fence);
293 if (ret) {
294 ttm_eu_backoff_reservation(&ticket, &validate_list);
295 goto fail_unref;
296 }
297 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f);
298 }
299
300 qobj->hw_res_handle = res_id;
301
302 ret = drm_gem_handle_create(file_priv, obj, &handle);
303 if (ret) {
304
305 drm_gem_object_release(obj);
306 if (vgdev->has_virgl_3d) {
307 virtio_gpu_unref_list(&validate_list);
308 dma_fence_put(&fence->f);
309 }
310 return ret;
311 }
312 drm_gem_object_put_unlocked(obj);
313
314 rc->res_handle = res_id; /* similiar to a VM address */
315 rc->bo_handle = handle;
316
317 if (vgdev->has_virgl_3d) {
318 virtio_gpu_unref_list(&validate_list);
319 dma_fence_put(&fence->f);
320 }
321 return 0;
322fail_unref:
323 if (vgdev->has_virgl_3d) {
324 virtio_gpu_unref_list(&validate_list);
325 dma_fence_put(&fence->f);
326 }
327//fail_obj:
328// drm_gem_object_handle_unreference_unlocked(obj);
329fail_id:
330 virtio_gpu_resource_id_put(vgdev, res_id);
331 return ret;
332}
333
334static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
335 struct drm_file *file_priv)
336{
337 struct drm_virtgpu_resource_info *ri = data;
338 struct drm_gem_object *gobj = NULL;
339 struct virtio_gpu_object *qobj = NULL;
340
341 gobj = drm_gem_object_lookup(file_priv, ri->bo_handle);
342 if (gobj == NULL)
343 return -ENOENT;
344
345 qobj = gem_to_virtio_gpu_obj(gobj);
346
347 ri->size = qobj->gem_base.size;
348 ri->res_handle = qobj->hw_res_handle;
349 drm_gem_object_put_unlocked(gobj);
350 return 0;
351}
352
353static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
354 void *data,
355 struct drm_file *file)
356{
357 struct virtio_gpu_device *vgdev = dev->dev_private;
358 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
359 struct drm_virtgpu_3d_transfer_from_host *args = data;
360 struct ttm_operation_ctx ctx = { true, false };
361 struct drm_gem_object *gobj = NULL;
362 struct virtio_gpu_object *qobj = NULL;
363 struct virtio_gpu_fence *fence;
364 int ret;
365 u32 offset = args->offset;
366 struct virtio_gpu_box box;
367
368 if (vgdev->has_virgl_3d == false)
369 return -ENOSYS;
370
371 gobj = drm_gem_object_lookup(file, args->bo_handle);
372 if (gobj == NULL)
373 return -ENOENT;
374
375 qobj = gem_to_virtio_gpu_obj(gobj);
376
377 ret = virtio_gpu_object_reserve(qobj, false);
378 if (ret)
379 goto out;
380
381 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
382 if (unlikely(ret))
383 goto out_unres;
384
385 convert_to_hw_box(&box, &args->box);
386 virtio_gpu_cmd_transfer_from_host_3d
387 (vgdev, qobj->hw_res_handle,
388 vfpriv->ctx_id, offset, args->level,
389 &box, &fence);
390 reservation_object_add_excl_fence(qobj->tbo.resv,
391 &fence->f);
392
393 dma_fence_put(&fence->f);
394out_unres:
395 virtio_gpu_object_unreserve(qobj);
396out:
397 drm_gem_object_put_unlocked(gobj);
398 return ret;
399}
400
401static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
402 struct drm_file *file)
403{
404 struct virtio_gpu_device *vgdev = dev->dev_private;
405 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
406 struct drm_virtgpu_3d_transfer_to_host *args = data;
407 struct ttm_operation_ctx ctx = { true, false };
408 struct drm_gem_object *gobj = NULL;
409 struct virtio_gpu_object *qobj = NULL;
410 struct virtio_gpu_fence *fence;
411 struct virtio_gpu_box box;
412 int ret;
413 u32 offset = args->offset;
414
415 gobj = drm_gem_object_lookup(file, args->bo_handle);
416 if (gobj == NULL)
417 return -ENOENT;
418
419 qobj = gem_to_virtio_gpu_obj(gobj);
420
421 ret = virtio_gpu_object_reserve(qobj, false);
422 if (ret)
423 goto out;
424
425 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx);
426 if (unlikely(ret))
427 goto out_unres;
428
429 convert_to_hw_box(&box, &args->box);
430 if (!vgdev->has_virgl_3d) {
431 virtio_gpu_cmd_transfer_to_host_2d
432 (vgdev, qobj->hw_res_handle, offset,
433 box.w, box.h, box.x, box.y, NULL);
434 } else {
435 virtio_gpu_cmd_transfer_to_host_3d
436 (vgdev, qobj->hw_res_handle,
437 vfpriv ? vfpriv->ctx_id : 0, offset,
438 args->level, &box, &fence);
439 reservation_object_add_excl_fence(qobj->tbo.resv,
440 &fence->f);
441 dma_fence_put(&fence->f);
442 }
443
444out_unres:
445 virtio_gpu_object_unreserve(qobj);
446out:
447 drm_gem_object_put_unlocked(gobj);
448 return ret;
449}
450
451static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
452 struct drm_file *file)
453{
454 struct drm_virtgpu_3d_wait *args = data;
455 struct drm_gem_object *gobj = NULL;
456 struct virtio_gpu_object *qobj = NULL;
457 int ret;
458 bool nowait = false;
459
460 gobj = drm_gem_object_lookup(file, args->handle);
461 if (gobj == NULL)
462 return -ENOENT;
463
464 qobj = gem_to_virtio_gpu_obj(gobj);
465
466 if (args->flags & VIRTGPU_WAIT_NOWAIT)
467 nowait = true;
468 ret = virtio_gpu_object_wait(qobj, nowait);
469
470 drm_gem_object_put_unlocked(gobj);
471 return ret;
472}
473
474static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
475 void *data, struct drm_file *file)
476{
477 struct virtio_gpu_device *vgdev = dev->dev_private;
478 struct drm_virtgpu_get_caps *args = data;
479 unsigned size, host_caps_size;
480 int i;
481 int found_valid = -1;
482 int ret;
483 struct virtio_gpu_drv_cap_cache *cache_ent;
484 void *ptr;
485
486 if (vgdev->num_capsets == 0)
487 return -ENOSYS;
488
489 /* don't allow userspace to pass 0 */
490 if (args->size == 0)
491 return -EINVAL;
492
493 spin_lock(&vgdev->display_info_lock);
494 for (i = 0; i < vgdev->num_capsets; i++) {
495 if (vgdev->capsets[i].id == args->cap_set_id) {
496 if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
497 found_valid = i;
498 break;
499 }
500 }
501 }
502
503 if (found_valid == -1) {
504 spin_unlock(&vgdev->display_info_lock);
505 return -EINVAL;
506 }
507
508 host_caps_size = vgdev->capsets[found_valid].max_size;
509 /* only copy to user the minimum of the host caps size or the guest caps size */
510 size = min(args->size, host_caps_size);
511
512 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
513 if (cache_ent->id == args->cap_set_id &&
514 cache_ent->version == args->cap_set_ver) {
515 ptr = cache_ent->caps_cache;
516 spin_unlock(&vgdev->display_info_lock);
517 goto copy_exit;
518 }
519 }
520 spin_unlock(&vgdev->display_info_lock);
521
522 /* not in cache - need to talk to hw */
523 virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
524 &cache_ent);
525
526 ret = wait_event_timeout(vgdev->resp_wq,
527 atomic_read(&cache_ent->is_valid), 5 * HZ);
528 if (!ret)
529 return -EBUSY;
530
531 ptr = cache_ent->caps_cache;
532
533copy_exit:
534 if (copy_to_user((void __user *)(unsigned long)args->addr, ptr, size))
535 return -EFAULT;
536
537 return 0;
538}
539
540struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
541 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
542 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
543
544 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
545 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
546
547 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
548 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
549
550 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
551 virtio_gpu_resource_create_ioctl,
552 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
553
554 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
555 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
556
557 /* make transfer async to the main ring? - no sure, can we
558 * thread these in the underlying GL
559 */
560 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
561 virtio_gpu_transfer_from_host_ioctl,
562 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
563 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
564 virtio_gpu_transfer_to_host_ioctl,
565 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
566
567 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
568 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
569
570 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
571 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
572};
1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Authors:
6 * Dave Airlie
7 * Alon Levy
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 */
27
28#include <linux/file.h>
29#include <linux/sync_file.h>
30#include <linux/uaccess.h>
31
32#include <drm/drm_file.h>
33#include <drm/virtgpu_drm.h>
34
35#include "virtgpu_drv.h"
36
37#define VIRTGPU_BLOB_FLAG_USE_MASK (VIRTGPU_BLOB_FLAG_USE_MAPPABLE | \
38 VIRTGPU_BLOB_FLAG_USE_SHAREABLE | \
39 VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE)
40
41void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file)
42{
43 struct virtio_gpu_device *vgdev = dev->dev_private;
44 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
45 char dbgname[TASK_COMM_LEN];
46
47 mutex_lock(&vfpriv->context_lock);
48 if (vfpriv->context_created)
49 goto out_unlock;
50
51 get_task_comm(dbgname, current);
52 virtio_gpu_cmd_context_create(vgdev, vfpriv->ctx_id,
53 strlen(dbgname), dbgname);
54 vfpriv->context_created = true;
55
56out_unlock:
57 mutex_unlock(&vfpriv->context_lock);
58}
59
60static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
61 struct drm_file *file)
62{
63 struct virtio_gpu_device *vgdev = dev->dev_private;
64 struct drm_virtgpu_map *virtio_gpu_map = data;
65
66 return virtio_gpu_mode_dumb_mmap(file, vgdev->ddev,
67 virtio_gpu_map->handle,
68 &virtio_gpu_map->offset);
69}
70
71/*
72 * Usage of execbuffer:
73 * Relocations need to take into account the full VIRTIO_GPUDrawable size.
74 * However, the command as passed from user space must *not* contain the initial
75 * VIRTIO_GPUReleaseInfo struct (first XXX bytes)
76 */
77static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
78 struct drm_file *file)
79{
80 struct drm_virtgpu_execbuffer *exbuf = data;
81 struct virtio_gpu_device *vgdev = dev->dev_private;
82 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
83 struct virtio_gpu_fence *out_fence;
84 int ret;
85 uint32_t *bo_handles = NULL;
86 void __user *user_bo_handles = NULL;
87 struct virtio_gpu_object_array *buflist = NULL;
88 struct sync_file *sync_file;
89 int in_fence_fd = exbuf->fence_fd;
90 int out_fence_fd = -1;
91 void *buf;
92
93 if (vgdev->has_virgl_3d == false)
94 return -ENOSYS;
95
96 if ((exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS))
97 return -EINVAL;
98
99 exbuf->fence_fd = -1;
100
101 virtio_gpu_create_context(dev, file);
102 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) {
103 struct dma_fence *in_fence;
104
105 in_fence = sync_file_get_fence(in_fence_fd);
106
107 if (!in_fence)
108 return -EINVAL;
109
110 /*
111 * Wait if the fence is from a foreign context, or if the fence
112 * array contains any fence from a foreign context.
113 */
114 ret = 0;
115 if (!dma_fence_match_context(in_fence, vgdev->fence_drv.context))
116 ret = dma_fence_wait(in_fence, true);
117
118 dma_fence_put(in_fence);
119 if (ret)
120 return ret;
121 }
122
123 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) {
124 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
125 if (out_fence_fd < 0)
126 return out_fence_fd;
127 }
128
129 if (exbuf->num_bo_handles) {
130 bo_handles = kvmalloc_array(exbuf->num_bo_handles,
131 sizeof(uint32_t), GFP_KERNEL);
132 if (!bo_handles) {
133 ret = -ENOMEM;
134 goto out_unused_fd;
135 }
136
137 user_bo_handles = u64_to_user_ptr(exbuf->bo_handles);
138 if (copy_from_user(bo_handles, user_bo_handles,
139 exbuf->num_bo_handles * sizeof(uint32_t))) {
140 ret = -EFAULT;
141 goto out_unused_fd;
142 }
143
144 buflist = virtio_gpu_array_from_handles(file, bo_handles,
145 exbuf->num_bo_handles);
146 if (!buflist) {
147 ret = -ENOENT;
148 goto out_unused_fd;
149 }
150 kvfree(bo_handles);
151 bo_handles = NULL;
152 }
153
154 buf = vmemdup_user(u64_to_user_ptr(exbuf->command), exbuf->size);
155 if (IS_ERR(buf)) {
156 ret = PTR_ERR(buf);
157 goto out_unused_fd;
158 }
159
160 if (buflist) {
161 ret = virtio_gpu_array_lock_resv(buflist);
162 if (ret)
163 goto out_memdup;
164 }
165
166 out_fence = virtio_gpu_fence_alloc(vgdev);
167 if(!out_fence) {
168 ret = -ENOMEM;
169 goto out_unresv;
170 }
171
172 if (out_fence_fd >= 0) {
173 sync_file = sync_file_create(&out_fence->f);
174 if (!sync_file) {
175 dma_fence_put(&out_fence->f);
176 ret = -ENOMEM;
177 goto out_unresv;
178 }
179
180 exbuf->fence_fd = out_fence_fd;
181 fd_install(out_fence_fd, sync_file->file);
182 }
183
184 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
185 vfpriv->ctx_id, buflist, out_fence);
186 dma_fence_put(&out_fence->f);
187 virtio_gpu_notify(vgdev);
188 return 0;
189
190out_unresv:
191 if (buflist)
192 virtio_gpu_array_unlock_resv(buflist);
193out_memdup:
194 kvfree(buf);
195out_unused_fd:
196 kvfree(bo_handles);
197 if (buflist)
198 virtio_gpu_array_put_free(buflist);
199
200 if (out_fence_fd >= 0)
201 put_unused_fd(out_fence_fd);
202
203 return ret;
204}
205
206static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
207 struct drm_file *file)
208{
209 struct virtio_gpu_device *vgdev = dev->dev_private;
210 struct drm_virtgpu_getparam *param = data;
211 int value;
212
213 switch (param->param) {
214 case VIRTGPU_PARAM_3D_FEATURES:
215 value = vgdev->has_virgl_3d ? 1 : 0;
216 break;
217 case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
218 value = 1;
219 break;
220 case VIRTGPU_PARAM_RESOURCE_BLOB:
221 value = vgdev->has_resource_blob ? 1 : 0;
222 break;
223 case VIRTGPU_PARAM_HOST_VISIBLE:
224 value = vgdev->has_host_visible ? 1 : 0;
225 break;
226 case VIRTGPU_PARAM_CROSS_DEVICE:
227 value = vgdev->has_resource_assign_uuid ? 1 : 0;
228 break;
229 default:
230 return -EINVAL;
231 }
232 if (copy_to_user(u64_to_user_ptr(param->value), &value, sizeof(int)))
233 return -EFAULT;
234
235 return 0;
236}
237
238static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
239 struct drm_file *file)
240{
241 struct virtio_gpu_device *vgdev = dev->dev_private;
242 struct drm_virtgpu_resource_create *rc = data;
243 struct virtio_gpu_fence *fence;
244 int ret;
245 struct virtio_gpu_object *qobj;
246 struct drm_gem_object *obj;
247 uint32_t handle = 0;
248 struct virtio_gpu_object_params params = { 0 };
249
250 if (vgdev->has_virgl_3d) {
251 virtio_gpu_create_context(dev, file);
252 params.virgl = true;
253 params.target = rc->target;
254 params.bind = rc->bind;
255 params.depth = rc->depth;
256 params.array_size = rc->array_size;
257 params.last_level = rc->last_level;
258 params.nr_samples = rc->nr_samples;
259 params.flags = rc->flags;
260 } else {
261 if (rc->depth > 1)
262 return -EINVAL;
263 if (rc->nr_samples > 1)
264 return -EINVAL;
265 if (rc->last_level > 1)
266 return -EINVAL;
267 if (rc->target != 2)
268 return -EINVAL;
269 if (rc->array_size > 1)
270 return -EINVAL;
271 }
272
273 params.format = rc->format;
274 params.width = rc->width;
275 params.height = rc->height;
276 params.size = rc->size;
277 /* allocate a single page size object */
278 if (params.size == 0)
279 params.size = PAGE_SIZE;
280
281 fence = virtio_gpu_fence_alloc(vgdev);
282 if (!fence)
283 return -ENOMEM;
284 ret = virtio_gpu_object_create(vgdev, ¶ms, &qobj, fence);
285 dma_fence_put(&fence->f);
286 if (ret < 0)
287 return ret;
288 obj = &qobj->base.base;
289
290 ret = drm_gem_handle_create(file, obj, &handle);
291 if (ret) {
292 drm_gem_object_release(obj);
293 return ret;
294 }
295 drm_gem_object_put(obj);
296
297 rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */
298 rc->bo_handle = handle;
299 return 0;
300}
301
302static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
303 struct drm_file *file)
304{
305 struct drm_virtgpu_resource_info *ri = data;
306 struct drm_gem_object *gobj = NULL;
307 struct virtio_gpu_object *qobj = NULL;
308
309 gobj = drm_gem_object_lookup(file, ri->bo_handle);
310 if (gobj == NULL)
311 return -ENOENT;
312
313 qobj = gem_to_virtio_gpu_obj(gobj);
314
315 ri->size = qobj->base.base.size;
316 ri->res_handle = qobj->hw_res_handle;
317 if (qobj->host3d_blob || qobj->guest_blob)
318 ri->blob_mem = qobj->blob_mem;
319
320 drm_gem_object_put(gobj);
321 return 0;
322}
323
324static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
325 void *data,
326 struct drm_file *file)
327{
328 struct virtio_gpu_device *vgdev = dev->dev_private;
329 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
330 struct drm_virtgpu_3d_transfer_from_host *args = data;
331 struct virtio_gpu_object *bo;
332 struct virtio_gpu_object_array *objs;
333 struct virtio_gpu_fence *fence;
334 int ret;
335 u32 offset = args->offset;
336
337 if (vgdev->has_virgl_3d == false)
338 return -ENOSYS;
339
340 virtio_gpu_create_context(dev, file);
341 objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
342 if (objs == NULL)
343 return -ENOENT;
344
345 bo = gem_to_virtio_gpu_obj(objs->objs[0]);
346 if (bo->guest_blob && !bo->host3d_blob) {
347 ret = -EINVAL;
348 goto err_put_free;
349 }
350
351 if (!bo->host3d_blob && (args->stride || args->layer_stride)) {
352 ret = -EINVAL;
353 goto err_put_free;
354 }
355
356 ret = virtio_gpu_array_lock_resv(objs);
357 if (ret != 0)
358 goto err_put_free;
359
360 fence = virtio_gpu_fence_alloc(vgdev);
361 if (!fence) {
362 ret = -ENOMEM;
363 goto err_unlock;
364 }
365
366 virtio_gpu_cmd_transfer_from_host_3d
367 (vgdev, vfpriv->ctx_id, offset, args->level, args->stride,
368 args->layer_stride, &args->box, objs, fence);
369 dma_fence_put(&fence->f);
370 virtio_gpu_notify(vgdev);
371 return 0;
372
373err_unlock:
374 virtio_gpu_array_unlock_resv(objs);
375err_put_free:
376 virtio_gpu_array_put_free(objs);
377 return ret;
378}
379
380static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
381 struct drm_file *file)
382{
383 struct virtio_gpu_device *vgdev = dev->dev_private;
384 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
385 struct drm_virtgpu_3d_transfer_to_host *args = data;
386 struct virtio_gpu_object *bo;
387 struct virtio_gpu_object_array *objs;
388 struct virtio_gpu_fence *fence;
389 int ret;
390 u32 offset = args->offset;
391
392 objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
393 if (objs == NULL)
394 return -ENOENT;
395
396 bo = gem_to_virtio_gpu_obj(objs->objs[0]);
397 if (bo->guest_blob && !bo->host3d_blob) {
398 ret = -EINVAL;
399 goto err_put_free;
400 }
401
402 if (!vgdev->has_virgl_3d) {
403 virtio_gpu_cmd_transfer_to_host_2d
404 (vgdev, offset,
405 args->box.w, args->box.h, args->box.x, args->box.y,
406 objs, NULL);
407 } else {
408 virtio_gpu_create_context(dev, file);
409
410 if (!bo->host3d_blob && (args->stride || args->layer_stride)) {
411 ret = -EINVAL;
412 goto err_put_free;
413 }
414
415 ret = virtio_gpu_array_lock_resv(objs);
416 if (ret != 0)
417 goto err_put_free;
418
419 ret = -ENOMEM;
420 fence = virtio_gpu_fence_alloc(vgdev);
421 if (!fence)
422 goto err_unlock;
423
424 virtio_gpu_cmd_transfer_to_host_3d
425 (vgdev,
426 vfpriv ? vfpriv->ctx_id : 0, offset, args->level,
427 args->stride, args->layer_stride, &args->box, objs,
428 fence);
429 dma_fence_put(&fence->f);
430 }
431 virtio_gpu_notify(vgdev);
432 return 0;
433
434err_unlock:
435 virtio_gpu_array_unlock_resv(objs);
436err_put_free:
437 virtio_gpu_array_put_free(objs);
438 return ret;
439}
440
441static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
442 struct drm_file *file)
443{
444 struct drm_virtgpu_3d_wait *args = data;
445 struct drm_gem_object *obj;
446 long timeout = 15 * HZ;
447 int ret;
448
449 obj = drm_gem_object_lookup(file, args->handle);
450 if (obj == NULL)
451 return -ENOENT;
452
453 if (args->flags & VIRTGPU_WAIT_NOWAIT) {
454 ret = dma_resv_test_signaled(obj->resv, true);
455 } else {
456 ret = dma_resv_wait_timeout(obj->resv, true, true, timeout);
457 }
458 if (ret == 0)
459 ret = -EBUSY;
460 else if (ret > 0)
461 ret = 0;
462
463 drm_gem_object_put(obj);
464 return ret;
465}
466
467static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
468 void *data, struct drm_file *file)
469{
470 struct virtio_gpu_device *vgdev = dev->dev_private;
471 struct drm_virtgpu_get_caps *args = data;
472 unsigned size, host_caps_size;
473 int i;
474 int found_valid = -1;
475 int ret;
476 struct virtio_gpu_drv_cap_cache *cache_ent;
477 void *ptr;
478
479 if (vgdev->num_capsets == 0)
480 return -ENOSYS;
481
482 /* don't allow userspace to pass 0 */
483 if (args->size == 0)
484 return -EINVAL;
485
486 spin_lock(&vgdev->display_info_lock);
487 for (i = 0; i < vgdev->num_capsets; i++) {
488 if (vgdev->capsets[i].id == args->cap_set_id) {
489 if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
490 found_valid = i;
491 break;
492 }
493 }
494 }
495
496 if (found_valid == -1) {
497 spin_unlock(&vgdev->display_info_lock);
498 return -EINVAL;
499 }
500
501 host_caps_size = vgdev->capsets[found_valid].max_size;
502 /* only copy to user the minimum of the host caps size or the guest caps size */
503 size = min(args->size, host_caps_size);
504
505 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
506 if (cache_ent->id == args->cap_set_id &&
507 cache_ent->version == args->cap_set_ver) {
508 spin_unlock(&vgdev->display_info_lock);
509 goto copy_exit;
510 }
511 }
512 spin_unlock(&vgdev->display_info_lock);
513
514 /* not in cache - need to talk to hw */
515 virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
516 &cache_ent);
517 virtio_gpu_notify(vgdev);
518
519copy_exit:
520 ret = wait_event_timeout(vgdev->resp_wq,
521 atomic_read(&cache_ent->is_valid), 5 * HZ);
522 if (!ret)
523 return -EBUSY;
524
525 /* is_valid check must proceed before copy of the cache entry. */
526 smp_rmb();
527
528 ptr = cache_ent->caps_cache;
529
530 if (copy_to_user(u64_to_user_ptr(args->addr), ptr, size))
531 return -EFAULT;
532
533 return 0;
534}
535
536static int verify_blob(struct virtio_gpu_device *vgdev,
537 struct virtio_gpu_fpriv *vfpriv,
538 struct virtio_gpu_object_params *params,
539 struct drm_virtgpu_resource_create_blob *rc_blob,
540 bool *guest_blob, bool *host3d_blob)
541{
542 if (!vgdev->has_resource_blob)
543 return -EINVAL;
544
545 if ((rc_blob->blob_flags & ~VIRTGPU_BLOB_FLAG_USE_MASK) ||
546 !rc_blob->blob_flags)
547 return -EINVAL;
548
549 if (rc_blob->blob_flags & VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE) {
550 if (!vgdev->has_resource_assign_uuid)
551 return -EINVAL;
552 }
553
554 switch (rc_blob->blob_mem) {
555 case VIRTGPU_BLOB_MEM_GUEST:
556 *guest_blob = true;
557 break;
558 case VIRTGPU_BLOB_MEM_HOST3D_GUEST:
559 *guest_blob = true;
560 fallthrough;
561 case VIRTGPU_BLOB_MEM_HOST3D:
562 *host3d_blob = true;
563 break;
564 default:
565 return -EINVAL;
566 }
567
568 if (*host3d_blob) {
569 if (!vgdev->has_virgl_3d)
570 return -EINVAL;
571
572 /* Must be dword aligned. */
573 if (rc_blob->cmd_size % 4 != 0)
574 return -EINVAL;
575
576 params->ctx_id = vfpriv->ctx_id;
577 params->blob_id = rc_blob->blob_id;
578 } else {
579 if (rc_blob->blob_id != 0)
580 return -EINVAL;
581
582 if (rc_blob->cmd_size != 0)
583 return -EINVAL;
584 }
585
586 params->blob_mem = rc_blob->blob_mem;
587 params->size = rc_blob->size;
588 params->blob = true;
589 params->blob_flags = rc_blob->blob_flags;
590 return 0;
591}
592
593static int virtio_gpu_resource_create_blob_ioctl(struct drm_device *dev,
594 void *data,
595 struct drm_file *file)
596{
597 int ret = 0;
598 uint32_t handle = 0;
599 bool guest_blob = false;
600 bool host3d_blob = false;
601 struct drm_gem_object *obj;
602 struct virtio_gpu_object *bo;
603 struct virtio_gpu_object_params params = { 0 };
604 struct virtio_gpu_device *vgdev = dev->dev_private;
605 struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
606 struct drm_virtgpu_resource_create_blob *rc_blob = data;
607
608 if (verify_blob(vgdev, vfpriv, ¶ms, rc_blob,
609 &guest_blob, &host3d_blob))
610 return -EINVAL;
611
612 if (vgdev->has_virgl_3d)
613 virtio_gpu_create_context(dev, file);
614
615 if (rc_blob->cmd_size) {
616 void *buf;
617
618 buf = memdup_user(u64_to_user_ptr(rc_blob->cmd),
619 rc_blob->cmd_size);
620
621 if (IS_ERR(buf))
622 return PTR_ERR(buf);
623
624 virtio_gpu_cmd_submit(vgdev, buf, rc_blob->cmd_size,
625 vfpriv->ctx_id, NULL, NULL);
626 }
627
628 if (guest_blob)
629 ret = virtio_gpu_object_create(vgdev, ¶ms, &bo, NULL);
630 else if (!guest_blob && host3d_blob)
631 ret = virtio_gpu_vram_create(vgdev, ¶ms, &bo);
632 else
633 return -EINVAL;
634
635 if (ret < 0)
636 return ret;
637
638 bo->guest_blob = guest_blob;
639 bo->host3d_blob = host3d_blob;
640 bo->blob_mem = rc_blob->blob_mem;
641 bo->blob_flags = rc_blob->blob_flags;
642
643 obj = &bo->base.base;
644 if (params.blob_flags & VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE) {
645 ret = virtio_gpu_resource_assign_uuid(vgdev, bo);
646 if (ret) {
647 drm_gem_object_release(obj);
648 return ret;
649 }
650 }
651
652 ret = drm_gem_handle_create(file, obj, &handle);
653 if (ret) {
654 drm_gem_object_release(obj);
655 return ret;
656 }
657 drm_gem_object_put(obj);
658
659 rc_blob->res_handle = bo->hw_res_handle;
660 rc_blob->bo_handle = handle;
661
662 return 0;
663}
664
665struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
666 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
667 DRM_RENDER_ALLOW),
668
669 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
670 DRM_RENDER_ALLOW),
671
672 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
673 DRM_RENDER_ALLOW),
674
675 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
676 virtio_gpu_resource_create_ioctl,
677 DRM_RENDER_ALLOW),
678
679 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
680 DRM_RENDER_ALLOW),
681
682 /* make transfer async to the main ring? - no sure, can we
683 * thread these in the underlying GL
684 */
685 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
686 virtio_gpu_transfer_from_host_ioctl,
687 DRM_RENDER_ALLOW),
688 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
689 virtio_gpu_transfer_to_host_ioctl,
690 DRM_RENDER_ALLOW),
691
692 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
693 DRM_RENDER_ALLOW),
694
695 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
696 DRM_RENDER_ALLOW),
697
698 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE_BLOB,
699 virtio_gpu_resource_create_blob_ioctl,
700 DRM_RENDER_ALLOW),
701};