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1/*
2 * i.MX IPUv3 Graphics driver
3 *
4 * Copyright (C) 2011 Sascha Hauer, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/component.h>
16#include <linux/module.h>
17#include <linux/export.h>
18#include <linux/device.h>
19#include <linux/platform_device.h>
20#include <drm/drmP.h>
21#include <drm/drm_atomic.h>
22#include <drm/drm_atomic_helper.h>
23#include <drm/drm_crtc_helper.h>
24#include <linux/clk.h>
25#include <linux/errno.h>
26#include <drm/drm_gem_cma_helper.h>
27#include <drm/drm_fb_cma_helper.h>
28
29#include <video/imx-ipu-v3.h>
30#include "imx-drm.h"
31#include "ipuv3-plane.h"
32
33#define DRIVER_DESC "i.MX IPUv3 Graphics"
34
35struct ipu_crtc {
36 struct device *dev;
37 struct drm_crtc base;
38 struct imx_drm_crtc *imx_crtc;
39
40 /* plane[0] is the full plane, plane[1] is the partial plane */
41 struct ipu_plane *plane[2];
42
43 struct ipu_dc *dc;
44 struct ipu_di *di;
45 int irq;
46};
47
48static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
49{
50 return container_of(crtc, struct ipu_crtc, base);
51}
52
53static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
54 struct drm_crtc_state *old_state)
55{
56 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
57 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
58
59 ipu_prg_enable(ipu);
60 ipu_dc_enable(ipu);
61 ipu_dc_enable_channel(ipu_crtc->dc);
62 ipu_di_enable(ipu_crtc->di);
63}
64
65static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
66 struct drm_crtc_state *old_crtc_state)
67{
68 bool disable_partial = false;
69 bool disable_full = false;
70 struct drm_plane *plane;
71
72 drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
73 if (plane == &ipu_crtc->plane[0]->base)
74 disable_full = true;
75 if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
76 disable_partial = true;
77 }
78
79 if (disable_partial)
80 ipu_plane_disable(ipu_crtc->plane[1], true);
81 if (disable_full)
82 ipu_plane_disable(ipu_crtc->plane[0], false);
83}
84
85static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
86 struct drm_crtc_state *old_crtc_state)
87{
88 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
89 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
90
91 ipu_dc_disable_channel(ipu_crtc->dc);
92 ipu_di_disable(ipu_crtc->di);
93 /*
94 * Planes must be disabled before DC clock is removed, as otherwise the
95 * attached IDMACs will be left in undefined state, possibly hanging
96 * the IPU or even system.
97 */
98 ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
99 ipu_dc_disable(ipu);
100 ipu_prg_disable(ipu);
101
102 spin_lock_irq(&crtc->dev->event_lock);
103 if (crtc->state->event) {
104 drm_crtc_send_vblank_event(crtc, crtc->state->event);
105 crtc->state->event = NULL;
106 }
107 spin_unlock_irq(&crtc->dev->event_lock);
108
109 drm_crtc_vblank_off(crtc);
110}
111
112static void imx_drm_crtc_reset(struct drm_crtc *crtc)
113{
114 struct imx_crtc_state *state;
115
116 if (crtc->state) {
117 if (crtc->state->mode_blob)
118 drm_property_blob_put(crtc->state->mode_blob);
119
120 state = to_imx_crtc_state(crtc->state);
121 memset(state, 0, sizeof(*state));
122 } else {
123 state = kzalloc(sizeof(*state), GFP_KERNEL);
124 if (!state)
125 return;
126 crtc->state = &state->base;
127 }
128
129 state->base.crtc = crtc;
130}
131
132static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
133{
134 struct imx_crtc_state *state;
135
136 state = kzalloc(sizeof(*state), GFP_KERNEL);
137 if (!state)
138 return NULL;
139
140 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
141
142 WARN_ON(state->base.crtc != crtc);
143 state->base.crtc = crtc;
144
145 return &state->base;
146}
147
148static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
149 struct drm_crtc_state *state)
150{
151 __drm_atomic_helper_crtc_destroy_state(state);
152 kfree(to_imx_crtc_state(state));
153}
154
155static int ipu_enable_vblank(struct drm_crtc *crtc)
156{
157 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
158
159 enable_irq(ipu_crtc->irq);
160
161 return 0;
162}
163
164static void ipu_disable_vblank(struct drm_crtc *crtc)
165{
166 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
167
168 disable_irq_nosync(ipu_crtc->irq);
169}
170
171static const struct drm_crtc_funcs ipu_crtc_funcs = {
172 .set_config = drm_atomic_helper_set_config,
173 .destroy = drm_crtc_cleanup,
174 .page_flip = drm_atomic_helper_page_flip,
175 .reset = imx_drm_crtc_reset,
176 .atomic_duplicate_state = imx_drm_crtc_duplicate_state,
177 .atomic_destroy_state = imx_drm_crtc_destroy_state,
178 .enable_vblank = ipu_enable_vblank,
179 .disable_vblank = ipu_disable_vblank,
180};
181
182static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
183{
184 struct ipu_crtc *ipu_crtc = dev_id;
185
186 drm_crtc_handle_vblank(&ipu_crtc->base);
187
188 return IRQ_HANDLED;
189}
190
191static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
192 const struct drm_display_mode *mode,
193 struct drm_display_mode *adjusted_mode)
194{
195 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
196 struct videomode vm;
197 int ret;
198
199 drm_display_mode_to_videomode(adjusted_mode, &vm);
200
201 ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
202 if (ret)
203 return false;
204
205 if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
206 return false;
207
208 drm_display_mode_from_videomode(&vm, adjusted_mode);
209
210 return true;
211}
212
213static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
214 struct drm_crtc_state *state)
215{
216 u32 primary_plane_mask = 1 << drm_plane_index(crtc->primary);
217
218 if (state->active && (primary_plane_mask & state->plane_mask) == 0)
219 return -EINVAL;
220
221 return 0;
222}
223
224static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
225 struct drm_crtc_state *old_crtc_state)
226{
227 drm_crtc_vblank_on(crtc);
228}
229
230static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
231 struct drm_crtc_state *old_crtc_state)
232{
233 spin_lock_irq(&crtc->dev->event_lock);
234 if (crtc->state->event) {
235 WARN_ON(drm_crtc_vblank_get(crtc));
236 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
237 crtc->state->event = NULL;
238 }
239 spin_unlock_irq(&crtc->dev->event_lock);
240}
241
242static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
243{
244 struct drm_device *dev = crtc->dev;
245 struct drm_encoder *encoder;
246 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
247 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
248 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
249 struct ipu_di_signal_cfg sig_cfg = {};
250 unsigned long encoder_types = 0;
251
252 dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
253 mode->hdisplay);
254 dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
255 mode->vdisplay);
256
257 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
258 if (encoder->crtc == crtc)
259 encoder_types |= BIT(encoder->encoder_type);
260 }
261
262 dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
263 __func__, encoder_types);
264
265 /*
266 * If we have DAC or LDB, then we need the IPU DI clock to be
267 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
268 * clock from 27 MHz TVE_DI clock, but allow to divide it.
269 */
270 if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
271 BIT(DRM_MODE_ENCODER_LVDS)))
272 sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
273 else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
274 sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
275 else
276 sig_cfg.clkflags = 0;
277
278 sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
279 /* Default to driving pixel data on negative clock edges */
280 sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
281 DRM_BUS_FLAG_PIXDATA_POSEDGE);
282 sig_cfg.bus_format = imx_crtc_state->bus_format;
283 sig_cfg.v_to_h_sync = 0;
284 sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
285 sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
286
287 drm_display_mode_to_videomode(mode, &sig_cfg.mode);
288
289 ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
290 mode->flags & DRM_MODE_FLAG_INTERLACE,
291 imx_crtc_state->bus_format, mode->hdisplay);
292 ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
293}
294
295static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
296 .mode_fixup = ipu_crtc_mode_fixup,
297 .mode_set_nofb = ipu_crtc_mode_set_nofb,
298 .atomic_check = ipu_crtc_atomic_check,
299 .atomic_begin = ipu_crtc_atomic_begin,
300 .atomic_flush = ipu_crtc_atomic_flush,
301 .atomic_disable = ipu_crtc_atomic_disable,
302 .atomic_enable = ipu_crtc_atomic_enable,
303};
304
305static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
306{
307 if (!IS_ERR_OR_NULL(ipu_crtc->dc))
308 ipu_dc_put(ipu_crtc->dc);
309 if (!IS_ERR_OR_NULL(ipu_crtc->di))
310 ipu_di_put(ipu_crtc->di);
311}
312
313static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
314 struct ipu_client_platformdata *pdata)
315{
316 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
317 int ret;
318
319 ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
320 if (IS_ERR(ipu_crtc->dc)) {
321 ret = PTR_ERR(ipu_crtc->dc);
322 goto err_out;
323 }
324
325 ipu_crtc->di = ipu_di_get(ipu, pdata->di);
326 if (IS_ERR(ipu_crtc->di)) {
327 ret = PTR_ERR(ipu_crtc->di);
328 goto err_out;
329 }
330
331 return 0;
332err_out:
333 ipu_put_resources(ipu_crtc);
334
335 return ret;
336}
337
338static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
339 struct ipu_client_platformdata *pdata, struct drm_device *drm)
340{
341 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
342 struct drm_crtc *crtc = &ipu_crtc->base;
343 int dp = -EINVAL;
344 int ret;
345
346 ret = ipu_get_resources(ipu_crtc, pdata);
347 if (ret) {
348 dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
349 ret);
350 return ret;
351 }
352
353 if (pdata->dp >= 0)
354 dp = IPU_DP_FLOW_SYNC_BG;
355 ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
356 DRM_PLANE_TYPE_PRIMARY);
357 if (IS_ERR(ipu_crtc->plane[0])) {
358 ret = PTR_ERR(ipu_crtc->plane[0]);
359 goto err_put_resources;
360 }
361
362 crtc->port = pdata->of_node;
363 drm_crtc_helper_add(crtc, &ipu_helper_funcs);
364 drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL,
365 &ipu_crtc_funcs, NULL);
366
367 ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
368 if (ret) {
369 dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
370 ret);
371 goto err_put_resources;
372 }
373
374 /* If this crtc is using the DP, add an overlay plane */
375 if (pdata->dp >= 0 && pdata->dma[1] > 0) {
376 ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
377 IPU_DP_FLOW_SYNC_FG,
378 drm_crtc_mask(&ipu_crtc->base),
379 DRM_PLANE_TYPE_OVERLAY);
380 if (IS_ERR(ipu_crtc->plane[1])) {
381 ipu_crtc->plane[1] = NULL;
382 } else {
383 ret = ipu_plane_get_resources(ipu_crtc->plane[1]);
384 if (ret) {
385 dev_err(ipu_crtc->dev, "getting plane 1 "
386 "resources failed with %d.\n", ret);
387 goto err_put_plane0_res;
388 }
389 }
390 }
391
392 ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
393 ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
394 "imx_drm", ipu_crtc);
395 if (ret < 0) {
396 dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
397 goto err_put_plane1_res;
398 }
399 /* Only enable IRQ when we actually need it to trigger work. */
400 disable_irq(ipu_crtc->irq);
401
402 return 0;
403
404err_put_plane1_res:
405 if (ipu_crtc->plane[1])
406 ipu_plane_put_resources(ipu_crtc->plane[1]);
407err_put_plane0_res:
408 ipu_plane_put_resources(ipu_crtc->plane[0]);
409err_put_resources:
410 ipu_put_resources(ipu_crtc);
411
412 return ret;
413}
414
415static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
416{
417 struct ipu_client_platformdata *pdata = dev->platform_data;
418 struct drm_device *drm = data;
419 struct ipu_crtc *ipu_crtc;
420 int ret;
421
422 ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
423 if (!ipu_crtc)
424 return -ENOMEM;
425
426 ipu_crtc->dev = dev;
427
428 ret = ipu_crtc_init(ipu_crtc, pdata, drm);
429 if (ret)
430 return ret;
431
432 dev_set_drvdata(dev, ipu_crtc);
433
434 return 0;
435}
436
437static void ipu_drm_unbind(struct device *dev, struct device *master,
438 void *data)
439{
440 struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
441
442 ipu_put_resources(ipu_crtc);
443 if (ipu_crtc->plane[1])
444 ipu_plane_put_resources(ipu_crtc->plane[1]);
445 ipu_plane_put_resources(ipu_crtc->plane[0]);
446}
447
448static const struct component_ops ipu_crtc_ops = {
449 .bind = ipu_drm_bind,
450 .unbind = ipu_drm_unbind,
451};
452
453static int ipu_drm_probe(struct platform_device *pdev)
454{
455 struct device *dev = &pdev->dev;
456 int ret;
457
458 if (!dev->platform_data)
459 return -EINVAL;
460
461 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
462 if (ret)
463 return ret;
464
465 return component_add(dev, &ipu_crtc_ops);
466}
467
468static int ipu_drm_remove(struct platform_device *pdev)
469{
470 component_del(&pdev->dev, &ipu_crtc_ops);
471 return 0;
472}
473
474struct platform_driver ipu_drm_driver = {
475 .driver = {
476 .name = "imx-ipuv3-crtc",
477 },
478 .probe = ipu_drm_probe,
479 .remove = ipu_drm_remove,
480};
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * i.MX IPUv3 Graphics driver
4 *
5 * Copyright (C) 2011 Sascha Hauer, Pengutronix
6 */
7
8#include <linux/clk.h>
9#include <linux/component.h>
10#include <linux/device.h>
11#include <linux/dma-mapping.h>
12#include <linux/errno.h>
13#include <linux/export.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16
17#include <video/imx-ipu-v3.h>
18
19#include <drm/drm_atomic.h>
20#include <drm/drm_atomic_helper.h>
21#include <drm/drm_fb_cma_helper.h>
22#include <drm/drm_gem_cma_helper.h>
23#include <drm/drm_managed.h>
24#include <drm/drm_probe_helper.h>
25#include <drm/drm_vblank.h>
26
27#include "imx-drm.h"
28#include "ipuv3-plane.h"
29
30#define DRIVER_DESC "i.MX IPUv3 Graphics"
31
32struct ipu_crtc {
33 struct device *dev;
34 struct drm_crtc base;
35
36 /* plane[0] is the full plane, plane[1] is the partial plane */
37 struct ipu_plane *plane[2];
38
39 struct ipu_dc *dc;
40 struct ipu_di *di;
41 int irq;
42 struct drm_pending_vblank_event *event;
43};
44
45static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc)
46{
47 return container_of(crtc, struct ipu_crtc, base);
48}
49
50static void ipu_crtc_atomic_enable(struct drm_crtc *crtc,
51 struct drm_atomic_state *state)
52{
53 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
54 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
55
56 ipu_prg_enable(ipu);
57 ipu_dc_enable(ipu);
58 ipu_dc_enable_channel(ipu_crtc->dc);
59 ipu_di_enable(ipu_crtc->di);
60}
61
62static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
63 struct drm_crtc_state *old_crtc_state)
64{
65 bool disable_partial = false;
66 bool disable_full = false;
67 struct drm_plane *plane;
68
69 drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
70 if (plane == &ipu_crtc->plane[0]->base)
71 disable_full = true;
72 if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
73 disable_partial = true;
74 }
75
76 if (disable_partial)
77 ipu_plane_disable(ipu_crtc->plane[1], true);
78 if (disable_full)
79 ipu_plane_disable(ipu_crtc->plane[0], true);
80}
81
82static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
83 struct drm_atomic_state *state)
84{
85 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
86 crtc);
87 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
88 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
89
90 ipu_dc_disable_channel(ipu_crtc->dc);
91 ipu_di_disable(ipu_crtc->di);
92 /*
93 * Planes must be disabled before DC clock is removed, as otherwise the
94 * attached IDMACs will be left in undefined state, possibly hanging
95 * the IPU or even system.
96 */
97 ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
98 ipu_dc_disable(ipu);
99 ipu_prg_disable(ipu);
100
101 drm_crtc_vblank_off(crtc);
102
103 spin_lock_irq(&crtc->dev->event_lock);
104 if (crtc->state->event && !crtc->state->active) {
105 drm_crtc_send_vblank_event(crtc, crtc->state->event);
106 crtc->state->event = NULL;
107 }
108 spin_unlock_irq(&crtc->dev->event_lock);
109}
110
111static void imx_drm_crtc_reset(struct drm_crtc *crtc)
112{
113 struct imx_crtc_state *state;
114
115 if (crtc->state)
116 __drm_atomic_helper_crtc_destroy_state(crtc->state);
117
118 kfree(to_imx_crtc_state(crtc->state));
119 crtc->state = NULL;
120
121 state = kzalloc(sizeof(*state), GFP_KERNEL);
122 if (state)
123 __drm_atomic_helper_crtc_reset(crtc, &state->base);
124}
125
126static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc)
127{
128 struct imx_crtc_state *state;
129
130 state = kzalloc(sizeof(*state), GFP_KERNEL);
131 if (!state)
132 return NULL;
133
134 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
135
136 WARN_ON(state->base.crtc != crtc);
137 state->base.crtc = crtc;
138
139 return &state->base;
140}
141
142static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc,
143 struct drm_crtc_state *state)
144{
145 __drm_atomic_helper_crtc_destroy_state(state);
146 kfree(to_imx_crtc_state(state));
147}
148
149static int ipu_enable_vblank(struct drm_crtc *crtc)
150{
151 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
152
153 enable_irq(ipu_crtc->irq);
154
155 return 0;
156}
157
158static void ipu_disable_vblank(struct drm_crtc *crtc)
159{
160 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
161
162 disable_irq_nosync(ipu_crtc->irq);
163}
164
165static const struct drm_crtc_funcs ipu_crtc_funcs = {
166 .set_config = drm_atomic_helper_set_config,
167 .page_flip = drm_atomic_helper_page_flip,
168 .reset = imx_drm_crtc_reset,
169 .atomic_duplicate_state = imx_drm_crtc_duplicate_state,
170 .atomic_destroy_state = imx_drm_crtc_destroy_state,
171 .enable_vblank = ipu_enable_vblank,
172 .disable_vblank = ipu_disable_vblank,
173};
174
175static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
176{
177 struct ipu_crtc *ipu_crtc = dev_id;
178 struct drm_crtc *crtc = &ipu_crtc->base;
179 unsigned long flags;
180 int i;
181
182 drm_crtc_handle_vblank(crtc);
183
184 if (ipu_crtc->event) {
185 for (i = 0; i < ARRAY_SIZE(ipu_crtc->plane); i++) {
186 struct ipu_plane *plane = ipu_crtc->plane[i];
187
188 if (!plane)
189 continue;
190
191 if (ipu_plane_atomic_update_pending(&plane->base))
192 break;
193 }
194
195 if (i == ARRAY_SIZE(ipu_crtc->plane)) {
196 spin_lock_irqsave(&crtc->dev->event_lock, flags);
197 drm_crtc_send_vblank_event(crtc, ipu_crtc->event);
198 ipu_crtc->event = NULL;
199 drm_crtc_vblank_put(crtc);
200 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
201 }
202 }
203
204 return IRQ_HANDLED;
205}
206
207static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
208 const struct drm_display_mode *mode,
209 struct drm_display_mode *adjusted_mode)
210{
211 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
212 struct videomode vm;
213 int ret;
214
215 drm_display_mode_to_videomode(adjusted_mode, &vm);
216
217 ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm);
218 if (ret)
219 return false;
220
221 if ((vm.vsync_len == 0) || (vm.hsync_len == 0))
222 return false;
223
224 drm_display_mode_from_videomode(&vm, adjusted_mode);
225
226 return true;
227}
228
229static int ipu_crtc_atomic_check(struct drm_crtc *crtc,
230 struct drm_atomic_state *state)
231{
232 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
233 crtc);
234 u32 primary_plane_mask = drm_plane_mask(crtc->primary);
235
236 if (crtc_state->active && (primary_plane_mask & crtc_state->plane_mask) == 0)
237 return -EINVAL;
238
239 return 0;
240}
241
242static void ipu_crtc_atomic_begin(struct drm_crtc *crtc,
243 struct drm_atomic_state *state)
244{
245 drm_crtc_vblank_on(crtc);
246}
247
248static void ipu_crtc_atomic_flush(struct drm_crtc *crtc,
249 struct drm_atomic_state *state)
250{
251 spin_lock_irq(&crtc->dev->event_lock);
252 if (crtc->state->event) {
253 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
254
255 WARN_ON(drm_crtc_vblank_get(crtc));
256 ipu_crtc->event = crtc->state->event;
257 crtc->state->event = NULL;
258 }
259 spin_unlock_irq(&crtc->dev->event_lock);
260}
261
262static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc)
263{
264 struct drm_device *dev = crtc->dev;
265 struct drm_encoder *encoder;
266 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
267 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
268 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state);
269 struct ipu_di_signal_cfg sig_cfg = {};
270 unsigned long encoder_types = 0;
271
272 dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
273 mode->hdisplay);
274 dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
275 mode->vdisplay);
276
277 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
278 if (encoder->crtc == crtc)
279 encoder_types |= BIT(encoder->encoder_type);
280 }
281
282 dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n",
283 __func__, encoder_types);
284
285 /*
286 * If we have DAC or LDB, then we need the IPU DI clock to be
287 * the same as the LDB DI clock. For TVDAC, derive the IPU DI
288 * clock from 27 MHz TVE_DI clock, but allow to divide it.
289 */
290 if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) |
291 BIT(DRM_MODE_ENCODER_LVDS)))
292 sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT;
293 else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC))
294 sig_cfg.clkflags = IPU_DI_CLKMODE_EXT;
295 else
296 sig_cfg.clkflags = 0;
297
298 sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW);
299 /* Default to driving pixel data on negative clock edges */
300 sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags &
301 DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE);
302 sig_cfg.bus_format = imx_crtc_state->bus_format;
303 sig_cfg.v_to_h_sync = 0;
304 sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin;
305 sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin;
306
307 drm_display_mode_to_videomode(mode, &sig_cfg.mode);
308 if (!IS_ALIGNED(sig_cfg.mode.hactive, 8)) {
309 unsigned int new_hactive = ALIGN(sig_cfg.mode.hactive, 8);
310
311 dev_warn(ipu_crtc->dev, "8-pixel align hactive %d -> %d\n",
312 sig_cfg.mode.hactive, new_hactive);
313
314 sig_cfg.mode.hfront_porch = new_hactive - sig_cfg.mode.hactive;
315 sig_cfg.mode.hactive = new_hactive;
316 }
317
318 ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di,
319 mode->flags & DRM_MODE_FLAG_INTERLACE,
320 imx_crtc_state->bus_format, sig_cfg.mode.hactive);
321 ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
322}
323
324static const struct drm_crtc_helper_funcs ipu_helper_funcs = {
325 .mode_fixup = ipu_crtc_mode_fixup,
326 .mode_set_nofb = ipu_crtc_mode_set_nofb,
327 .atomic_check = ipu_crtc_atomic_check,
328 .atomic_begin = ipu_crtc_atomic_begin,
329 .atomic_flush = ipu_crtc_atomic_flush,
330 .atomic_disable = ipu_crtc_atomic_disable,
331 .atomic_enable = ipu_crtc_atomic_enable,
332};
333
334static void ipu_put_resources(struct drm_device *dev, void *ptr)
335{
336 struct ipu_crtc *ipu_crtc = ptr;
337
338 if (!IS_ERR_OR_NULL(ipu_crtc->dc))
339 ipu_dc_put(ipu_crtc->dc);
340 if (!IS_ERR_OR_NULL(ipu_crtc->di))
341 ipu_di_put(ipu_crtc->di);
342}
343
344static int ipu_get_resources(struct drm_device *dev, struct ipu_crtc *ipu_crtc,
345 struct ipu_client_platformdata *pdata)
346{
347 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
348 int ret;
349
350 ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
351 if (IS_ERR(ipu_crtc->dc))
352 return PTR_ERR(ipu_crtc->dc);
353
354 ret = drmm_add_action_or_reset(dev, ipu_put_resources, ipu_crtc);
355 if (ret)
356 return ret;
357
358 ipu_crtc->di = ipu_di_get(ipu, pdata->di);
359 if (IS_ERR(ipu_crtc->di))
360 return PTR_ERR(ipu_crtc->di);
361
362 return 0;
363}
364
365static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
366{
367 struct ipu_client_platformdata *pdata = dev->platform_data;
368 struct ipu_soc *ipu = dev_get_drvdata(dev->parent);
369 struct drm_device *drm = data;
370 struct ipu_plane *primary_plane;
371 struct ipu_crtc *ipu_crtc;
372 struct drm_crtc *crtc;
373 int dp = -EINVAL;
374 int ret;
375
376 if (pdata->dp >= 0)
377 dp = IPU_DP_FLOW_SYNC_BG;
378 primary_plane = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0,
379 DRM_PLANE_TYPE_PRIMARY);
380 if (IS_ERR(primary_plane))
381 return PTR_ERR(primary_plane);
382
383 ipu_crtc = drmm_crtc_alloc_with_planes(drm, struct ipu_crtc, base,
384 &primary_plane->base, NULL,
385 &ipu_crtc_funcs, NULL);
386 if (IS_ERR(ipu_crtc))
387 return PTR_ERR(ipu_crtc);
388
389 ipu_crtc->dev = dev;
390 ipu_crtc->plane[0] = primary_plane;
391
392 crtc = &ipu_crtc->base;
393 crtc->port = pdata->of_node;
394 drm_crtc_helper_add(crtc, &ipu_helper_funcs);
395
396 ret = ipu_get_resources(drm, ipu_crtc, pdata);
397 if (ret) {
398 dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
399 ret);
400 return ret;
401 }
402
403 /* If this crtc is using the DP, add an overlay plane */
404 if (pdata->dp >= 0 && pdata->dma[1] > 0) {
405 ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1],
406 IPU_DP_FLOW_SYNC_FG,
407 drm_crtc_mask(&ipu_crtc->base),
408 DRM_PLANE_TYPE_OVERLAY);
409 if (IS_ERR(ipu_crtc->plane[1]))
410 ipu_crtc->plane[1] = NULL;
411 }
412
413 ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
414 ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
415 "imx_drm", ipu_crtc);
416 if (ret < 0) {
417 dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
418 return ret;
419 }
420 /* Only enable IRQ when we actually need it to trigger work. */
421 disable_irq(ipu_crtc->irq);
422
423 return 0;
424}
425
426static const struct component_ops ipu_crtc_ops = {
427 .bind = ipu_drm_bind,
428};
429
430static int ipu_drm_probe(struct platform_device *pdev)
431{
432 struct device *dev = &pdev->dev;
433 int ret;
434
435 if (!dev->platform_data)
436 return -EINVAL;
437
438 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
439 if (ret)
440 return ret;
441
442 return component_add(dev, &ipu_crtc_ops);
443}
444
445static int ipu_drm_remove(struct platform_device *pdev)
446{
447 component_del(&pdev->dev, &ipu_crtc_ops);
448 return 0;
449}
450
451struct platform_driver ipu_drm_driver = {
452 .driver = {
453 .name = "imx-ipuv3-crtc",
454 },
455 .probe = ipu_drm_probe,
456 .remove = ipu_drm_remove,
457};