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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "amdgpu_jpeg.h"
26#include "soc15.h"
27#include "soc15d.h"
28#include "jpeg_v2_0.h"
29
30#include "vcn/vcn_2_5_offset.h"
31#include "vcn/vcn_2_5_sh_mask.h"
32#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
33
34#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
35
36#define JPEG25_MAX_HW_INSTANCES_ARCTURUS 2
37
38static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
39static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
40static int jpeg_v2_5_set_powergating_state(void *handle,
41 enum amd_powergating_state state);
42
43static int amdgpu_ih_clientid_jpeg[] = {
44 SOC15_IH_CLIENTID_VCN,
45 SOC15_IH_CLIENTID_VCN1
46};
47
48/**
49 * jpeg_v2_5_early_init - set function pointers
50 *
51 * @handle: amdgpu_device pointer
52 *
53 * Set ring and irq function pointers
54 */
55static int jpeg_v2_5_early_init(void *handle)
56{
57 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
58 u32 harvest;
59 int i;
60
61 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS;
62 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
63 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING);
64 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
65 adev->jpeg.harvest_config |= 1 << i;
66 }
67 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 |
68 AMDGPU_JPEG_HARVEST_JPEG1))
69 return -ENOENT;
70
71 jpeg_v2_5_set_dec_ring_funcs(adev);
72 jpeg_v2_5_set_irq_funcs(adev);
73
74 return 0;
75}
76
77/**
78 * jpeg_v2_5_sw_init - sw init for JPEG block
79 *
80 * @handle: amdgpu_device pointer
81 *
82 * Load firmware and sw initialization
83 */
84static int jpeg_v2_5_sw_init(void *handle)
85{
86 struct amdgpu_ring *ring;
87 int i, r;
88 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
89
90 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
91 if (adev->jpeg.harvest_config & (1 << i))
92 continue;
93
94 /* JPEG TRAP */
95 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
96 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq);
97 if (r)
98 return r;
99 }
100
101 r = amdgpu_jpeg_sw_init(adev);
102 if (r)
103 return r;
104
105 r = amdgpu_jpeg_resume(adev);
106 if (r)
107 return r;
108
109 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
110 if (adev->jpeg.harvest_config & (1 << i))
111 continue;
112
113 ring = &adev->jpeg.inst[i].ring_dec;
114 ring->use_doorbell = true;
115 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
116 sprintf(ring->name, "jpeg_dec_%d", i);
117 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq,
118 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
119 if (r)
120 return r;
121
122 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
123 adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);
124 }
125
126 return 0;
127}
128
129/**
130 * jpeg_v2_5_sw_fini - sw fini for JPEG block
131 *
132 * @handle: amdgpu_device pointer
133 *
134 * JPEG suspend and free up sw allocation
135 */
136static int jpeg_v2_5_sw_fini(void *handle)
137{
138 int r;
139 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
140
141 r = amdgpu_jpeg_suspend(adev);
142 if (r)
143 return r;
144
145 r = amdgpu_jpeg_sw_fini(adev);
146
147 return r;
148}
149
150/**
151 * jpeg_v2_5_hw_init - start and test JPEG block
152 *
153 * @handle: amdgpu_device pointer
154 *
155 */
156static int jpeg_v2_5_hw_init(void *handle)
157{
158 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
159 struct amdgpu_ring *ring;
160 int i, r;
161
162 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
163 if (adev->jpeg.harvest_config & (1 << i))
164 continue;
165
166 ring = &adev->jpeg.inst[i].ring_dec;
167 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
168 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i);
169
170 r = amdgpu_ring_test_helper(ring);
171 if (r)
172 return r;
173 }
174
175 DRM_INFO("JPEG decode initialized successfully.\n");
176
177 return 0;
178}
179
180/**
181 * jpeg_v2_5_hw_fini - stop the hardware block
182 *
183 * @handle: amdgpu_device pointer
184 *
185 * Stop the JPEG block, mark ring as not ready any more
186 */
187static int jpeg_v2_5_hw_fini(void *handle)
188{
189 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
190 int i;
191
192 cancel_delayed_work_sync(&adev->vcn.idle_work);
193
194 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
195 if (adev->jpeg.harvest_config & (1 << i))
196 continue;
197
198 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
199 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
200 jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
201 }
202
203 return 0;
204}
205
206/**
207 * jpeg_v2_5_suspend - suspend JPEG block
208 *
209 * @handle: amdgpu_device pointer
210 *
211 * HW fini and suspend JPEG block
212 */
213static int jpeg_v2_5_suspend(void *handle)
214{
215 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
216 int r;
217
218 r = jpeg_v2_5_hw_fini(adev);
219 if (r)
220 return r;
221
222 r = amdgpu_jpeg_suspend(adev);
223
224 return r;
225}
226
227/**
228 * jpeg_v2_5_resume - resume JPEG block
229 *
230 * @handle: amdgpu_device pointer
231 *
232 * Resume firmware and hw init JPEG block
233 */
234static int jpeg_v2_5_resume(void *handle)
235{
236 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
237 int r;
238
239 r = amdgpu_jpeg_resume(adev);
240 if (r)
241 return r;
242
243 r = jpeg_v2_5_hw_init(adev);
244
245 return r;
246}
247
248static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
249{
250 uint32_t data;
251
252 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
253 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
254 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
255 else
256 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
257
258 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
259 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
260 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
261
262 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
263 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
264 | JPEG_CGC_GATE__JPEG2_DEC_MASK
265 | JPEG_CGC_GATE__JMCIF_MASK
266 | JPEG_CGC_GATE__JRBBM_MASK);
267 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
268
269 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
270 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
271 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
272 | JPEG_CGC_CTRL__JMCIF_MODE_MASK
273 | JPEG_CGC_CTRL__JRBBM_MODE_MASK);
274 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
275}
276
277static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
278{
279 uint32_t data;
280
281 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
282 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
283 |JPEG_CGC_GATE__JPEG2_DEC_MASK
284 |JPEG_CGC_GATE__JPEG_ENC_MASK
285 |JPEG_CGC_GATE__JMCIF_MASK
286 |JPEG_CGC_GATE__JRBBM_MASK);
287 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
288}
289
290/**
291 * jpeg_v2_5_start - start JPEG block
292 *
293 * @adev: amdgpu_device pointer
294 *
295 * Setup and start the JPEG block
296 */
297static int jpeg_v2_5_start(struct amdgpu_device *adev)
298{
299 struct amdgpu_ring *ring;
300 int i;
301
302 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
303 if (adev->jpeg.harvest_config & (1 << i))
304 continue;
305
306 ring = &adev->jpeg.inst[i].ring_dec;
307 /* disable anti hang mechanism */
308 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
309 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
310
311 /* JPEG disable CGC */
312 jpeg_v2_5_disable_clock_gating(adev, i);
313
314 /* MJPEG global tiling registers */
315 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
316 adev->gfx.config.gb_addr_config);
317 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
318 adev->gfx.config.gb_addr_config);
319
320 /* enable JMI channel */
321 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
322 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
323
324 /* enable System Interrupt for JRBC */
325 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
326 JPEG_SYS_INT_EN__DJRBC_MASK,
327 ~JPEG_SYS_INT_EN__DJRBC_MASK);
328
329 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
330 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
331 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
332 lower_32_bits(ring->gpu_addr));
333 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
334 upper_32_bits(ring->gpu_addr));
335 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);
336 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);
337 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
338 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
339 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
340 }
341
342 return 0;
343}
344
345/**
346 * jpeg_v2_5_stop - stop JPEG block
347 *
348 * @adev: amdgpu_device pointer
349 *
350 * stop the JPEG block
351 */
352static int jpeg_v2_5_stop(struct amdgpu_device *adev)
353{
354 int i;
355
356 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
357 if (adev->jpeg.harvest_config & (1 << i))
358 continue;
359
360 /* reset JMI */
361 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
362 UVD_JMI_CNTL__SOFT_RESET_MASK,
363 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
364
365 jpeg_v2_5_enable_clock_gating(adev, i);
366
367 /* enable anti hang mechanism */
368 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
369 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
370 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
371 }
372
373 return 0;
374}
375
376/**
377 * jpeg_v2_5_dec_ring_get_rptr - get read pointer
378 *
379 * @ring: amdgpu_ring pointer
380 *
381 * Returns the current hardware read pointer
382 */
383static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
384{
385 struct amdgpu_device *adev = ring->adev;
386
387 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR);
388}
389
390/**
391 * jpeg_v2_5_dec_ring_get_wptr - get write pointer
392 *
393 * @ring: amdgpu_ring pointer
394 *
395 * Returns the current hardware write pointer
396 */
397static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
398{
399 struct amdgpu_device *adev = ring->adev;
400
401 if (ring->use_doorbell)
402 return adev->wb.wb[ring->wptr_offs];
403 else
404 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);
405}
406
407/**
408 * jpeg_v2_5_dec_ring_set_wptr - set write pointer
409 *
410 * @ring: amdgpu_ring pointer
411 *
412 * Commits the write pointer to the hardware
413 */
414static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
415{
416 struct amdgpu_device *adev = ring->adev;
417
418 if (ring->use_doorbell) {
419 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
420 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
421 } else {
422 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
423 }
424}
425
426static bool jpeg_v2_5_is_idle(void *handle)
427{
428 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
429 int i, ret = 1;
430
431 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
432 if (adev->jpeg.harvest_config & (1 << i))
433 continue;
434
435 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) &
436 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
437 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
438 }
439
440 return ret;
441}
442
443static int jpeg_v2_5_wait_for_idle(void *handle)
444{
445 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
446 int i, ret;
447
448 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
449 if (adev->jpeg.harvest_config & (1 << i))
450 continue;
451
452 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,
453 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
454 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
455 if (ret)
456 return ret;
457 }
458
459 return 0;
460}
461
462static int jpeg_v2_5_set_clockgating_state(void *handle,
463 enum amd_clockgating_state state)
464{
465 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
466 bool enable = (state == AMD_CG_STATE_GATE);
467 int i;
468
469 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
470 if (adev->jpeg.harvest_config & (1 << i))
471 continue;
472
473 if (enable) {
474 if (!jpeg_v2_5_is_idle(handle))
475 return -EBUSY;
476 jpeg_v2_5_enable_clock_gating(adev, i);
477 } else {
478 jpeg_v2_5_disable_clock_gating(adev, i);
479 }
480 }
481
482 return 0;
483}
484
485static int jpeg_v2_5_set_powergating_state(void *handle,
486 enum amd_powergating_state state)
487{
488 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
489 int ret;
490
491 if(state == adev->jpeg.cur_state)
492 return 0;
493
494 if (state == AMD_PG_STATE_GATE)
495 ret = jpeg_v2_5_stop(adev);
496 else
497 ret = jpeg_v2_5_start(adev);
498
499 if(!ret)
500 adev->jpeg.cur_state = state;
501
502 return ret;
503}
504
505static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev,
506 struct amdgpu_irq_src *source,
507 unsigned type,
508 enum amdgpu_interrupt_state state)
509{
510 return 0;
511}
512
513static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,
514 struct amdgpu_irq_src *source,
515 struct amdgpu_iv_entry *entry)
516{
517 uint32_t ip_instance;
518
519 switch (entry->client_id) {
520 case SOC15_IH_CLIENTID_VCN:
521 ip_instance = 0;
522 break;
523 case SOC15_IH_CLIENTID_VCN1:
524 ip_instance = 1;
525 break;
526 default:
527 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
528 return 0;
529 }
530
531 DRM_DEBUG("IH: JPEG TRAP\n");
532
533 switch (entry->src_id) {
534 case VCN_2_0__SRCID__JPEG_DECODE:
535 amdgpu_fence_process(&adev->jpeg.inst[ip_instance].ring_dec);
536 break;
537 default:
538 DRM_ERROR("Unhandled interrupt: %d %d\n",
539 entry->src_id, entry->src_data[0]);
540 break;
541 }
542
543 return 0;
544}
545
546static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
547 .name = "jpeg_v2_5",
548 .early_init = jpeg_v2_5_early_init,
549 .late_init = NULL,
550 .sw_init = jpeg_v2_5_sw_init,
551 .sw_fini = jpeg_v2_5_sw_fini,
552 .hw_init = jpeg_v2_5_hw_init,
553 .hw_fini = jpeg_v2_5_hw_fini,
554 .suspend = jpeg_v2_5_suspend,
555 .resume = jpeg_v2_5_resume,
556 .is_idle = jpeg_v2_5_is_idle,
557 .wait_for_idle = jpeg_v2_5_wait_for_idle,
558 .check_soft_reset = NULL,
559 .pre_soft_reset = NULL,
560 .soft_reset = NULL,
561 .post_soft_reset = NULL,
562 .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
563 .set_powergating_state = jpeg_v2_5_set_powergating_state,
564};
565
566static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
567 .name = "jpeg_v2_6",
568 .early_init = jpeg_v2_5_early_init,
569 .late_init = NULL,
570 .sw_init = jpeg_v2_5_sw_init,
571 .sw_fini = jpeg_v2_5_sw_fini,
572 .hw_init = jpeg_v2_5_hw_init,
573 .hw_fini = jpeg_v2_5_hw_fini,
574 .suspend = jpeg_v2_5_suspend,
575 .resume = jpeg_v2_5_resume,
576 .is_idle = jpeg_v2_5_is_idle,
577 .wait_for_idle = jpeg_v2_5_wait_for_idle,
578 .check_soft_reset = NULL,
579 .pre_soft_reset = NULL,
580 .soft_reset = NULL,
581 .post_soft_reset = NULL,
582 .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
583 .set_powergating_state = jpeg_v2_5_set_powergating_state,
584};
585
586static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
587 .type = AMDGPU_RING_TYPE_VCN_JPEG,
588 .align_mask = 0xf,
589 .vmhub = AMDGPU_MMHUB_1,
590 .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
591 .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
592 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
593 .emit_frame_size =
594 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
595 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
596 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
597 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
598 8 + 16,
599 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
600 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
601 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
602 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
603 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
604 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
605 .insert_nop = jpeg_v2_0_dec_ring_nop,
606 .insert_start = jpeg_v2_0_dec_ring_insert_start,
607 .insert_end = jpeg_v2_0_dec_ring_insert_end,
608 .pad_ib = amdgpu_ring_generic_pad_ib,
609 .begin_use = amdgpu_jpeg_ring_begin_use,
610 .end_use = amdgpu_jpeg_ring_end_use,
611 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
612 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
613 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
614};
615
616static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {
617 .type = AMDGPU_RING_TYPE_VCN_JPEG,
618 .align_mask = 0xf,
619 .vmhub = AMDGPU_MMHUB_0,
620 .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
621 .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
622 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
623 .emit_frame_size =
624 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
625 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
626 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
627 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
628 8 + 16,
629 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
630 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
631 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
632 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
633 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
634 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
635 .insert_nop = jpeg_v2_0_dec_ring_nop,
636 .insert_start = jpeg_v2_0_dec_ring_insert_start,
637 .insert_end = jpeg_v2_0_dec_ring_insert_end,
638 .pad_ib = amdgpu_ring_generic_pad_ib,
639 .begin_use = amdgpu_jpeg_ring_begin_use,
640 .end_use = amdgpu_jpeg_ring_end_use,
641 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
642 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
643 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
644};
645
646static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
647{
648 int i;
649
650 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
651 if (adev->jpeg.harvest_config & (1 << i))
652 continue;
653 if (adev->asic_type == CHIP_ARCTURUS)
654 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs;
655 else /* CHIP_ALDEBARAN */
656 adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_6_dec_ring_vm_funcs;
657 adev->jpeg.inst[i].ring_dec.me = i;
658 DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i);
659 }
660}
661
662static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = {
663 .set = jpeg_v2_5_set_interrupt_state,
664 .process = jpeg_v2_5_process_interrupt,
665};
666
667static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev)
668{
669 int i;
670
671 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
672 if (adev->jpeg.harvest_config & (1 << i))
673 continue;
674
675 adev->jpeg.inst[i].irq.num_types = 1;
676 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;
677 }
678}
679
680const struct amdgpu_ip_block_version jpeg_v2_5_ip_block =
681{
682 .type = AMD_IP_BLOCK_TYPE_JPEG,
683 .major = 2,
684 .minor = 5,
685 .rev = 0,
686 .funcs = &jpeg_v2_5_ip_funcs,
687};
688
689const struct amdgpu_ip_block_version jpeg_v2_6_ip_block =
690{
691 .type = AMD_IP_BLOCK_TYPE_JPEG,
692 .major = 2,
693 .minor = 6,
694 .rev = 0,
695 .funcs = &jpeg_v2_6_ip_funcs,
696};