1/*
   2 * Copyright 2007-8 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: Dave Airlie
  24 *          Alex Deucher
  25 */
  26#include <drm/drmP.h>
  27#include <drm/drm_edid.h>
  28#include <drm/drm_crtc_helper.h>
  29#include <drm/drm_fb_helper.h>
 
 
  30#include <drm/amdgpu_drm.h>
  31#include "amdgpu.h"
  32#include "atom.h"
  33#include "atombios_encoders.h"
  34#include "atombios_dp.h"
  35#include "amdgpu_connectors.h"
  36#include "amdgpu_i2c.h"
 
  37
  38#include <linux/pm_runtime.h>
  39
  40void amdgpu_connector_hotplug(struct drm_connector *connector)
  41{
  42	struct drm_device *dev = connector->dev;
  43	struct amdgpu_device *adev = dev->dev_private;
  44	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  45
  46	/* bail if the connector does not have hpd pin, e.g.,
  47	 * VGA, TV, etc.
  48	 */
  49	if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE)
  50		return;
  51
  52	amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  53
  54	/* if the connector is already off, don't turn it back on */
  55	if (connector->dpms != DRM_MODE_DPMS_ON)
  56		return;
  57
  58	/* just deal with DP (not eDP) here. */
  59	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
  60		struct amdgpu_connector_atom_dig *dig_connector =
  61			amdgpu_connector->con_priv;
  62
  63		/* if existing sink type was not DP no need to retrain */
  64		if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT)
  65			return;
  66
  67		/* first get sink type as it may be reset after (un)plug */
  68		dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
  69		/* don't do anything if sink is not display port, i.e.,
  70		 * passive dp->(dvi|hdmi) adaptor
  71		 */
  72		if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT &&
  73		    amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) &&
  74		    amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
  75			/* Don't start link training before we have the DPCD */
  76			if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
  77				return;
  78
  79			/* Turn the connector off and back on immediately, which
  80			 * will trigger link training
  81			 */
  82			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
  83			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
  84		}
  85	}
  86}
  87
  88static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder)
  89{
  90	struct drm_crtc *crtc = encoder->crtc;
  91
  92	if (crtc && crtc->enabled) {
  93		drm_crtc_helper_set_mode(crtc, &crtc->mode,
  94					 crtc->x, crtc->y, crtc->primary->fb);
  95	}
  96}
  97
  98int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
  99{
 100	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 101	struct amdgpu_connector_atom_dig *dig_connector;
 102	int bpc = 8;
 103	unsigned mode_clock, max_tmds_clock;
 104
 105	switch (connector->connector_type) {
 106	case DRM_MODE_CONNECTOR_DVII:
 107	case DRM_MODE_CONNECTOR_HDMIB:
 108		if (amdgpu_connector->use_digital) {
 109			if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 110				if (connector->display_info.bpc)
 111					bpc = connector->display_info.bpc;
 112			}
 113		}
 114		break;
 115	case DRM_MODE_CONNECTOR_DVID:
 116	case DRM_MODE_CONNECTOR_HDMIA:
 117		if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 118			if (connector->display_info.bpc)
 119				bpc = connector->display_info.bpc;
 120		}
 121		break;
 122	case DRM_MODE_CONNECTOR_DisplayPort:
 123		dig_connector = amdgpu_connector->con_priv;
 124		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 125		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) ||
 126		    drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 127			if (connector->display_info.bpc)
 128				bpc = connector->display_info.bpc;
 129		}
 130		break;
 131	case DRM_MODE_CONNECTOR_eDP:
 132	case DRM_MODE_CONNECTOR_LVDS:
 133		if (connector->display_info.bpc)
 134			bpc = connector->display_info.bpc;
 135		else {
 136			const struct drm_connector_helper_funcs *connector_funcs =
 137				connector->helper_private;
 138			struct drm_encoder *encoder = connector_funcs->best_encoder(connector);
 139			struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 140			struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
 141
 142			if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR)
 143				bpc = 6;
 144			else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR)
 145				bpc = 8;
 146		}
 147		break;
 148	}
 149
 150	if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
 151		/*
 152		 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make
 153		 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at
 154		 * 12 bpc is always supported on hdmi deep color sinks, as this is
 155		 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum.
 156		 */
 157		if (bpc > 12) {
 158			DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n",
 159				  connector->name, bpc);
 160			bpc = 12;
 161		}
 162
 163		/* Any defined maximum tmds clock limit we must not exceed? */
 164		if (connector->display_info.max_tmds_clock > 0) {
 165			/* mode_clock is clock in kHz for mode to be modeset on this connector */
 166			mode_clock = amdgpu_connector->pixelclock_for_modeset;
 167
 168			/* Maximum allowable input clock in kHz */
 169			max_tmds_clock = connector->display_info.max_tmds_clock;
 170
 171			DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n",
 172				  connector->name, mode_clock, max_tmds_clock);
 173
 174			/* Check if bpc is within clock limit. Try to degrade gracefully otherwise */
 175			if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) {
 176				if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) &&
 177				    (mode_clock * 5/4 <= max_tmds_clock))
 178					bpc = 10;
 179				else
 180					bpc = 8;
 181
 182				DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n",
 183					  connector->name, bpc);
 184			}
 185
 186			if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) {
 187				bpc = 8;
 188				DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
 189					  connector->name, bpc);
 190			}
 191		} else if (bpc > 8) {
 192			/* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
 193			DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
 194				  connector->name);
 195			bpc = 8;
 196		}
 197	}
 198
 199	if ((amdgpu_deep_color == 0) && (bpc > 8)) {
 200		DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",
 201			  connector->name);
 202		bpc = 8;
 203	}
 204
 205	DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n",
 206		  connector->name, connector->display_info.bpc, bpc);
 207
 208	return bpc;
 209}
 210
 211static void
 212amdgpu_connector_update_scratch_regs(struct drm_connector *connector,
 213				      enum drm_connector_status status)
 214{
 215	struct drm_encoder *best_encoder = NULL;
 216	struct drm_encoder *encoder = NULL;
 217	const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 218	bool connected;
 219	int i;
 220
 221	best_encoder = connector_funcs->best_encoder(connector);
 222
 223	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 224		if (connector->encoder_ids[i] == 0)
 225			break;
 226
 227		encoder = drm_encoder_find(connector->dev, NULL,
 228					connector->encoder_ids[i]);
 229		if (!encoder)
 230			continue;
 231
 232		if ((encoder == best_encoder) && (status == connector_status_connected))
 233			connected = true;
 234		else
 235			connected = false;
 236
 237		amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected);
 238
 239	}
 240}
 241
 242static struct drm_encoder *
 243amdgpu_connector_find_encoder(struct drm_connector *connector,
 244			       int encoder_type)
 245{
 246	struct drm_encoder *encoder;
 247	int i;
 248
 249	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 250		if (connector->encoder_ids[i] == 0)
 251			break;
 252		encoder = drm_encoder_find(connector->dev, NULL,
 253					connector->encoder_ids[i]);
 254		if (!encoder)
 255			continue;
 256
 
 257		if (encoder->encoder_type == encoder_type)
 258			return encoder;
 259	}
 
 260	return NULL;
 261}
 262
 263struct edid *amdgpu_connector_edid(struct drm_connector *connector)
 264{
 265	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 266	struct drm_property_blob *edid_blob = connector->edid_blob_ptr;
 267
 268	if (amdgpu_connector->edid) {
 269		return amdgpu_connector->edid;
 270	} else if (edid_blob) {
 271		struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL);
 272		if (edid)
 273			amdgpu_connector->edid = edid;
 274	}
 275	return amdgpu_connector->edid;
 276}
 277
 278static struct edid *
 279amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev)
 280{
 281	struct edid *edid;
 282
 283	if (adev->mode_info.bios_hardcoded_edid) {
 284		edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
 285		if (edid) {
 286			memcpy((unsigned char *)edid,
 287			       (unsigned char *)adev->mode_info.bios_hardcoded_edid,
 288			       adev->mode_info.bios_hardcoded_edid_size);
 289			return edid;
 290		}
 291	}
 292	return NULL;
 293}
 294
 295static void amdgpu_connector_get_edid(struct drm_connector *connector)
 296{
 297	struct drm_device *dev = connector->dev;
 298	struct amdgpu_device *adev = dev->dev_private;
 299	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 300
 301	if (amdgpu_connector->edid)
 302		return;
 303
 304	/* on hw with routers, select right port */
 305	if (amdgpu_connector->router.ddc_valid)
 306		amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
 307
 308	if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
 309	     ENCODER_OBJECT_ID_NONE) &&
 310	    amdgpu_connector->ddc_bus->has_aux) {
 311		amdgpu_connector->edid = drm_get_edid(connector,
 312						      &amdgpu_connector->ddc_bus->aux.ddc);
 313	} else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 314		   (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
 315		struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
 316
 317		if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 318		     dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 319		    amdgpu_connector->ddc_bus->has_aux)
 320			amdgpu_connector->edid = drm_get_edid(connector,
 321							      &amdgpu_connector->ddc_bus->aux.ddc);
 322		else if (amdgpu_connector->ddc_bus)
 323			amdgpu_connector->edid = drm_get_edid(connector,
 324							      &amdgpu_connector->ddc_bus->adapter);
 325	} else if (amdgpu_connector->ddc_bus) {
 326		amdgpu_connector->edid = drm_get_edid(connector,
 327						      &amdgpu_connector->ddc_bus->adapter);
 328	}
 329
 330	if (!amdgpu_connector->edid) {
 331		/* some laptops provide a hardcoded edid in rom for LCDs */
 332		if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 333		     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)))
 334			amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev);
 335	}
 336}
 337
 338static void amdgpu_connector_free_edid(struct drm_connector *connector)
 339{
 340	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 341
 342	kfree(amdgpu_connector->edid);
 343	amdgpu_connector->edid = NULL;
 344}
 345
 346static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector)
 347{
 348	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 349	int ret;
 350
 351	if (amdgpu_connector->edid) {
 352		drm_mode_connector_update_edid_property(connector, amdgpu_connector->edid);
 353		ret = drm_add_edid_modes(connector, amdgpu_connector->edid);
 354		return ret;
 355	}
 356	drm_mode_connector_update_edid_property(connector, NULL);
 357	return 0;
 358}
 359
 360static struct drm_encoder *
 361amdgpu_connector_best_single_encoder(struct drm_connector *connector)
 362{
 363	int enc_id = connector->encoder_ids[0];
 
 
 
 
 364
 365	/* pick the encoder ids */
 366	if (enc_id)
 367		return drm_encoder_find(connector->dev, NULL, enc_id);
 368	return NULL;
 369}
 370
 371static void amdgpu_get_native_mode(struct drm_connector *connector)
 372{
 373	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 374	struct amdgpu_encoder *amdgpu_encoder;
 375
 376	if (encoder == NULL)
 377		return;
 378
 379	amdgpu_encoder = to_amdgpu_encoder(encoder);
 380
 381	if (!list_empty(&connector->probed_modes)) {
 382		struct drm_display_mode *preferred_mode =
 383			list_first_entry(&connector->probed_modes,
 384					 struct drm_display_mode, head);
 385
 386		amdgpu_encoder->native_mode = *preferred_mode;
 387	} else {
 388		amdgpu_encoder->native_mode.clock = 0;
 389	}
 390}
 391
 392static struct drm_display_mode *
 393amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder)
 394{
 395	struct drm_device *dev = encoder->dev;
 396	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 397	struct drm_display_mode *mode = NULL;
 398	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 399
 400	if (native_mode->hdisplay != 0 &&
 401	    native_mode->vdisplay != 0 &&
 402	    native_mode->clock != 0) {
 403		mode = drm_mode_duplicate(dev, native_mode);
 404		mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 405		drm_mode_set_name(mode);
 406
 407		DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name);
 408	} else if (native_mode->hdisplay != 0 &&
 409		   native_mode->vdisplay != 0) {
 410		/* mac laptops without an edid */
 411		/* Note that this is not necessarily the exact panel mode,
 412		 * but an approximation based on the cvt formula.  For these
 413		 * systems we should ideally read the mode info out of the
 414		 * registers or add a mode table, but this works and is much
 415		 * simpler.
 416		 */
 417		mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false);
 418		mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
 419		DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name);
 420	}
 421	return mode;
 422}
 423
 424static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder,
 425					       struct drm_connector *connector)
 426{
 427	struct drm_device *dev = encoder->dev;
 428	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 429	struct drm_display_mode *mode = NULL;
 430	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 431	int i;
 432	static const struct mode_size {
 433		int w;
 434		int h;
 435	} common_modes[17] = {
 436		{ 640,  480},
 437		{ 720,  480},
 438		{ 800,  600},
 439		{ 848,  480},
 440		{1024,  768},
 441		{1152,  768},
 442		{1280,  720},
 443		{1280,  800},
 444		{1280,  854},
 445		{1280,  960},
 446		{1280, 1024},
 447		{1440,  900},
 448		{1400, 1050},
 449		{1680, 1050},
 450		{1600, 1200},
 451		{1920, 1080},
 452		{1920, 1200}
 453	};
 454
 455	for (i = 0; i < 17; i++) {
 456		if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
 457			if (common_modes[i].w > 1024 ||
 458			    common_modes[i].h > 768)
 459				continue;
 460		}
 461		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 462			if (common_modes[i].w > native_mode->hdisplay ||
 463			    common_modes[i].h > native_mode->vdisplay ||
 464			    (common_modes[i].w == native_mode->hdisplay &&
 465			     common_modes[i].h == native_mode->vdisplay))
 466				continue;
 467		}
 468		if (common_modes[i].w < 320 || common_modes[i].h < 200)
 469			continue;
 470
 471		mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 472		drm_mode_probed_add(connector, mode);
 473	}
 474}
 475
 476static int amdgpu_connector_set_property(struct drm_connector *connector,
 477					  struct drm_property *property,
 478					  uint64_t val)
 479{
 480	struct drm_device *dev = connector->dev;
 481	struct amdgpu_device *adev = dev->dev_private;
 482	struct drm_encoder *encoder;
 483	struct amdgpu_encoder *amdgpu_encoder;
 484
 485	if (property == adev->mode_info.coherent_mode_property) {
 486		struct amdgpu_encoder_atom_dig *dig;
 487		bool new_coherent_mode;
 488
 489		/* need to find digital encoder on connector */
 490		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 491		if (!encoder)
 492			return 0;
 493
 494		amdgpu_encoder = to_amdgpu_encoder(encoder);
 495
 496		if (!amdgpu_encoder->enc_priv)
 497			return 0;
 498
 499		dig = amdgpu_encoder->enc_priv;
 500		new_coherent_mode = val ? true : false;
 501		if (dig->coherent_mode != new_coherent_mode) {
 502			dig->coherent_mode = new_coherent_mode;
 503			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 504		}
 505	}
 506
 507	if (property == adev->mode_info.audio_property) {
 508		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 509		/* need to find digital encoder on connector */
 510		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 511		if (!encoder)
 512			return 0;
 513
 514		amdgpu_encoder = to_amdgpu_encoder(encoder);
 515
 516		if (amdgpu_connector->audio != val) {
 517			amdgpu_connector->audio = val;
 518			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 519		}
 520	}
 521
 522	if (property == adev->mode_info.dither_property) {
 523		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 524		/* need to find digital encoder on connector */
 525		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 526		if (!encoder)
 527			return 0;
 528
 529		amdgpu_encoder = to_amdgpu_encoder(encoder);
 530
 531		if (amdgpu_connector->dither != val) {
 532			amdgpu_connector->dither = val;
 533			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 534		}
 535	}
 536
 537	if (property == adev->mode_info.underscan_property) {
 538		/* need to find digital encoder on connector */
 539		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 540		if (!encoder)
 541			return 0;
 542
 543		amdgpu_encoder = to_amdgpu_encoder(encoder);
 544
 545		if (amdgpu_encoder->underscan_type != val) {
 546			amdgpu_encoder->underscan_type = val;
 547			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 548		}
 549	}
 550
 551	if (property == adev->mode_info.underscan_hborder_property) {
 552		/* need to find digital encoder on connector */
 553		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 554		if (!encoder)
 555			return 0;
 556
 557		amdgpu_encoder = to_amdgpu_encoder(encoder);
 558
 559		if (amdgpu_encoder->underscan_hborder != val) {
 560			amdgpu_encoder->underscan_hborder = val;
 561			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 562		}
 563	}
 564
 565	if (property == adev->mode_info.underscan_vborder_property) {
 566		/* need to find digital encoder on connector */
 567		encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS);
 568		if (!encoder)
 569			return 0;
 570
 571		amdgpu_encoder = to_amdgpu_encoder(encoder);
 572
 573		if (amdgpu_encoder->underscan_vborder != val) {
 574			amdgpu_encoder->underscan_vborder = val;
 575			amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 576		}
 577	}
 578
 579	if (property == adev->mode_info.load_detect_property) {
 580		struct amdgpu_connector *amdgpu_connector =
 581			to_amdgpu_connector(connector);
 582
 583		if (val == 0)
 584			amdgpu_connector->dac_load_detect = false;
 585		else
 586			amdgpu_connector->dac_load_detect = true;
 587	}
 588
 589	if (property == dev->mode_config.scaling_mode_property) {
 590		enum amdgpu_rmx_type rmx_type;
 591
 592		if (connector->encoder) {
 593			amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 594		} else {
 595			const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 596			amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 597		}
 598
 599		switch (val) {
 600		default:
 601		case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 602		case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 603		case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 604		case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 605		}
 606		if (amdgpu_encoder->rmx_type == rmx_type)
 607			return 0;
 608
 609		if ((rmx_type != DRM_MODE_SCALE_NONE) &&
 610		    (amdgpu_encoder->native_mode.clock == 0))
 611			return 0;
 612
 613		amdgpu_encoder->rmx_type = rmx_type;
 614
 615		amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 616	}
 617
 618	return 0;
 619}
 620
 621static void
 622amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder,
 623					struct drm_connector *connector)
 624{
 625	struct amdgpu_encoder *amdgpu_encoder =	to_amdgpu_encoder(encoder);
 626	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 627	struct drm_display_mode *t, *mode;
 628
 629	/* If the EDID preferred mode doesn't match the native mode, use it */
 630	list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 631		if (mode->type & DRM_MODE_TYPE_PREFERRED) {
 632			if (mode->hdisplay != native_mode->hdisplay ||
 633			    mode->vdisplay != native_mode->vdisplay)
 634				memcpy(native_mode, mode, sizeof(*mode));
 635		}
 636	}
 637
 638	/* Try to get native mode details from EDID if necessary */
 639	if (!native_mode->clock) {
 640		list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
 641			if (mode->hdisplay == native_mode->hdisplay &&
 642			    mode->vdisplay == native_mode->vdisplay) {
 643				*native_mode = *mode;
 644				drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
 645				DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
 646				break;
 647			}
 648		}
 649	}
 650
 651	if (!native_mode->clock) {
 652		DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
 653		amdgpu_encoder->rmx_type = RMX_OFF;
 654	}
 655}
 656
 657static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector)
 658{
 659	struct drm_encoder *encoder;
 660	int ret = 0;
 661	struct drm_display_mode *mode;
 662
 663	amdgpu_connector_get_edid(connector);
 664	ret = amdgpu_connector_ddc_get_modes(connector);
 665	if (ret > 0) {
 666		encoder = amdgpu_connector_best_single_encoder(connector);
 667		if (encoder) {
 668			amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
 669			/* add scaled modes */
 670			amdgpu_connector_add_common_modes(encoder, connector);
 671		}
 672		return ret;
 673	}
 674
 675	encoder = amdgpu_connector_best_single_encoder(connector);
 676	if (!encoder)
 677		return 0;
 678
 679	/* we have no EDID modes */
 680	mode = amdgpu_connector_lcd_native_mode(encoder);
 681	if (mode) {
 682		ret = 1;
 683		drm_mode_probed_add(connector, mode);
 684		/* add the width/height from vbios tables if available */
 685		connector->display_info.width_mm = mode->width_mm;
 686		connector->display_info.height_mm = mode->height_mm;
 687		/* add scaled modes */
 688		amdgpu_connector_add_common_modes(encoder, connector);
 689	}
 690
 691	return ret;
 692}
 693
 694static int amdgpu_connector_lvds_mode_valid(struct drm_connector *connector,
 695					     struct drm_display_mode *mode)
 696{
 697	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 698
 699	if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
 700		return MODE_PANEL;
 701
 702	if (encoder) {
 703		struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 704		struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 705
 706		/* AVIVO hardware supports downscaling modes larger than the panel
 707		 * to the panel size, but I'm not sure this is desirable.
 708		 */
 709		if ((mode->hdisplay > native_mode->hdisplay) ||
 710		    (mode->vdisplay > native_mode->vdisplay))
 711			return MODE_PANEL;
 712
 713		/* if scaling is disabled, block non-native modes */
 714		if (amdgpu_encoder->rmx_type == RMX_OFF) {
 715			if ((mode->hdisplay != native_mode->hdisplay) ||
 716			    (mode->vdisplay != native_mode->vdisplay))
 717				return MODE_PANEL;
 718		}
 719	}
 720
 721	return MODE_OK;
 722}
 723
 724static enum drm_connector_status
 725amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force)
 726{
 727	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 728	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
 729	enum drm_connector_status ret = connector_status_disconnected;
 730	int r;
 731
 732	if (!drm_kms_helper_is_poll_worker()) {
 733		r = pm_runtime_get_sync(connector->dev->dev);
 734		if (r < 0)
 
 735			return connector_status_disconnected;
 
 736	}
 737
 738	if (encoder) {
 739		struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
 740		struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
 741
 742		/* check if panel is valid */
 743		if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
 744			ret = connector_status_connected;
 745
 746	}
 747
 748	/* check for edid as well */
 749	amdgpu_connector_get_edid(connector);
 750	if (amdgpu_connector->edid)
 751		ret = connector_status_connected;
 752	/* check acpi lid status ??? */
 753
 754	amdgpu_connector_update_scratch_regs(connector, ret);
 755
 756	if (!drm_kms_helper_is_poll_worker()) {
 757		pm_runtime_mark_last_busy(connector->dev->dev);
 758		pm_runtime_put_autosuspend(connector->dev->dev);
 759	}
 760
 761	return ret;
 762}
 763
 764static void amdgpu_connector_unregister(struct drm_connector *connector)
 765{
 766	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 767
 768	if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) {
 769		drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux);
 770		amdgpu_connector->ddc_bus->has_aux = false;
 771	}
 772}
 773
 774static void amdgpu_connector_destroy(struct drm_connector *connector)
 775{
 776	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 777
 778	amdgpu_connector_free_edid(connector);
 779	kfree(amdgpu_connector->con_priv);
 780	drm_connector_unregister(connector);
 781	drm_connector_cleanup(connector);
 782	kfree(connector);
 783}
 784
 785static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 786					      struct drm_property *property,
 787					      uint64_t value)
 788{
 789	struct drm_device *dev = connector->dev;
 790	struct amdgpu_encoder *amdgpu_encoder;
 791	enum amdgpu_rmx_type rmx_type;
 792
 793	DRM_DEBUG_KMS("\n");
 794	if (property != dev->mode_config.scaling_mode_property)
 795		return 0;
 796
 797	if (connector->encoder)
 798		amdgpu_encoder = to_amdgpu_encoder(connector->encoder);
 799	else {
 800		const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
 801		amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector));
 802	}
 803
 804	switch (value) {
 805	case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
 806	case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
 807	case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
 808	default:
 809	case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
 810	}
 811	if (amdgpu_encoder->rmx_type == rmx_type)
 812		return 0;
 813
 814	amdgpu_encoder->rmx_type = rmx_type;
 815
 816	amdgpu_connector_property_change_mode(&amdgpu_encoder->base);
 817	return 0;
 818}
 819
 820
 821static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = {
 822	.get_modes = amdgpu_connector_lvds_get_modes,
 823	.mode_valid = amdgpu_connector_lvds_mode_valid,
 824	.best_encoder = amdgpu_connector_best_single_encoder,
 825};
 826
 827static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = {
 828	.dpms = drm_helper_connector_dpms,
 829	.detect = amdgpu_connector_lvds_detect,
 830	.fill_modes = drm_helper_probe_single_connector_modes,
 831	.early_unregister = amdgpu_connector_unregister,
 832	.destroy = amdgpu_connector_destroy,
 833	.set_property = amdgpu_connector_set_lcd_property,
 834};
 835
 836static int amdgpu_connector_vga_get_modes(struct drm_connector *connector)
 837{
 838	int ret;
 839
 840	amdgpu_connector_get_edid(connector);
 841	ret = amdgpu_connector_ddc_get_modes(connector);
 842
 843	return ret;
 844}
 845
 846static int amdgpu_connector_vga_mode_valid(struct drm_connector *connector,
 847					    struct drm_display_mode *mode)
 848{
 849	struct drm_device *dev = connector->dev;
 850	struct amdgpu_device *adev = dev->dev_private;
 851
 852	/* XXX check mode bandwidth */
 853
 854	if ((mode->clock / 10) > adev->clock.max_pixel_clock)
 855		return MODE_CLOCK_HIGH;
 856
 857	return MODE_OK;
 858}
 859
 860static enum drm_connector_status
 861amdgpu_connector_vga_detect(struct drm_connector *connector, bool force)
 862{
 863	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 864	struct drm_encoder *encoder;
 865	const struct drm_encoder_helper_funcs *encoder_funcs;
 866	bool dret = false;
 867	enum drm_connector_status ret = connector_status_disconnected;
 868	int r;
 869
 870	if (!drm_kms_helper_is_poll_worker()) {
 871		r = pm_runtime_get_sync(connector->dev->dev);
 872		if (r < 0)
 
 873			return connector_status_disconnected;
 
 874	}
 875
 876	encoder = amdgpu_connector_best_single_encoder(connector);
 877	if (!encoder)
 878		ret = connector_status_disconnected;
 879
 880	if (amdgpu_connector->ddc_bus)
 881		dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
 882	if (dret) {
 883		amdgpu_connector->detected_by_load = false;
 884		amdgpu_connector_free_edid(connector);
 885		amdgpu_connector_get_edid(connector);
 886
 887		if (!amdgpu_connector->edid) {
 888			DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
 889					connector->name);
 890			ret = connector_status_connected;
 891		} else {
 892			amdgpu_connector->use_digital =
 893				!!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
 894
 895			/* some oems have boards with separate digital and analog connectors
 896			 * with a shared ddc line (often vga + hdmi)
 897			 */
 898			if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) {
 899				amdgpu_connector_free_edid(connector);
 900				ret = connector_status_disconnected;
 901			} else {
 902				ret = connector_status_connected;
 903			}
 904		}
 905	} else {
 906
 907		/* if we aren't forcing don't do destructive polling */
 908		if (!force) {
 909			/* only return the previous status if we last
 910			 * detected a monitor via load.
 911			 */
 912			if (amdgpu_connector->detected_by_load)
 913				ret = connector->status;
 914			goto out;
 915		}
 916
 917		if (amdgpu_connector->dac_load_detect && encoder) {
 918			encoder_funcs = encoder->helper_private;
 919			ret = encoder_funcs->detect(encoder, connector);
 920			if (ret != connector_status_disconnected)
 921				amdgpu_connector->detected_by_load = true;
 922		}
 923	}
 924
 925	amdgpu_connector_update_scratch_regs(connector, ret);
 926
 927out:
 928	if (!drm_kms_helper_is_poll_worker()) {
 929		pm_runtime_mark_last_busy(connector->dev->dev);
 930		pm_runtime_put_autosuspend(connector->dev->dev);
 931	}
 932
 933	return ret;
 934}
 935
 936static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = {
 937	.get_modes = amdgpu_connector_vga_get_modes,
 938	.mode_valid = amdgpu_connector_vga_mode_valid,
 939	.best_encoder = amdgpu_connector_best_single_encoder,
 940};
 941
 942static const struct drm_connector_funcs amdgpu_connector_vga_funcs = {
 943	.dpms = drm_helper_connector_dpms,
 944	.detect = amdgpu_connector_vga_detect,
 945	.fill_modes = drm_helper_probe_single_connector_modes,
 946	.early_unregister = amdgpu_connector_unregister,
 947	.destroy = amdgpu_connector_destroy,
 948	.set_property = amdgpu_connector_set_property,
 949};
 950
 951static bool
 952amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector)
 953{
 954	struct drm_device *dev = connector->dev;
 955	struct amdgpu_device *adev = dev->dev_private;
 956	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 957	enum drm_connector_status status;
 958
 959	if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) {
 960		if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd))
 961			status = connector_status_connected;
 962		else
 963			status = connector_status_disconnected;
 964		if (connector->status == status)
 965			return true;
 966	}
 967
 968	return false;
 969}
 970
 971/*
 972 * DVI is complicated
 973 * Do a DDC probe, if DDC probe passes, get the full EDID so
 974 * we can do analog/digital monitor detection at this point.
 975 * If the monitor is an analog monitor or we got no DDC,
 976 * we need to find the DAC encoder object for this connector.
 977 * If we got no DDC, we do load detection on the DAC encoder object.
 978 * If we got analog DDC or load detection passes on the DAC encoder
 979 * we have to check if this analog encoder is shared with anyone else (TV)
 980 * if its shared we have to set the other connector to disconnected.
 981 */
 982static enum drm_connector_status
 983amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
 984{
 985	struct drm_device *dev = connector->dev;
 986	struct amdgpu_device *adev = dev->dev_private;
 987	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 988	struct drm_encoder *encoder = NULL;
 989	const struct drm_encoder_helper_funcs *encoder_funcs;
 990	int i, r;
 991	enum drm_connector_status ret = connector_status_disconnected;
 992	bool dret = false, broken_edid = false;
 993
 994	if (!drm_kms_helper_is_poll_worker()) {
 995		r = pm_runtime_get_sync(connector->dev->dev);
 996		if (r < 0)
 
 997			return connector_status_disconnected;
 
 998	}
 999
1000	if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1001		ret = connector->status;
1002		goto exit;
1003	}
1004
1005	if (amdgpu_connector->ddc_bus)
1006		dret = amdgpu_display_ddc_probe(amdgpu_connector, false);
1007	if (dret) {
1008		amdgpu_connector->detected_by_load = false;
1009		amdgpu_connector_free_edid(connector);
1010		amdgpu_connector_get_edid(connector);
1011
1012		if (!amdgpu_connector->edid) {
1013			DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
1014					connector->name);
1015			ret = connector_status_connected;
1016			broken_edid = true; /* defer use_digital to later */
1017		} else {
1018			amdgpu_connector->use_digital =
1019				!!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
1020
1021			/* some oems have boards with separate digital and analog connectors
1022			 * with a shared ddc line (often vga + hdmi)
1023			 */
1024			if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) {
1025				amdgpu_connector_free_edid(connector);
1026				ret = connector_status_disconnected;
1027			} else {
1028				ret = connector_status_connected;
1029			}
1030
1031			/* This gets complicated.  We have boards with VGA + HDMI with a
1032			 * shared DDC line and we have boards with DVI-D + HDMI with a shared
1033			 * DDC line.  The latter is more complex because with DVI<->HDMI adapters
1034			 * you don't really know what's connected to which port as both are digital.
1035			 */
1036			if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) {
1037				struct drm_connector *list_connector;
 
1038				struct amdgpu_connector *list_amdgpu_connector;
1039				list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
 
 
 
1040					if (connector == list_connector)
1041						continue;
1042					list_amdgpu_connector = to_amdgpu_connector(list_connector);
1043					if (list_amdgpu_connector->shared_ddc &&
1044					    (list_amdgpu_connector->ddc_bus->rec.i2c_id ==
1045					     amdgpu_connector->ddc_bus->rec.i2c_id)) {
1046						/* cases where both connectors are digital */
1047						if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
1048							/* hpd is our only option in this case */
1049							if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1050								amdgpu_connector_free_edid(connector);
1051								ret = connector_status_disconnected;
1052							}
1053						}
1054					}
1055				}
 
1056			}
1057		}
1058	}
1059
1060	if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true))
1061		goto out;
1062
1063	/* DVI-D and HDMI-A are digital only */
1064	if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) ||
1065	    (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))
1066		goto out;
1067
1068	/* if we aren't forcing don't do destructive polling */
1069	if (!force) {
1070		/* only return the previous status if we last
1071		 * detected a monitor via load.
1072		 */
1073		if (amdgpu_connector->detected_by_load)
1074			ret = connector->status;
1075		goto out;
1076	}
1077
1078	/* find analog encoder */
1079	if (amdgpu_connector->dac_load_detect) {
1080		for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1081			if (connector->encoder_ids[i] == 0)
1082				break;
1083
1084			encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
1085			if (!encoder)
1086				continue;
1087
 
1088			if (encoder->encoder_type != DRM_MODE_ENCODER_DAC &&
1089			    encoder->encoder_type != DRM_MODE_ENCODER_TVDAC)
1090				continue;
1091
1092			encoder_funcs = encoder->helper_private;
1093			if (encoder_funcs->detect) {
1094				if (!broken_edid) {
1095					if (ret != connector_status_connected) {
1096						/* deal with analog monitors without DDC */
1097						ret = encoder_funcs->detect(encoder, connector);
1098						if (ret == connector_status_connected) {
1099							amdgpu_connector->use_digital = false;
1100						}
1101						if (ret != connector_status_disconnected)
1102							amdgpu_connector->detected_by_load = true;
1103					}
1104				} else {
1105					enum drm_connector_status lret;
1106					/* assume digital unless load detected otherwise */
1107					amdgpu_connector->use_digital = true;
1108					lret = encoder_funcs->detect(encoder, connector);
1109					DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
1110					if (lret == connector_status_connected)
1111						amdgpu_connector->use_digital = false;
1112				}
1113				break;
1114			}
1115		}
1116	}
1117
1118out:
1119	/* updated in get modes as well since we need to know if it's analog or digital */
1120	amdgpu_connector_update_scratch_regs(connector, ret);
1121
1122exit:
1123	if (!drm_kms_helper_is_poll_worker()) {
1124		pm_runtime_mark_last_busy(connector->dev->dev);
1125		pm_runtime_put_autosuspend(connector->dev->dev);
1126	}
1127
1128	return ret;
1129}
1130
1131/* okay need to be smart in here about which encoder to pick */
1132static struct drm_encoder *
1133amdgpu_connector_dvi_encoder(struct drm_connector *connector)
1134{
1135	int enc_id = connector->encoder_ids[0];
1136	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1137	struct drm_encoder *encoder;
1138	int i;
1139	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1140		if (connector->encoder_ids[i] == 0)
1141			break;
1142
1143		encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
1144		if (!encoder)
1145			continue;
1146
 
1147		if (amdgpu_connector->use_digital == true) {
1148			if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1149				return encoder;
1150		} else {
1151			if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
1152			    encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1153				return encoder;
1154		}
1155	}
1156
1157	/* see if we have a default encoder  TODO */
1158
1159	/* then check use digitial */
1160	/* pick the first one */
1161	if (enc_id)
1162		return drm_encoder_find(connector->dev, NULL, enc_id);
 
1163	return NULL;
1164}
1165
1166static void amdgpu_connector_dvi_force(struct drm_connector *connector)
1167{
1168	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1169	if (connector->force == DRM_FORCE_ON)
1170		amdgpu_connector->use_digital = false;
1171	if (connector->force == DRM_FORCE_ON_DIGITAL)
1172		amdgpu_connector->use_digital = true;
1173}
1174
1175static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector,
1176					    struct drm_display_mode *mode)
1177{
1178	struct drm_device *dev = connector->dev;
1179	struct amdgpu_device *adev = dev->dev_private;
1180	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1181
1182	/* XXX check mode bandwidth */
1183
1184	if (amdgpu_connector->use_digital && (mode->clock > 165000)) {
1185		if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
1186		    (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
1187		    (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) {
1188			return MODE_OK;
1189		} else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1190			/* HDMI 1.3+ supports max clock of 340 Mhz */
1191			if (mode->clock > 340000)
1192				return MODE_CLOCK_HIGH;
1193			else
1194				return MODE_OK;
1195		} else {
1196			return MODE_CLOCK_HIGH;
1197		}
1198	}
1199
1200	/* check against the max pixel clock */
1201	if ((mode->clock / 10) > adev->clock.max_pixel_clock)
1202		return MODE_CLOCK_HIGH;
1203
1204	return MODE_OK;
1205}
1206
1207static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = {
1208	.get_modes = amdgpu_connector_vga_get_modes,
1209	.mode_valid = amdgpu_connector_dvi_mode_valid,
1210	.best_encoder = amdgpu_connector_dvi_encoder,
1211};
1212
1213static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = {
1214	.dpms = drm_helper_connector_dpms,
1215	.detect = amdgpu_connector_dvi_detect,
1216	.fill_modes = drm_helper_probe_single_connector_modes,
1217	.set_property = amdgpu_connector_set_property,
1218	.early_unregister = amdgpu_connector_unregister,
1219	.destroy = amdgpu_connector_destroy,
1220	.force = amdgpu_connector_dvi_force,
1221};
1222
1223static int amdgpu_connector_dp_get_modes(struct drm_connector *connector)
1224{
1225	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1226	struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1227	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1228	int ret;
1229
1230	if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1231	    (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1232		struct drm_display_mode *mode;
1233
1234		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1235			if (!amdgpu_dig_connector->edp_on)
1236				amdgpu_atombios_encoder_set_edp_panel_power(connector,
1237								     ATOM_TRANSMITTER_ACTION_POWER_ON);
1238			amdgpu_connector_get_edid(connector);
1239			ret = amdgpu_connector_ddc_get_modes(connector);
1240			if (!amdgpu_dig_connector->edp_on)
1241				amdgpu_atombios_encoder_set_edp_panel_power(connector,
1242								     ATOM_TRANSMITTER_ACTION_POWER_OFF);
1243		} else {
1244			/* need to setup ddc on the bridge */
1245			if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1246			    ENCODER_OBJECT_ID_NONE) {
1247				if (encoder)
1248					amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1249			}
1250			amdgpu_connector_get_edid(connector);
1251			ret = amdgpu_connector_ddc_get_modes(connector);
1252		}
1253
1254		if (ret > 0) {
1255			if (encoder) {
1256				amdgpu_connector_fixup_lcd_native_mode(encoder, connector);
1257				/* add scaled modes */
1258				amdgpu_connector_add_common_modes(encoder, connector);
1259			}
1260			return ret;
1261		}
1262
1263		if (!encoder)
1264			return 0;
1265
1266		/* we have no EDID modes */
1267		mode = amdgpu_connector_lcd_native_mode(encoder);
1268		if (mode) {
1269			ret = 1;
1270			drm_mode_probed_add(connector, mode);
1271			/* add the width/height from vbios tables if available */
1272			connector->display_info.width_mm = mode->width_mm;
1273			connector->display_info.height_mm = mode->height_mm;
1274			/* add scaled modes */
1275			amdgpu_connector_add_common_modes(encoder, connector);
1276		}
1277	} else {
1278		/* need to setup ddc on the bridge */
1279		if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1280			ENCODER_OBJECT_ID_NONE) {
1281			if (encoder)
1282				amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1283		}
1284		amdgpu_connector_get_edid(connector);
1285		ret = amdgpu_connector_ddc_get_modes(connector);
1286
1287		amdgpu_get_native_mode(connector);
1288	}
1289
1290	return ret;
1291}
1292
1293u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector)
1294{
1295	struct drm_encoder *encoder;
1296	struct amdgpu_encoder *amdgpu_encoder;
1297	int i;
1298
1299	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1300		if (connector->encoder_ids[i] == 0)
1301			break;
1302
1303		encoder = drm_encoder_find(connector->dev, NULL,
1304					connector->encoder_ids[i]);
1305		if (!encoder)
1306			continue;
1307
 
1308		amdgpu_encoder = to_amdgpu_encoder(encoder);
1309
1310		switch (amdgpu_encoder->encoder_id) {
1311		case ENCODER_OBJECT_ID_TRAVIS:
1312		case ENCODER_OBJECT_ID_NUTMEG:
1313			return amdgpu_encoder->encoder_id;
1314		default:
1315			break;
1316		}
1317	}
1318
1319	return ENCODER_OBJECT_ID_NONE;
1320}
1321
1322static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector)
1323{
1324	struct drm_encoder *encoder;
1325	struct amdgpu_encoder *amdgpu_encoder;
1326	int i;
1327	bool found = false;
1328
1329	for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
1330		if (connector->encoder_ids[i] == 0)
1331			break;
1332		encoder = drm_encoder_find(connector->dev, NULL,
1333					connector->encoder_ids[i]);
1334		if (!encoder)
1335			continue;
1336
1337		amdgpu_encoder = to_amdgpu_encoder(encoder);
1338		if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
1339			found = true;
1340	}
1341
1342	return found;
1343}
1344
1345bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector)
1346{
1347	struct drm_device *dev = connector->dev;
1348	struct amdgpu_device *adev = dev->dev_private;
1349
1350	if ((adev->clock.default_dispclk >= 53900) &&
1351	    amdgpu_connector_encoder_is_hbr2(connector)) {
1352		return true;
1353	}
1354
1355	return false;
1356}
1357
1358static enum drm_connector_status
1359amdgpu_connector_dp_detect(struct drm_connector *connector, bool force)
1360{
1361	struct drm_device *dev = connector->dev;
1362	struct amdgpu_device *adev = dev->dev_private;
1363	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1364	enum drm_connector_status ret = connector_status_disconnected;
1365	struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1366	struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1367	int r;
1368
1369	if (!drm_kms_helper_is_poll_worker()) {
1370		r = pm_runtime_get_sync(connector->dev->dev);
1371		if (r < 0)
 
1372			return connector_status_disconnected;
 
1373	}
1374
1375	if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) {
1376		ret = connector->status;
1377		goto out;
1378	}
1379
1380	amdgpu_connector_free_edid(connector);
1381
1382	if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1383	    (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1384		if (encoder) {
1385			struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1386			struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1387
1388			/* check if panel is valid */
1389			if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
1390				ret = connector_status_connected;
1391		}
1392		/* eDP is always DP */
1393		amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1394		if (!amdgpu_dig_connector->edp_on)
1395			amdgpu_atombios_encoder_set_edp_panel_power(connector,
1396							     ATOM_TRANSMITTER_ACTION_POWER_ON);
1397		if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1398			ret = connector_status_connected;
1399		if (!amdgpu_dig_connector->edp_on)
1400			amdgpu_atombios_encoder_set_edp_panel_power(connector,
1401							     ATOM_TRANSMITTER_ACTION_POWER_OFF);
1402	} else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) !=
1403		   ENCODER_OBJECT_ID_NONE) {
1404		/* DP bridges are always DP */
1405		amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
1406		/* get the DPCD from the bridge */
1407		amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1408
1409		if (encoder) {
1410			/* setup ddc on the bridge */
1411			amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder);
1412			/* bridge chips are always aux */
1413			/* try DDC */
1414			if (amdgpu_display_ddc_probe(amdgpu_connector, true))
1415				ret = connector_status_connected;
1416			else if (amdgpu_connector->dac_load_detect) { /* try load detection */
1417				const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1418				ret = encoder_funcs->detect(encoder, connector);
1419			}
1420		}
1421	} else {
1422		amdgpu_dig_connector->dp_sink_type =
1423			amdgpu_atombios_dp_get_sinktype(amdgpu_connector);
1424		if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) {
1425			ret = connector_status_connected;
1426			if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
1427				amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
1428		} else {
1429			if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
1430				if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
1431					ret = connector_status_connected;
1432			} else {
1433				/* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */
1434				if (amdgpu_display_ddc_probe(amdgpu_connector,
1435							     false))
1436					ret = connector_status_connected;
1437			}
1438		}
1439	}
1440
1441	amdgpu_connector_update_scratch_regs(connector, ret);
1442out:
1443	if (!drm_kms_helper_is_poll_worker()) {
1444		pm_runtime_mark_last_busy(connector->dev->dev);
1445		pm_runtime_put_autosuspend(connector->dev->dev);
1446	}
1447
 
 
 
 
 
 
1448	return ret;
1449}
1450
1451static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector,
1452					   struct drm_display_mode *mode)
1453{
1454	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
1455	struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv;
1456
1457	/* XXX check mode bandwidth */
1458
1459	if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) ||
1460	    (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) {
1461		struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector);
1462
1463		if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
1464			return MODE_PANEL;
1465
1466		if (encoder) {
1467			struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1468			struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
1469
1470			/* AVIVO hardware supports downscaling modes larger than the panel
1471			 * to the panel size, but I'm not sure this is desirable.
1472			 */
1473			if ((mode->hdisplay > native_mode->hdisplay) ||
1474			    (mode->vdisplay > native_mode->vdisplay))
1475				return MODE_PANEL;
1476
1477			/* if scaling is disabled, block non-native modes */
1478			if (amdgpu_encoder->rmx_type == RMX_OFF) {
1479				if ((mode->hdisplay != native_mode->hdisplay) ||
1480				    (mode->vdisplay != native_mode->vdisplay))
1481					return MODE_PANEL;
1482			}
1483		}
1484		return MODE_OK;
1485	} else {
1486		if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1487		    (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
1488			return amdgpu_atombios_dp_mode_valid_helper(connector, mode);
1489		} else {
1490			if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) {
1491				/* HDMI 1.3+ supports max clock of 340 Mhz */
1492				if (mode->clock > 340000)
1493					return MODE_CLOCK_HIGH;
1494			} else {
1495				if (mode->clock > 165000)
1496					return MODE_CLOCK_HIGH;
1497			}
1498		}
1499	}
1500
1501	return MODE_OK;
1502}
1503
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1504static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = {
1505	.get_modes = amdgpu_connector_dp_get_modes,
1506	.mode_valid = amdgpu_connector_dp_mode_valid,
1507	.best_encoder = amdgpu_connector_dvi_encoder,
1508};
1509
1510static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
1511	.dpms = drm_helper_connector_dpms,
1512	.detect = amdgpu_connector_dp_detect,
1513	.fill_modes = drm_helper_probe_single_connector_modes,
1514	.set_property = amdgpu_connector_set_property,
1515	.early_unregister = amdgpu_connector_unregister,
1516	.destroy = amdgpu_connector_destroy,
1517	.force = amdgpu_connector_dvi_force,
 
1518};
1519
1520static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
1521	.dpms = drm_helper_connector_dpms,
1522	.detect = amdgpu_connector_dp_detect,
1523	.fill_modes = drm_helper_probe_single_connector_modes,
1524	.set_property = amdgpu_connector_set_lcd_property,
1525	.early_unregister = amdgpu_connector_unregister,
1526	.destroy = amdgpu_connector_destroy,
1527	.force = amdgpu_connector_dvi_force,
 
1528};
1529
1530void
1531amdgpu_connector_add(struct amdgpu_device *adev,
1532		      uint32_t connector_id,
1533		      uint32_t supported_device,
1534		      int connector_type,
1535		      struct amdgpu_i2c_bus_rec *i2c_bus,
1536		      uint16_t connector_object_id,
1537		      struct amdgpu_hpd *hpd,
1538		      struct amdgpu_router *router)
1539{
1540	struct drm_device *dev = adev->ddev;
1541	struct drm_connector *connector;
 
1542	struct amdgpu_connector *amdgpu_connector;
1543	struct amdgpu_connector_atom_dig *amdgpu_dig_connector;
1544	struct drm_encoder *encoder;
1545	struct amdgpu_encoder *amdgpu_encoder;
 
1546	uint32_t subpixel_order = SubPixelNone;
1547	bool shared_ddc = false;
1548	bool is_dp_bridge = false;
1549	bool has_aux = false;
1550
1551	if (connector_type == DRM_MODE_CONNECTOR_Unknown)
1552		return;
1553
1554	/* see if we already added it */
1555	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 
1556		amdgpu_connector = to_amdgpu_connector(connector);
1557		if (amdgpu_connector->connector_id == connector_id) {
1558			amdgpu_connector->devices |= supported_device;
 
1559			return;
1560		}
1561		if (amdgpu_connector->ddc_bus && i2c_bus->valid) {
1562			if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) {
1563				amdgpu_connector->shared_ddc = true;
1564				shared_ddc = true;
1565			}
1566			if (amdgpu_connector->router_bus && router->ddc_valid &&
1567			    (amdgpu_connector->router.router_id == router->router_id)) {
1568				amdgpu_connector->shared_ddc = false;
1569				shared_ddc = false;
1570			}
1571		}
1572	}
 
1573
1574	/* check if it's a dp bridge */
1575	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1576		amdgpu_encoder = to_amdgpu_encoder(encoder);
1577		if (amdgpu_encoder->devices & supported_device) {
1578			switch (amdgpu_encoder->encoder_id) {
1579			case ENCODER_OBJECT_ID_TRAVIS:
1580			case ENCODER_OBJECT_ID_NUTMEG:
1581				is_dp_bridge = true;
1582				break;
1583			default:
1584				break;
1585			}
1586		}
1587	}
1588
1589	amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
1590	if (!amdgpu_connector)
1591		return;
1592
1593	connector = &amdgpu_connector->base;
1594
1595	amdgpu_connector->connector_id = connector_id;
1596	amdgpu_connector->devices = supported_device;
1597	amdgpu_connector->shared_ddc = shared_ddc;
1598	amdgpu_connector->connector_object_id = connector_object_id;
1599	amdgpu_connector->hpd = *hpd;
1600
1601	amdgpu_connector->router = *router;
1602	if (router->ddc_valid || router->cd_valid) {
1603		amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info);
1604		if (!amdgpu_connector->router_bus)
1605			DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
1606	}
1607
1608	if (is_dp_bridge) {
1609		amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1610		if (!amdgpu_dig_connector)
1611			goto failed;
1612		amdgpu_connector->con_priv = amdgpu_dig_connector;
1613		if (i2c_bus->valid) {
1614			amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1615			if (amdgpu_connector->ddc_bus)
1616				has_aux = true;
1617			else
 
1618				DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
 
1619		}
1620		switch (connector_type) {
1621		case DRM_MODE_CONNECTOR_VGA:
1622		case DRM_MODE_CONNECTOR_DVIA:
1623		default:
1624			drm_connector_init(dev, &amdgpu_connector->base,
1625					   &amdgpu_connector_dp_funcs, connector_type);
 
 
1626			drm_connector_helper_add(&amdgpu_connector->base,
1627						 &amdgpu_connector_dp_helper_funcs);
1628			connector->interlace_allowed = true;
1629			connector->doublescan_allowed = true;
1630			amdgpu_connector->dac_load_detect = true;
1631			drm_object_attach_property(&amdgpu_connector->base.base,
1632						      adev->mode_info.load_detect_property,
1633						      1);
1634			drm_object_attach_property(&amdgpu_connector->base.base,
1635						   dev->mode_config.scaling_mode_property,
1636						   DRM_MODE_SCALE_NONE);
1637			break;
1638		case DRM_MODE_CONNECTOR_DVII:
1639		case DRM_MODE_CONNECTOR_DVID:
1640		case DRM_MODE_CONNECTOR_HDMIA:
1641		case DRM_MODE_CONNECTOR_HDMIB:
1642		case DRM_MODE_CONNECTOR_DisplayPort:
1643			drm_connector_init(dev, &amdgpu_connector->base,
1644					   &amdgpu_connector_dp_funcs, connector_type);
 
 
1645			drm_connector_helper_add(&amdgpu_connector->base,
1646						 &amdgpu_connector_dp_helper_funcs);
1647			drm_object_attach_property(&amdgpu_connector->base.base,
1648						      adev->mode_info.underscan_property,
1649						      UNDERSCAN_OFF);
1650			drm_object_attach_property(&amdgpu_connector->base.base,
1651						      adev->mode_info.underscan_hborder_property,
1652						      0);
1653			drm_object_attach_property(&amdgpu_connector->base.base,
1654						      adev->mode_info.underscan_vborder_property,
1655						      0);
1656
1657			drm_object_attach_property(&amdgpu_connector->base.base,
1658						   dev->mode_config.scaling_mode_property,
1659						   DRM_MODE_SCALE_NONE);
1660
1661			drm_object_attach_property(&amdgpu_connector->base.base,
1662						   adev->mode_info.dither_property,
1663						   AMDGPU_FMT_DITHER_DISABLE);
1664
1665			if (amdgpu_audio != 0)
1666				drm_object_attach_property(&amdgpu_connector->base.base,
1667							   adev->mode_info.audio_property,
1668							   AMDGPU_AUDIO_AUTO);
1669
1670			subpixel_order = SubPixelHorizontalRGB;
1671			connector->interlace_allowed = true;
1672			if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1673				connector->doublescan_allowed = true;
1674			else
1675				connector->doublescan_allowed = false;
1676			if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1677				amdgpu_connector->dac_load_detect = true;
1678				drm_object_attach_property(&amdgpu_connector->base.base,
1679							      adev->mode_info.load_detect_property,
1680							      1);
1681			}
1682			break;
1683		case DRM_MODE_CONNECTOR_LVDS:
1684		case DRM_MODE_CONNECTOR_eDP:
1685			drm_connector_init(dev, &amdgpu_connector->base,
1686					   &amdgpu_connector_edp_funcs, connector_type);
 
 
1687			drm_connector_helper_add(&amdgpu_connector->base,
1688						 &amdgpu_connector_dp_helper_funcs);
1689			drm_object_attach_property(&amdgpu_connector->base.base,
1690						      dev->mode_config.scaling_mode_property,
1691						      DRM_MODE_SCALE_FULLSCREEN);
1692			subpixel_order = SubPixelHorizontalRGB;
1693			connector->interlace_allowed = false;
1694			connector->doublescan_allowed = false;
1695			break;
1696		}
1697	} else {
1698		switch (connector_type) {
1699		case DRM_MODE_CONNECTOR_VGA:
1700			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1701			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1702			if (i2c_bus->valid) {
1703				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1704				if (!amdgpu_connector->ddc_bus)
1705					DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
 
 
1706			}
 
 
 
 
 
1707			amdgpu_connector->dac_load_detect = true;
1708			drm_object_attach_property(&amdgpu_connector->base.base,
1709						      adev->mode_info.load_detect_property,
1710						      1);
1711			drm_object_attach_property(&amdgpu_connector->base.base,
1712						   dev->mode_config.scaling_mode_property,
1713						   DRM_MODE_SCALE_NONE);
1714			/* no HPD on analog connectors */
1715			amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1716			connector->interlace_allowed = true;
1717			connector->doublescan_allowed = true;
1718			break;
1719		case DRM_MODE_CONNECTOR_DVIA:
1720			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type);
1721			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs);
1722			if (i2c_bus->valid) {
1723				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1724				if (!amdgpu_connector->ddc_bus)
1725					DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
 
 
1726			}
 
 
 
 
 
1727			amdgpu_connector->dac_load_detect = true;
1728			drm_object_attach_property(&amdgpu_connector->base.base,
1729						      adev->mode_info.load_detect_property,
1730						      1);
1731			drm_object_attach_property(&amdgpu_connector->base.base,
1732						   dev->mode_config.scaling_mode_property,
1733						   DRM_MODE_SCALE_NONE);
1734			/* no HPD on analog connectors */
1735			amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE;
1736			connector->interlace_allowed = true;
1737			connector->doublescan_allowed = true;
1738			break;
1739		case DRM_MODE_CONNECTOR_DVII:
1740		case DRM_MODE_CONNECTOR_DVID:
1741			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1742			if (!amdgpu_dig_connector)
1743				goto failed;
1744			amdgpu_connector->con_priv = amdgpu_dig_connector;
1745			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1746			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1747			if (i2c_bus->valid) {
1748				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1749				if (!amdgpu_connector->ddc_bus)
1750					DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
 
 
1751			}
 
 
 
 
 
1752			subpixel_order = SubPixelHorizontalRGB;
1753			drm_object_attach_property(&amdgpu_connector->base.base,
1754						      adev->mode_info.coherent_mode_property,
1755						      1);
1756			drm_object_attach_property(&amdgpu_connector->base.base,
1757						   adev->mode_info.underscan_property,
1758						   UNDERSCAN_OFF);
1759			drm_object_attach_property(&amdgpu_connector->base.base,
1760						   adev->mode_info.underscan_hborder_property,
1761						   0);
1762			drm_object_attach_property(&amdgpu_connector->base.base,
1763						   adev->mode_info.underscan_vborder_property,
1764						   0);
1765			drm_object_attach_property(&amdgpu_connector->base.base,
1766						   dev->mode_config.scaling_mode_property,
1767						   DRM_MODE_SCALE_NONE);
1768
1769			if (amdgpu_audio != 0) {
1770				drm_object_attach_property(&amdgpu_connector->base.base,
1771							   adev->mode_info.audio_property,
1772							   AMDGPU_AUDIO_AUTO);
1773			}
1774			drm_object_attach_property(&amdgpu_connector->base.base,
1775						   adev->mode_info.dither_property,
1776						   AMDGPU_FMT_DITHER_DISABLE);
1777			if (connector_type == DRM_MODE_CONNECTOR_DVII) {
1778				amdgpu_connector->dac_load_detect = true;
1779				drm_object_attach_property(&amdgpu_connector->base.base,
1780							   adev->mode_info.load_detect_property,
1781							   1);
1782			}
1783			connector->interlace_allowed = true;
1784			if (connector_type == DRM_MODE_CONNECTOR_DVII)
1785				connector->doublescan_allowed = true;
1786			else
1787				connector->doublescan_allowed = false;
1788			break;
1789		case DRM_MODE_CONNECTOR_HDMIA:
1790		case DRM_MODE_CONNECTOR_HDMIB:
1791			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1792			if (!amdgpu_dig_connector)
1793				goto failed;
1794			amdgpu_connector->con_priv = amdgpu_dig_connector;
1795			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type);
1796			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs);
1797			if (i2c_bus->valid) {
1798				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1799				if (!amdgpu_connector->ddc_bus)
1800					DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
 
 
1801			}
 
 
 
 
 
1802			drm_object_attach_property(&amdgpu_connector->base.base,
1803						      adev->mode_info.coherent_mode_property,
1804						      1);
1805			drm_object_attach_property(&amdgpu_connector->base.base,
1806						   adev->mode_info.underscan_property,
1807						   UNDERSCAN_OFF);
1808			drm_object_attach_property(&amdgpu_connector->base.base,
1809						   adev->mode_info.underscan_hborder_property,
1810						   0);
1811			drm_object_attach_property(&amdgpu_connector->base.base,
1812						   adev->mode_info.underscan_vborder_property,
1813						   0);
1814			drm_object_attach_property(&amdgpu_connector->base.base,
1815						   dev->mode_config.scaling_mode_property,
1816						   DRM_MODE_SCALE_NONE);
1817			if (amdgpu_audio != 0) {
1818				drm_object_attach_property(&amdgpu_connector->base.base,
1819							   adev->mode_info.audio_property,
1820							   AMDGPU_AUDIO_AUTO);
1821			}
1822			drm_object_attach_property(&amdgpu_connector->base.base,
1823						   adev->mode_info.dither_property,
1824						   AMDGPU_FMT_DITHER_DISABLE);
1825			subpixel_order = SubPixelHorizontalRGB;
1826			connector->interlace_allowed = true;
1827			if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
1828				connector->doublescan_allowed = true;
1829			else
1830				connector->doublescan_allowed = false;
1831			break;
1832		case DRM_MODE_CONNECTOR_DisplayPort:
1833			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1834			if (!amdgpu_dig_connector)
1835				goto failed;
1836			amdgpu_connector->con_priv = amdgpu_dig_connector;
1837			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type);
1838			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1839			if (i2c_bus->valid) {
1840				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1841				if (amdgpu_connector->ddc_bus)
1842					has_aux = true;
1843				else
 
1844					DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
 
1845			}
 
 
 
 
 
1846			subpixel_order = SubPixelHorizontalRGB;
1847			drm_object_attach_property(&amdgpu_connector->base.base,
1848						      adev->mode_info.coherent_mode_property,
1849						      1);
1850			drm_object_attach_property(&amdgpu_connector->base.base,
1851						   adev->mode_info.underscan_property,
1852						   UNDERSCAN_OFF);
1853			drm_object_attach_property(&amdgpu_connector->base.base,
1854						   adev->mode_info.underscan_hborder_property,
1855						   0);
1856			drm_object_attach_property(&amdgpu_connector->base.base,
1857						   adev->mode_info.underscan_vborder_property,
1858						   0);
1859			drm_object_attach_property(&amdgpu_connector->base.base,
1860						   dev->mode_config.scaling_mode_property,
1861						   DRM_MODE_SCALE_NONE);
1862			if (amdgpu_audio != 0) {
1863				drm_object_attach_property(&amdgpu_connector->base.base,
1864							   adev->mode_info.audio_property,
1865							   AMDGPU_AUDIO_AUTO);
1866			}
1867			drm_object_attach_property(&amdgpu_connector->base.base,
1868						   adev->mode_info.dither_property,
1869						   AMDGPU_FMT_DITHER_DISABLE);
1870			connector->interlace_allowed = true;
1871			/* in theory with a DP to VGA converter... */
1872			connector->doublescan_allowed = false;
1873			break;
1874		case DRM_MODE_CONNECTOR_eDP:
1875			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1876			if (!amdgpu_dig_connector)
1877				goto failed;
1878			amdgpu_connector->con_priv = amdgpu_dig_connector;
1879			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type);
1880			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs);
1881			if (i2c_bus->valid) {
1882				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1883				if (amdgpu_connector->ddc_bus)
1884					has_aux = true;
1885				else
 
1886					DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
 
1887			}
 
 
 
 
 
1888			drm_object_attach_property(&amdgpu_connector->base.base,
1889						      dev->mode_config.scaling_mode_property,
1890						      DRM_MODE_SCALE_FULLSCREEN);
1891			subpixel_order = SubPixelHorizontalRGB;
1892			connector->interlace_allowed = false;
1893			connector->doublescan_allowed = false;
1894			break;
1895		case DRM_MODE_CONNECTOR_LVDS:
1896			amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL);
1897			if (!amdgpu_dig_connector)
1898				goto failed;
1899			amdgpu_connector->con_priv = amdgpu_dig_connector;
1900			drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type);
1901			drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs);
1902			if (i2c_bus->valid) {
1903				amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus);
1904				if (!amdgpu_connector->ddc_bus)
1905					DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
 
 
1906			}
 
 
 
 
 
1907			drm_object_attach_property(&amdgpu_connector->base.base,
1908						      dev->mode_config.scaling_mode_property,
1909						      DRM_MODE_SCALE_FULLSCREEN);
1910			subpixel_order = SubPixelHorizontalRGB;
1911			connector->interlace_allowed = false;
1912			connector->doublescan_allowed = false;
1913			break;
1914		}
1915	}
1916
1917	if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
1918		if (i2c_bus->valid) {
1919			connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1920			                    DRM_CONNECTOR_POLL_DISCONNECT;
1921		}
1922	} else
1923		connector->polled = DRM_CONNECTOR_POLL_HPD;
1924
1925	connector->display_info.subpixel_order = subpixel_order;
1926	drm_connector_register(connector);
1927
1928	if (has_aux)
1929		amdgpu_atombios_dp_aux_init(amdgpu_connector);
 
 
 
 
 
1930
1931	return;
1932
1933failed:
1934	drm_connector_cleanup(connector);
1935	kfree(connector);
1936}